CN113224031B - Chip RF packaging and RF modules - Google Patents
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- CN113224031B CN113224031B CN202010952572.5A CN202010952572A CN113224031B CN 113224031 B CN113224031 B CN 113224031B CN 202010952572 A CN202010952572 A CN 202010952572A CN 113224031 B CN113224031 B CN 113224031B
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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- H01L2223/64—Impedance arrangements
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- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
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Abstract
本公开提出一种芯片射频封装件和射频模块，所述芯片射频封装件包括：基板，包括第一腔、第一连接构件和第二连接构件、芯构件；射频集成电路(RFIC)，设置在所述基板的上表面上；以及第一前端集成电路(FEIC)，设置在所述第一腔中。所述芯构件包括芯绝缘层和贯穿所述芯绝缘层的芯过孔。所述第一连接构件具有其中堆叠有第一绝缘层和第一布线层的结构。所述第二连接构件具有其中堆叠有第二绝缘层和第二布线层的第二结构。所述RFIC输入或输出基础信号和具有比所述基础信号的频率高的频率的第一射频(RF)信号，并且所述第一FEIC输入或输出所述第一RF信号和第二RF信号。
The present disclosure proposes a chip radio frequency package and a radio frequency module, the chip radio frequency package comprising: a substrate including a first cavity, a first connecting member and a second connecting member, and a core member; a radio frequency integrated circuit (RFIC) disposed on the upper surface of the substrate; and a first front-end integrated circuit (FEIC) disposed in the first cavity. The core member includes a core insulating layer and a core via penetrating the core insulating layer. The first connecting member has a structure in which a first insulating layer and a first wiring layer are stacked. The second connecting member has a second structure in which a second insulating layer and a second wiring layer are stacked. The RFIC inputs or outputs a basic signal and a first radio frequency (RF) signal having a frequency higher than that of the basic signal, and the first FEIC inputs or outputs the first RF signal and the second RF signal.
Description
The present application claims the priority rights of korean patent application No. 10-2020-0013914 filed on 5 months of 2 months in 2020 and korean patent application No. 10-2020-0088717 filed on 17 months of 7 months in 2020, which are incorporated herein by reference in their entireties for all purposes.
Technical Field
The following description relates to a chip radio frequency package and a radio frequency module.
Background
Data traffic in mobile communication systems continues to grow rapidly each year. Systems supporting the real-time transmission of such rapidly growing data in wireless networks are being implemented. For example, content of systems such as internet of things (IoT) -based data, augmented Reality (AR), virtual Reality (VR), live VR/AR in combination with Social Networking Services (SNS), autonomous navigation, applications such as synchronized view (real-time video user transmission using ultra-small cameras), etc., may benefit from communications supporting the sending and receiving of large amounts of data (e.g., 5 th generation (5G) communications, millimeter wave (mmWave) communications, etc.).
Further, millimeter wave (mmWave) communication including 5 th generation (5G) communication is being implemented in communication systems.
Disclosure of Invention
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In one general aspect, a chip radio frequency package includes: a substrate including a first cavity, a first connection member, and a second connection member, and including a core member disposed between the first connection member and the second connection member; a Radio Frequency Integrated Circuit (RFIC) disposed on an upper surface of the substrate; and a first front-end integrated circuit (FEIC) disposed in the first cavity, wherein the core member includes a core insulating layer and a core via disposed through the core insulating layer, the first connection member has a first stacked structure in which at least one first insulating layer and at least one first wiring layer are alternately stacked and the at least one first wiring layer is electrically connected to the core via, the second connection member has a second stacked structure in which at least one second insulating layer and at least one second wiring layer are alternately stacked and the at least one second wiring layer is electrically connected to the core via, the RFIC is configured to input or output a base signal and a first Radio Frequency (RF) signal through the at least one second wiring layer, the first RF signal has a frequency higher than that of the base signal, and the first FEIC is configured to input or output the first signal and the second RF signal, the second signal having a power different from that of the first RF signal.
The first connection member is provided on a lower surface of the core member, and the second connection member is provided on an upper surface of the core member.
The chip radio frequency package may further include a third connection member having a third stacked structure in which at least one third insulating layer and at least one third wiring layer are alternately stacked, and the third connection member may be disposed on a lower surface of the first connection member, wherein the first FEIC may be disposed on an upper surface of the third connection member.
The first FEIC may be configured to input or output the first RF signal and the second RF signal in a downward direction.
The first connection member may be disposed below the core member, the second connection member is disposed above the core member, and the third connection member is disposed below the core member.
The first connection member may be disposed below the core member, and the second connection member may be disposed above the core member.
The first FEIC may be surrounded by the core member and the first connection member and disposed on a lower surface of the second connection member.
The horizontal width of the portion of the first cavity corresponding to the upper surface of the core member may be smaller than the horizontal width of the portion corresponding to the lower surface of the core member.
The substrate may further include a cavity cover layer, at least a portion of which is disposed on an upper surface of the first cavity, and the cavity cover layer is surrounded by the core member or the second connection member.
The cavity cover layer may be electrically connected to the RFIC.
The chip radio frequency package may further include a second FEIC, the second FEIC disposed in a second cavity of the substrate, wherein a portion of the cavity cover layer is disposed on an upper surface of the second cavity.
The chip radio frequency package may further include a second FEIC, the second FEIC being disposed in a second cavity of the core member.
The first and second chambers may be spaced apart from each other, and respective side surfaces of the first and second chambers may be inclined.
The second FEIC may be configured to input or output a third RF signal and a fourth RF signal, wherein the fourth RF signal has a power different from that of the third RF signal, and a frequency of the third RF signal and a frequency of the fourth RF signal may be different from a frequency of the first RF signal and a frequency of the second RF signal.
The second FEIC may be configured to receive a third RF signal, amplify the third RF signal and output a fourth RF signal, the first FEIC is configured to amplify the first RF signal and output the second RF signal, and the RFIC is configured to convert a base signal to the first RF signal and to convert the fourth RF signal to a base signal.
At least a portion of at least one of the first FEIC and the second FEIC may overlap the RFIC in a vertical direction.
In one general aspect, a radio frequency module includes: a first substrate including a first cavity, a first connection member, and a second connection member, and including a core member disposed between the first connection member and the second connection member; a Radio Frequency Integrated Circuit (RFIC) disposed on an upper surface of the first substrate; a first front-end integrated circuit (FEIC) disposed in the first cavity; a second substrate having an upper surface, the first substrate being disposed on the upper surface of the second substrate; and an electrical connection structure configured to form an electrical connection between the second substrate and the first substrate, wherein the core member includes a core insulating layer and a core via provided to penetrate the core insulating layer, the first connection member has a first stacked structure in which at least one first insulating layer and at least one first wiring layer are alternately stacked, and the at least one first wiring layer is electrically connected to the core via, the second connection member has a second stacked structure in which at least one second insulating layer and at least one second wiring layer are alternately stacked, and the at least one second wiring layer is electrically connected to the core via, the RFIC is configured to input or output a base signal and a first Radio Frequency (RF) signal through the at least one second wiring layer, the first RF signal has a frequency higher than that of the base signal, and the first FEIC is configured to input or output an RF signal having the same power as the first RF signal from or from the second substrate to the first RF signal.
The first connection member is provided on a lower surface of the core member, and the second connection member is provided on an upper surface of the core member.
The second substrate may include: a patch antenna pattern configured to transmit or receive the first RF signal or the second RF signal; and a feed via connected to the patch antenna pattern.
The radio frequency module may include a second FEIC, the second FEIC being disposed in a second cavity of the core member.
The radio frequency module may include an encapsulation portion encapsulating at least a portion of the RFIC on the upper surface of the first substrate.
The lower surface of the first substrate may be smaller than the upper surface of the second substrate.
In one general aspect, a radio frequency module includes: a substrate including a first cavity and a second cavity; a Radio Frequency Integrated Circuit (RFIC) configured to process a base signal and a first Radio Frequency (RF) signal; a first front-end integrated circuit (FEIC) disposed in the first cavity and configured to input or output the first Radio Frequency (RF) signal and a second RF signal; a second FEIC disposed in the second cavity and configured to input or output a third RF signal and a fourth RF signal, wherein fundamental frequencies of the first RF signal and the second RF signal are different from fundamental frequencies of the third RF signal and the fourth RF signal.
In one general aspect, a radio frequency module includes: a first substrate including a first connection member and a second connection member, and including a core member disposed between the first connection member and the second connection member and having a first cavity; a Radio Frequency Integrated Circuit (RFIC) disposed on an upper surface of the first substrate; a first front-end integrated circuit (FEIC) disposed in the first cavity; and a second substrate providing a disposition region of the first substrate, wherein the core member includes a core insulating layer and a core via disposed to penetrate the core insulating layer, the first connection member has a first stacked structure in which at least one first insulating layer and at least one first wiring layer are alternately stacked, and the at least one first wiring layer is electrically connected to the core via, the second connection member has a second stacked structure in which at least one second insulating layer and at least one second wiring layer are alternately stacked, and the at least one second wiring layer is electrically connected to the core via, the RFIC inputs or outputs a base signal and a first Radio Frequency (RF) signal through the at least one second wiring layer, the first RF signal has a frequency higher than a frequency of the base signal, and the first or output signal and the first RF signal have a power different from that of the first RF signal, and the second RF signal are disposed on an upper surface of the core member.
The radio frequency module may include an electrical connection structure electrically connected between the second substrate and the first substrate, wherein the first substrate is disposed on an upper surface of the second substrate.
The second substrate may include: a patch antenna pattern configured to transmit or receive the second RF signal; and a feed via configured to feed the patch antenna pattern.
The radio frequency module may include a chip antenna disposed on the second substrate and configured to transmit or receive the second RF signal and having a dielectric constant higher than that of the second substrate, wherein the second substrate includes a feed via configured to feed the chip antenna.
The radio frequency module may include a second FEIC, the second FEIC being disposed in a second cavity of the core member.
The second substrate may include: at least four patch antenna patterns configured to transmit or receive the second RF signal; and at least four feed vias configured to feed to corresponding ones of the at least four patch antenna patterns, respectively, wherein at least two of the at least four feed vias are electrically connected to the first FEIC and a remaining portion of the at least four feed vias are electrically connected to the second FEIC.
The radio frequency module may include: at least four chip antennas disposed on the second substrate and configured to transmit or receive the second RF signal and having a dielectric constant higher than that of the second substrate; and at least four feed vias configured to feed to corresponding ones of the at least four chip antennas, respectively, wherein at least two of the at least four feed vias are electrically connected to the first FEIC and a remaining portion of the at least four feed vias are electrically connected to the second FEIC.
The radio frequency module may include an encapsulation portion encapsulating at least a portion of the RFIC on the upper surface of the first substrate.
The lower surface of the first substrate may be smaller than the upper surface of the second substrate.
The first substrate may include a plurality of first substrates spaced apart from each other, the first FEIC being disposed on one of the plurality of first substrates, the radio frequency module further includes a second FEIC, the second FEIC being disposed on another of the plurality of first substrates, the second substrate including a plurality of second substrates spaced apart from each other, and each of the plurality of second substrates providing at least one of a first disposed region of a patch antenna pattern configured to transmit or receive the second RF signal and a second disposed region of a patch antenna configured to transmit or receive the second RF signal and having a dielectric constant higher than that of the second substrate.
The plurality of second substrates may include at least three second substrates spaced apart from each other, and at least one of the at least three second substrates is spaced apart from the plurality of first substrates.
In one general aspect, a radio frequency module includes: a first substrate including a first connection member and a second connection member, and including a core member disposed between the first connection member and the second connection member and having a first cavity; a first front-end integrated circuit (FEIC) disposed in the first cavity; a Radio Frequency Integrated Circuit (RFIC) electrically connected to said first FEIC; a base substrate providing a setting region of the first substrate; and a plurality of antenna modules disposed on the base substrate, spaced apart from each other, and electrically connected to the first FEIC, and configured to transmit or receive second Radio Frequency (RF) signals, respectively, wherein the core member includes a core insulation layer and a core via disposed to penetrate the core insulation layer, the first connection member has a first stacked structure in which at least one first insulation layer and at least one first wiring layer are alternately stacked, and the at least one first wiring layer is electrically connected to the core via, the second connection member has a second stacked structure in which at least one second insulation layer and at least one second wiring layer are alternately stacked, and the at least one second wiring layer is electrically connected to the core via, the RFIC inputs or outputs a base signal and a first RF signal, the first signal having a higher frequency than the first signal and the RF signal having a higher power than the first signal FEIC, and the RF signal having a first power than the first signal.
At least one antenna module of the plurality of antenna modules may include: a second substrate including a plurality of feed-through vias electrically connected to the base substrate; and a plurality of patch antenna patterns fed from corresponding ones of the plurality of feed vias Kong Kuidian.
At least one antenna module of the plurality of antenna modules may include: a second substrate including a plurality of feed-through holes electrically connected to the base substrate, and a plurality of chip antennas disposed on the second substrate and configured to transmit or receive the second RF signal and having a dielectric constant higher than that of the second substrate.
The radio frequency module may include a second FEIC, the second FEIC disposed in a second cavity of the core member, wherein the plurality of antenna modules includes at least three antenna modules, and at least one of the first FEIC and the second FEIC is electrically connected to at least two of the at least three antenna modules.
The plurality of antenna modules may be arranged to transmit or receive the second RF signal in directions different from each other.
The radio frequency module may include a communication modem disposed on the base substrate, wherein the base substrate provides a disposition region of the RFIC.
Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.
Drawings
1A-1D are side views illustrating an example chip radio frequency package in accordance with one or more embodiments;
2A-2C are side views illustrating an example chip radio frequency package in accordance with one or more embodiments;
FIG. 3 is a plan view illustrating an example chip radio frequency package in accordance with one or more embodiments;
Fig. 4A-4D are side views illustrating a process of manufacturing a chip radio frequency package in accordance with one or more embodiments;
fig. 5A and 5B are side views illustrating an example radio frequency module in accordance with one or more embodiments;
Fig. 6A is a side view illustrating a structure in which an RFIC is omitted in a radio frequency module according to an embodiment of the disclosure;
fig. 6B is a side view illustrating a structure in which a chip radio frequency package is combined (accumulated) with a second substrate in a radio frequency module according to an embodiment of the present disclosure;
fig. 6C is a side view illustrating a radio frequency module including a patch antenna according to an embodiment of the present disclosure;
Fig. 7A to 7C are side views illustrating a plurality of first substrates and a plurality of second substrates of a radio frequency module according to an embodiment of the present disclosure;
Fig. 8A and 8B are side views illustrating a radio frequency module including a plurality of antenna modules according to an embodiment of the present disclosure; and
Fig. 9 is a plan view illustrating an example arrangement of a radio frequency module in an electronic device in accordance with one or more embodiments.
Throughout the drawings and detailed description, identical reference numerals will be understood to refer to identical elements, features and structures unless otherwise described or provided. The figures may not be drawn to scale and the relative sizes, proportions, and depictions of elements in the figures may be exaggerated for clarity, illustration, and convenience.
Detailed Description
The following detailed description is provided to assist the reader in obtaining a thorough understanding of the methods, apparatus, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the present disclosure. For example, the order of operations described herein is merely an example and is not limited to the order set forth herein, but rather variations that will be apparent upon an understanding of the present disclosure may be made in addition to operations that must occur in a specific order. In addition, descriptions of features that are known after understanding the present disclosure may be omitted for clarity and conciseness.
The terminology used herein is for the purpose of describing various examples only and will not be limiting of the disclosure. Singular forms also are intended to include plural forms unless the context clearly indicates otherwise. The terms "comprises," "comprising," and "having" are intended to specify the presence of stated features, integers, operations, elements, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, operations, elements, and/or groups thereof.
In the entire specification, when an element (such as a layer, region or substrate) is described as being "on", "connected to" or "bonded to" another element, the element may be directly "on", directly "connected to" or directly "bonded to" the other element, or there may be one or more other elements interposed therebetween. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there may be no other element intervening elements present.
As used herein, the term "and/or" includes any one of the listed items of interest and any combination of any two or more.
Although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first member, first component, first region, first layer, or first portion referred to in the examples described herein may also be referred to as a second member, second component, second region, second layer, or second portion without departing from the teachings of the examples.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs after understanding the present disclosure. Terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
FIG. 1A is a side view illustrating an example chip radio frequency package in accordance with one or more embodiments.
Referring to fig. 1A, a chip radio frequency package 100a in accordance with one or more embodiments may include a Radio Frequency Integrated Circuit (RFIC) 110, a first Front End Integrated Circuit (FEIC) 120a, and a second FEIC b. It is noted herein that use of the term "may" with respect to an example or embodiment (e.g., with respect to what the example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such features, and that all examples and embodiments are not so limited.
The RFIC 110 may input and/or output a base signal and a first Radio Frequency (RF) signal having a frequency that is higher than the frequency of the base signal.
For example, the RFIC 110 may process a base signal (e.g., frequency conversion, filtering, phase control, etc.) to generate a first RF signal and process the first RF signal to generate the base signal.
The first FEIC a may input and/or output a first RF signal and a second RF signal having a power different from that of the first RF signal.
For example, the first FEIC a may amplify the first RF signal to generate the second RF signal and amplify the second RF signal to generate the first RF signal. In a non-limiting example, the amplified second RF signal may be transmitted remotely through an antenna, and the second RF signal received remotely from the antenna may be amplified through the first FEIC a.
In an example, the first FEIC a may include at least a portion of a power amplifier, a low-noise amplifier, and a transmit/receive switch. The power amplifier, the low noise amplifier, and the transmission/reception changeover switch may be implemented as a combined structure of a semiconductor transistor element and an impedance element, but are not limited thereto.
Since the first FEIC a may amplify the first RF signal and/or the second RF signal, the RFIC 110 may not include front-end amplification circuitry (e.g., power amplifier, low noise amplifier).
Since ensuring performance (e.g., power consumption, linearity characteristics, noise characteristics, size, gain, etc.) of the front-end amplification circuit may be more difficult than ensuring performance of circuits in the RFIC 110 that perform operations other than amplification, compatibility with respect to circuits in the RFIC 110 that perform operations other than amplification may be relatively low.
In an example, the front-end amplification circuit may be implemented as a type of IC (e.g., a compound semiconductor) other than a conventional Complementary Metal Oxide Semiconductor (CMOS) based IC, or may be configured to have an efficient structure for receiving the impedance of the passive element, or may be optimized for a particular desired performance to be implemented alone, thereby ensuring performance.
Accordingly, the chip radio frequency package 100a according to one or more embodiments may have a structure in which the first FEIC a performing the front-end amplification operation and the RFIC 110 performing operations other than the front-end amplification are separately implemented. As a result, the performance of the amplifying circuit and the performance of the circuit of the RFIC 110 that performs operations other than front-end amplification can be achieved.
Further, the power consumption and/or heat generation of the front-end amplification circuit may be greater than those of circuits of the RFIC 110 that perform operations other than front-end amplification.
The chip radio frequency package 100a according to one or more embodiments may have the following structure: the first FEIC a performing the front-end amplification operation and the RFIC 110 performing operations other than the front-end amplification are separately implemented, so that power consumption efficiency can be increased and heat generation paths can be more effectively dispersed.
The energy loss in transmitting the first RF signal and/or the second RF signal may increase as the power of the first RF signal and/or the second RF signal increases.
In an example in which the first FEIC a or the second FEIC b performing the front-end amplification operation and the RFIC 110 performing an operation other than the front-end amplification are separately implemented, since the first FEIC a or the second FEIC b may be electrically connected closer to the antenna, the electrical length of the transmission path of the finally amplified second RF signal to the antenna may be more easily shortened, and the energy efficiency of the chip radio frequency package 100a may be further improved.
In an example, although the overall size of the RFIC 110 and the first FEIC a may be greater than the size of the RFIC integrated with the front-end amplification circuitry, the chip radio frequency package 100a according to one or more embodiments may have a structure in which the RFIC 110 and the first FEIC a may be arranged in a compact manner.
Referring to fig. 1A, a chip radio frequency package 100a according to one or more embodiments may include a substrate, and the substrate may include a core member 160, a first connection member 170, and a second connection member 180.
In an example, the core member 160 may include a core insulating layer 161 and a core via 163 disposed to penetrate the core insulating layer 161.
In an example, the first connection member 170 may have a first stacked structure in which at least one first insulating layer 171 and at least one first wiring layer 172 are alternately stacked. The at least one first wiring layer 172 may be electrically connected to the core via 163, and may be disposed on a lower surface of the core member 160.
In an example, the first connection member 170 may have a structure accumulated in a downward direction of the core member 160. In other words, the first connection member 170 may be disposed under the core member 160. Accordingly, the first via 173, which may be included in the first connection member 170, may have a structure in which a width of a lower end thereof is longer than or greater than a width of an upper end thereof.
The second connection member 180 may have a second stacked structure in which at least one second insulating layer 181 and at least one second wiring layer 182 are alternately stacked. The at least one second wiring layer 182 may be electrically connected to the core via 163, and may be disposed on the upper surface of the core member 160.
In an example, the second connection member 180 may have a structure accumulated in an upward direction of the core member 160. In other words, the second connection member 180 may be disposed above the core member 160. Accordingly, the second via 183, which may be included in the second connection member 180, may have a structure in which the width of the upper end thereof is longer or greater than the width of the lower end thereof.
The RFIC 110 may be disposed on an upper surface of the second connection member 180 and may input and/or output a base signal and a first RF signal through the at least one second wiring layer 182.
The core member 160 and the first connection member 170 may surround the first cavity in which the first FEIC a is disposed in a horizontal direction (e.g., X-direction, Y-direction), and the second connection member 180 may be disposed to overlap the first cavity in a vertical direction (e.g., Z-direction). That is, the first cavity may have a concave structure having the same thickness as the substrate.
Accordingly, since the RFIC 110 and the first FEIC a may be disposed in a compact manner with respect to each other, the actual size of the chip radio frequency package 100a according to one or more embodiments may be reduced and may be less than or equal to the size of a chip radio frequency package implemented with an RFIC integrated with a front-end amplification circuit.
Further, since the second connection member 180 may be disposed between the RFIC 110 and the first FEIC a, electromagnetic isolation between the RFIC 110 and the first FEIC a may be improved.
Referring to fig. 1A, a chip radio frequency package 100a according to one or more embodiments may further include a third connection member 190 disposed on a lower surface of the first connection member 170.
The third connection member 190 may have a third stacked structure in which at least one third insulating layer 191 and at least one third wiring layer 192 are alternately stacked.
In an example, the third connection member 190 may have a structure accumulated in a downward direction of the core member 160. In other words, the third connection member 190 may be disposed under the core member 160 and under the first connection member. Accordingly, the third via 193, which may be included in the third connection member 190, may have a structure in which a width of a lower end thereof is longer or greater than a width of an upper end thereof.
A plurality of electrical connection structures 130 may be provided on a lower surface of the third connection member 190. In a non-limiting example, the plurality of electrical connection structures 130 may be implemented with solder balls, pads, or lands.
The first FEIC a may be disposed on an upper surface of the third connection member 190.
In an example, the first FEIC a may input or output the first RF signal and the second RF signal in a downward direction. Accordingly, since the wiring complexity of the second connection member 180 can be reduced, the second connection member 180 can stably provide an arrangement space of the wirings electrically connected to the RFIC 110. In addition, electromagnetic isolation between the RFIC 110 and the first FEIC a may be further improved.
The first electrical connection structure 131 of the plurality of electrical connection structures 130 may provide an electrical connection path of the RFIC 110 to the outside and the second electrical connection structure 132 of the plurality of electrical connection structures 130 may provide an electrical connection path of the first FEIC a to the outside.
Referring to fig. 1A, the chip radio frequency package 100a according to one or more embodiments may further include a cavity cover layer 151A, wherein at least a portion of the cavity cover layer 151A is disposed on an upper surface of the first cavity and is surrounded by the core member 160 or the second connection member 180 in a horizontal direction (e.g., an X-direction or a Y-direction).
The cavity cover layer 151a may serve as a barrier to stop a process of forming the first cavity. Thus, a difference between the height of the first cavity and the height of the first FEIC a may be reduced. Accordingly, since the first FEIC a and the RFIC 110 can be more compactly provided, the actual size of the chip radio frequency package 100a can be further reduced.
In an example, an adhesive layer 152a may be disposed between the cavity cover layer 151a and the first FEIC a such that the first FEIC a may be stably adhered to the lower surface of the cavity cover layer 151 a.
In a non-limiting example, the side surface of the first cavity may be sloped. That is, the inner walls facing the first FEIC a from the core member 160 and the first connection member 170 may be inclined. Specifically, in an example, the horizontal width of the portion of the first cavity corresponding to the upper surface of the core member 160 may be smaller than the horizontal width of the portion corresponding to the lower surface of the core member 160.
The inclined side surface of the first cavity may be formed due to an asymmetrical structure of the first cavity in the vertical direction in the substrate, which is caused by not forming the first cavity in the second connection member 180.
In an example, the first encapsulation 141 may be filled in a portion of the first cavity in which the first FEIC a is not disposed.
In an example, the second encapsulant 142a may encapsulate at least a portion of the RFIC110 on an upper surface of the second connection member 180. Accordingly, in an example, the chip radio frequency package 100a may be a standardized electronic component, and may have a structure that is easy to mass-produce, distribute, and use, and may protect the RFIC110 from external influences.
Referring to fig. 1A, a chip radio frequency package 100a in accordance with one or more embodiments may further include a second FEIC 120b.
The core member 160 and the first connection member 170 may surround the second cavity in which the second FEIC b may be disposed in a horizontal direction (e.g., an X-direction or a Y-direction), and the second connection member 180 may be disposed to overlap the second cavity in a vertical direction (e.g., a Z-direction). That is, the second cavity may have a structure recessed into the thickness of the substrate.
At least a portion of at least one of the first FEIC a and the second FEIC b may overlap with the RFIC 110 in a vertical direction (e.g., Z-direction).
In an example, the first FEIC a and the second FEIC b may be disposed in first and second cavities, respectively, that are spaced apart from one another. Accordingly, electromagnetic isolation between the first FEIC a and the second FEIC b may be improved, and each of the first FEIC a and the second FEIC b may be allowed to dissipate heat more effectively.
In an example, since the first and second cavities may be formed substantially simultaneously, the cavity cover layer 151a may be disposed to overlap both the first and second cavities in a vertical direction (e.g., a Z direction).
For example, since the second cavity may have the same shape as that of the first cavity, the side surface of the second cavity may be inclined.
When the total horizontal width of the first and second chambers is large with respect to the total horizontal width of the substrate, the structural stability of the substrate may be reduced, and warpage of the substrate may be increased.
When the first and second cavities have an asymmetric structure in the vertical direction in the substrate, the total horizontal width of the first and second cavities may be easily widened than when the first and second cavities are formed to penetrate the entire substrate.
Thus, the chip radio frequency package 100a according to one or more embodiments may stably include the first cavity and the second cavity even though it has a relatively small horizontal width, and may use the first FEIC a and the second FEIC b together even though it has a relatively small horizontal width.
The second FEIC b may input and/or output a third RF signal and a fourth RF signal, where the fourth RF signal may have a different power than the third RF signal.
In an example, the fundamental frequencies of the first and second RF signals input and/or output from the first FEIC a may be different from the fundamental frequencies of the third and fourth RF signals input and/or output from the second FEIC b.
That is, the chip radio frequency package 100a in accordance with one or more embodiments may support multi-band communication. Since the chip radio frequency package 100a may use the first FEIC a and the second FEIC b together, multi-band communication may be efficiently supported even though it has a relatively small horizontal width.
In an example, the first FEIC a may amplify the first RF signal to output the second RF signal and the second FEIC b may receive the third RF signal and amplify the third RF signal to output the fourth RF signal. The RFIC 110 may convert the base signal to a first RF signal and convert a fourth RF signal to a base signal.
That is, the first FEIC a may be used for signal transmission and the second FEIC b may be used for signal reception. Accordingly, since the first FEIC a and the second FEIC b may not include a switch for switching between transmission and reception, respectively, they may have a further reduced size. Accordingly, the size of the chip radio frequency package 100a may be further reduced.
Fig. 1B-1D are side views illustrating an example chip radio frequency package in accordance with one or more embodiments.
Referring to fig. 1B, an example chip radio frequency package 100B in accordance with one or more embodiments may include a second encapsulant 142B, and the second encapsulant 142B may have a thickness less than the thickness of the second encapsulant 142a shown in fig. 1A.
Referring to fig. 1C, an example chip radio frequency package 100C according to one or more embodiments may have a structure in which the second encapsulation parts 142a and 142B shown in fig. 1A and 1B, respectively, are omitted.
Referring to fig. 1D, an example chip radio frequency package 100D in accordance with one or more embodiments may include a third encapsulation 143 encapsulating the plurality of third electrical connection structures 133. The plurality of third electrical connection structures 133 may support the mounting of the RFIC 110 on the upper surface of the second connection member 180.
Fig. 2A-2C are side views illustrating an example chip radio frequency package in accordance with one or more embodiments.
Referring to fig. 2A, an example chip radio frequency package 100e in accordance with one or more embodiments may have a structure omitting the second FEIC b shown in fig. 1A.
Referring to fig. 2B, an example chip radio frequency package 100f in accordance with one or more embodiments may include second wiring layers 182a and 182B modified in the structure of at least one second wiring layer shown in fig. 1A, and may have a third wiring layer 192a modified in the structure of at least one third wiring layer shown in fig. 1A.
Referring to fig. 2C, an example chip radio frequency package 100g in accordance with one or more embodiments may include a cavity cover layer 151C electrically connected to at least one second via 183. That is, the cavity cover 151c may be electrically connected to the RFIC 110.
In an example, the cavity cover 151c may be in an electrically stable grounded state, providing ground to the RFIC 110. Since the cavity cap 151c may have a relatively wide horizontal width, the cavity cap 151c may have a more electrically stable state and may provide a more stable ground to the RFIC 110. In addition, since the cavity cover layer 151c is electrically stable in a grounded state, electromagnetic isolation between the RFIC 110 and the first FEIC a can be further improved.
Fig. 3 is a plan view illustrating a chip radio frequency package in accordance with one or more embodiments.
Referring to fig. 3, the core insulating layer 161 of the example chip radio frequency package 100a may surround the first FEIC a and the second FEIC b, respectively, and the example chip radio frequency package 100a may include a plurality of core vias 163.
Fig. 4A-4D are side views illustrating a process of manufacturing a chip radio frequency package in accordance with one or more embodiments.
Referring to fig. 4A, in a first operation 1001, a portion of the core member 1160a in which a core via is to be disposed may be removed.
Referring to fig. 4A, in a second operation 1002, a core via 1163 may be formed to penetrate through a core member 1160a, a cavity cap layer 1151 and a second wiring layer 1182 may be provided on an upper surface of the core member 1160a, and a first wiring layer 1172 may be provided on a lower surface of the core member 1160 a.
Referring to fig. 4A, in a third operation 1003, a first insulating layer 1171 may be disposed on a lower surface of the core member 1160a, a first via 1173 may be formed in the first insulating layer 1171, a second insulating layer 1181 may be disposed on an upper surface of the core member 1160a, and a second via 1183 may be formed on the second insulating layer 1181. Thus, some layers of the first connection member 1170a may be formed, and some layers of the second connection member 1180a may be formed.
Referring to fig. 4B, in the fourth operation 1004, the total thickness of each of the first insulating layer 1171 and the second insulating layer 1181 may be thicker than the total thickness of the first insulating layer 1171 and the second insulating layer 1181 shown in operation 1003 of fig. 4A, the first wiring layer 1172 and the second wiring layer 1182 may be further stacked than the stack of the first wiring layer 1172 and the second wiring layer 1182 shown in operation 1003 of fig. 4A, and the first via 1173 and the second via 1183 may be longer than the first via 1173 and the second via 1183 shown in operation 1003 of fig. 4A. Accordingly, the number of stacked layers of the first connection member 1170b may be increased, and the number of stacked layers of the second connection member 1180b may be increased.
Referring to fig. 4B, in a fifth operation 1005, a first cavity and a second cavity may be formed in the core member 1160B and the first connection member 1170 c. For example, the first and second cavities may be formed when a plurality of fine particles or laser light collide in the +z direction in a specific region of the core member 1160b and the first connection member 1170 c.
Referring to fig. 4B, in a sixth operation 1006, an adhesive layer 1152 may be disposed in the first and second chambers, and first FEIC a and second FEIC B may be disposed in the first and second chambers, respectively.
Referring to fig. 4C, in a seventh operation 1007, the first encapsulation 1141 may be filled in portions of the first and second cavities in which the respective first FEIC a and second FEIC b are not disposed.
Referring to fig. 4C, in the eighth operation 1008, a third insulating layer 1191a may be disposed on a lower surface of the first connection member 1170C, and the third insulating layer 1191a may have an arrangement space of third via holes 1193 a. Thus, some layers of the third connection member 1190a may be formed.
Referring to fig. 4D, in a ninth operation 1009, the total thickness of the third insulating layer 1191b may be thicker than the thickness of the third insulating layer 1191a of fig. 4C, and a third wiring layer 1192b and a third via 1193b may be formed in the third insulating layer 1191 b. Accordingly, the number of stacked layers of the third connection member 1190b may increase.
Referring to fig. 4D, in the tenth operation 1010, the total thickness of the third insulating layer 1191C may be thicker than the thickness of the third insulating layer 1191a of fig. 4C, and the third wiring layer 1192C and the third via 1193C may be further formed in the third insulating layer 1191C. Accordingly, the number of stacked layers of the third connection member 1190c may be further increased.
Fig. 5A and 5B are side views illustrating an example radio frequency module in accordance with one or more embodiments.
Referring to fig. 5A, an example radio frequency module may include a chip radio frequency package 100a and a second substrate 200a.
The second substrate 200a may have a structure in which the fourth insulating layer 201, the fourth wiring layer 202, and the fourth via hole 203 are combined, and may have a structure similar to that of a Printed Circuit Board (PCB). Further, the substrate including the core member, the first cavity, the first connection member, and the second connection member may be referred to as a first substrate by those skilled in the art as needed. In this case, the second encapsulation portion 142a may encapsulate at least a portion of the RFIC 110 on the upper surface of the first substrate.
When the number of stacked layers of the connection members of the chip rf package 100a increases, the number of the fourth insulating layer 201 and the fourth wiring layer 202 of the second substrate 200a may be reduced, so that the thickness of the second substrate 200a may be thinned.
The chip radio frequency package 100a may be mounted on the upper surface of the second substrate 200a by the first and second electrical connection structures, and may be electrically connected to the fourth wiring layer 202 and the fourth via 203.
The lower surface of the first substrate may be smaller than the upper surface of the second substrate 200 a. Specifically, the horizontal width of the chip rf package 100a may be smaller or less than the width of the upper surface of the second substrate 200 a. Thus, with respect to the second substrate 200a, the chip rf package 100a may be used as an electronic component.
A plurality of fourth electrical connection structures 230 may be disposed on the lower surface of the second substrate 200a and may be electrically connected to the fourth wiring layer 202 and the fourth via 203.
The plurality of fourth electrical connection structures 230 may support the mounting of the patch antenna, and the patch antenna may remotely transmit and/or receive the second RF signal. Further, a portion of the fourth plurality of electrical connection structures 230 may be used as input and/or output paths for the base signal. In particular, the first FEIC a may be configured to input or output the first and second RF signals from or to the second substrate 200 a.
Referring to fig. 5B, the second substrate 200B may further include a plurality of patch antenna patterns 210 and a plurality of feed vias 220, wherein the feed vias 220 may be connected to the plurality of patch antenna patterns 210.
The plurality of patch antenna patterns 210 may be formed together with the wiring layer of the second substrate 200b, may remotely transmit and/or receive the first RF signal or the second RF signal, and may be fed from the plurality of feed vias 220.
Fig. 6A is a side view illustrating a structure in which an RFIC is omitted in a radio frequency module according to an embodiment of the disclosure.
Referring to fig. 6A, the radio frequency module 300a according to an embodiment of the present disclosure may have a structure in which a chip radio frequency package 100h, in which an RFIC is omitted, is mounted on an upper surface of the second substrate 200 b.
That is, the placement position of the RFIC is not limited to the chip radio frequency package 100h. For example, the RFIC may be disposed on the second substrate 200b, or may be disposed on a base substrate that may be bonded to the upper surface of the chip radio frequency package 100h.
Fig. 6B is a side view illustrating a structure in which a chip rf package is combined (accumulated) with a second substrate in an rf module according to an embodiment of the present disclosure.
Referring to fig. 6B, the radio frequency module 300B according to an embodiment of the present disclosure may have a structure in which the chip radio frequency package 100i is combined (accumulated) with the second substrate 200 c.
The third connection member 190, the first connection member 170, the core member 160, and the second connection member 180 of the chip rf package 100i may be sequentially disposed on the second substrate 200 c. For example, the upper surface of the second substrate 200c and the chip radio frequency package 100i may be bonded to each other by an adhesive material.
The first FEIC a and the second FEIC b may be embedded in the bonding structure of the chip rf package 100i and the second substrate 200 c. Accordingly, the electrical length between the first FEIC a and second FEIC b and the patch antenna pattern 210 may be shorter, and the energy loss of the feed path may be further reduced. The feed path may include a feed via 220, a feed line 222, and a second feed via 223.
The number of patch antenna patterns 210 and the number of feed vias 220 may be four or more, respectively. The greater the number of patch antenna patterns 210, the higher the gain and maximum output of the radio frequency module 300b according to an embodiment of the present disclosure, and the larger the size of the radio frequency module 300b in the horizontal direction may be.
Since the gain and maximum output of the radio frequency module 300b may be increased due to the amplification of the first FEIC a and the second FEIC b, in case the gain and maximum output of the radio frequency module 300b are not changed, the number of patch antenna patterns 210 may be reduced due to at least one of the first FEIC a and the second FEIC b, thereby reducing the size of the radio frequency module 300b in the horizontal direction.
At least two of the at least four feed-through vias 220 may be electrically connected to the first FEIC a and the remainder thereof may be electrically connected to the second FEIC b.
Accordingly, since the horizontal distance in the feed path of the at least four patch antenna patterns 210 may be short, the electrical lengths between the first FEIC a and second FEIC b and the at least four patch antenna patterns 210 may be short, and the energy loss of the feed path may be further reduced.
Fig. 6C is a side view illustrating a radio frequency module including a patch antenna according to an embodiment of the present disclosure.
Referring to fig. 6C, the radio frequency module 300C according to an embodiment of the present disclosure may further include a chip antenna 240, and the chip antenna 240 may include a patch antenna pattern 241, a feed via 242, a dielectric layer 243, and an electrical connection structure 244.
The dielectric layer 243 may have a dielectric constant higher than that of the fourth insulating layer 201 of the second substrate 200 c. For example, the dielectric layer 243 may be made of ceramic, and thus has a relatively high dielectric constant.
Since the chip antenna 240 is separately manufactured for the remaining structure of the radio frequency module 300c and may be disposed on the radio frequency module 300c, the dielectric layer 243 may be made of a material (e.g., prepreg) different from that of the fourth insulating layer 201 of the second substrate 200c and may be implemented in a method selected from more diversified and free methods than the implementation method of the fourth insulating layer 201.
Thus, the patch antenna 240 may have improved antenna performance (e.g., gain, bandwidth, maximum output, and polarization efficiency) without changing size.
For example, the dielectric layer 243 may be composed of a material having a relatively high dielectric constant, such as a ceramic-based material (such as low temperature co-fired ceramic (LTCC)) or a glass-based material, or a material having a relatively low dielectric loss tangent (such as polytetrafluoroethylene), and may be configured to have a higher dielectric constant or a higher durability by further including at least one of magnesium (Mg), silicon (Si), aluminum (Al), calcium (Ca), and titanium (Ti). For example, the dielectric layer 243 may include Mg 2SiO4、MgAlO4 and CaTiO 3.
The number of dielectric layers 243 may be two or more. The patch antenna pattern 241 may be disposed between the plurality of dielectric layers 243. For example, the plurality of dielectric layers 243 may be bonded to one another by a bonding material (e.g., a bonding polymer).
The patch antenna pattern 241 and the feed via 242 may be implemented in the same manner as the implementation of the patch antenna pattern and the feed via shown in fig. 6B, and the electrical connection structure 244 may be implemented in the same manner as the implementation of the electrical connection structure shown in fig. 1A. The feed via 242 may be fed from the feed via of the second substrate 200c and may be electrically connected to the first FEIC a and the second FEIC b.
The number of patch antennas 240 may be four or more. As the number of chip antennas 240 increases, the gain and maximum output of the radio frequency module 300c according to the embodiment of the present disclosure may increase, and the size of the radio frequency module 300c in the horizontal direction may increase.
Since the gain and maximum output of the radio frequency module 300c may be increased due to the amplification of the first FEIC a and the second FEIC b, the number of patch antennas 240 may be reduced due to at least one of the first FEIC a and the second FEIC b, with the gain and maximum output of the radio frequency module 300c unchanged, thereby reducing the size of the radio frequency module 300c in the horizontal direction.
At least two of the at least four patch antennas 240 may be electrically connected to the first FEIC a and the remainder thereof may be electrically connected to the second FEIC b.
Accordingly, since the horizontal distance in the feed path of the at least four patch antennas 240 may be short, the electrical paths between the first FEIC a and second FEIC b and the at least four patch antennas 240 may be short, and the energy loss of the feed path may be further reduced.
Fig. 7A to 7C are side views illustrating a plurality of first substrates and a plurality of second substrates of a radio frequency module according to an embodiment of the present disclosure.
Referring to fig. 7A, the radio frequency module according to an embodiment of the present disclosure may be divided into two radio frequency modules 300d-1 and 300d-2.
That is, the first substrate including the third connection member 190, the first connection member 170, the core member 160, and the second connection member 180 may include a plurality of first substrates spaced apart from one another. The second substrate 200c may be formed using a plurality of second substrates spaced apart from each other.
Each of the plurality of second substrates may provide at least one of a set region of the patch antenna pattern 210 and a set region of the patch antenna, the patch antenna pattern 210 being configured to transmit or receive the second RF signal, the patch antenna being configured to transmit or receive the second RF signal, and having a dielectric constant higher than that of the second substrate 200c, in particular, a dielectric constant of a dielectric layer of the patch antenna is higher than that of an insulating layer of the second substrate 200 c.
Accordingly, the set positions of the patch antenna patterns 210 or the chip antennas of the radio frequency modules 300d-1 and 300d-2 can be more freely designed, and the formation directions of the radiation patterns of the radio frequency modules 300d-1 and 300d-2 for transmitting or receiving the second RF signals can be further diversified.
The first FEIC a and the second FEIC b may be disposed in corresponding first substrates among the plurality of first substrates, and may be electrically connected to the RFIC 110, respectively.
Accordingly, since the horizontal distance in the feed path of the at least four patch antenna patterns 210 may be short, the electrical lengths between the first FEIC a and second FEIC b and the at least four patch antenna patterns 210 may be short, and the energy loss of the feed path may be further reduced.
Referring to fig. 7B, the radio frequency modules according to the embodiments of the present disclosure may be divided into four radio frequency modules 300d-1, 300d-2, 300d-3, and 300d-4, and may further include a third FEIC c and a fourth FEIC d. The first FEIC a, the second FEIC b, the third FEIC c, and the fourth FEIC d may be disposed in corresponding ones of the four first substrates and may be electrically connected to the RFIC 110, respectively.
Referring to fig. 7C, the radio frequency module according to the embodiment of the present disclosure may be divided into four radio frequency modules 300d-1, 300e-2, 300d-3, and 300e-4, and may have a structure in which the second FEIC and fourth FEIC are omitted. That is, each of the first FEIC a and the third FEIC c may be electrically connected to the plurality of patch antenna patterns 210 or the plurality of patch antennas provided on the plurality of second substrates. As another example, the radio frequency module may be divided into three, wherein the plurality of second substrates may include three second substrates spaced apart from each other, and at least one of the three second substrates may be spaced apart from the plurality of first substrates. That is, the plurality of second substrates may include at least three second substrates spaced apart from each other, and at least one of the at least three second substrates may be spaced apart from the plurality of first substrates.
Fig. 8A and 8B are side views illustrating a radio frequency module including a plurality of antenna modules according to an embodiment of the present disclosure.
Referring to fig. 8A, a radio frequency module 300f according to an embodiment of the present disclosure may include a chip radio frequency package 100a, a plurality of antenna modules 200-1, 200-2, 200-3, and 200-4, and a base substrate 600a.
The RFIC 110 may be omitted from the chip radio frequency package 100a depending on the design.
The plurality of antenna modules 200-1, 200-2, 200-3, and 200-4 may be disposed on the base substrate 600a and spaced apart from each other, and electrically connected to the first FEIC a and the second FEIC b, and may be configured to transmit or receive a second RF signal, respectively.
For example, the plurality of antenna modules 200-1, 200-2, 200-3, and 200-4 may include the second substrate shown in fig. 5B, 6A, 6B, 6C, 7A, 7B, and 7C, and may further include patch antenna patterns and/or patch antennas.
For example, the number of the plurality of antenna modules may be three or more, and the three or more antenna modules may be disposed to form radiation patterns in the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively, and at least one of the first FEIC a and the second FEIC b may be electrically connected to at least two of the three or more antenna modules.
The base substrate 600a may provide a placement area for the chip rf package 100 a. That is, the base substrate 600a may provide a disposition region of the first substrate including the third connection member 190, the first connection member 170, the core member 160, and the second connection member 180.
The arrangement positions of the plurality of antenna modules 200-1, 200-2, 200-3, and 200-4 on the base substrate 600a can be more freely designed, and the formation directions of the radiation patterns of the plurality of antenna modules 200-1, 200-2, 200-3, and 200-4 for transmitting and receiving the second RF signal can be further diversified.
The first FEIC a and the second FEIC b may be electrically connected to corresponding ones of the plurality of antenna modules 200-1, 200-2, 200-3, and 200-4. For example, the first FEIC a may be electrically connected to antenna module 1 200-1 and antenna module 2 200-2 and the second FEIC b may be electrically connected to antenna module 3200-3 and antenna module 4 200-4.
Accordingly, since the horizontal distance in the feed path of the plurality of antenna modules 200-1, 200-2, 200-3, and 200-4 may be short, the electrical lengths between the first FEIC a and second FEIC b and the plurality of antenna modules 200-1, 200-2, 200-3, and 200-4 may be short, and the energy loss of the feed path may be further reduced.
Referring to fig. 8B, the rf module 300j according to an embodiment of the present disclosure may have a structure in which a chip rf package is combined (accumulated) with a base substrate 600B. The RFIC 110 may be disposed on an upper surface of the base substrate 600 b.
The third connection member 190, the first connection member 170, the core member 160, and the second connection member 180 may be sequentially disposed on the base substrate 600 b. For example, one surface of the base substrate 600b and the chip radio frequency package may be bonded to each other by an adhesive material.
The first FEIC a and the second FEIC b may be embedded in a bonding structure of the chip rf package and the base substrate 600 b. Accordingly, the electrical length between the first FEIC a and the second FEIC b may be shorter, and the energy loss of the feed path may be further reduced.
Fig. 9 is a plan view illustrating an example arrangement of a radio frequency module in an electronic device in accordance with one or more embodiments.
Referring to fig. 9, example radio frequency modules 100a-1 and 100a-2 may be disposed adjacent a plurality of different edges of an electronic device 700, respectively.
In non-limiting examples, the electronic device 700 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop computer, a netbook computer, a television, a video game console, a smartwatch, an automotive component, or may be a device disposed in an autonomous vehicle, a robot, a smart phone, a tablet device, an Augmented Reality (AR) device, an internet of things (IoT) device, and the like, although the disclosure is not limited thereto and may correspond to various other types of devices.
The electronic device 700 may include a base substrate 600, and the base substrate 600 may further include a communication modem 610 and a baseband IC 620.
The communication modem 610 may include a memory chip, such as volatile memory or nonvolatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable and Programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FeRAM), and the like. Volatile memory can include Random Access Memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), and the like. In addition, the communication modem 610 may further include at least one of a Hard Disk Drive (HDD), a Solid State Drive (SSD), a Compact Flash (CF) card, a Secure Digital (SD) card, a Micro-secure digital (Micro-SD) card, a Micro-secure digital (Mini-SD) card, a super-speed (xD) card, and a memory stick.
The communication modem 610 may include the following chips to perform digital signal processing: an application processor chip such as a Central Processing Unit (CPU), a Graphics Processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc.; and logic chips such as analog-to-digital converters, application Specific Integrated Circuits (ASICs), and the like.
The baseband IC 620 may perform analog-to-digital conversion, amplification, filtering, and frequency conversion on the analog signal to generate a base signal. The base signals input/output from the baseband IC 620 may be transmitted to the radio frequency modules 100a-1 and 100a-2 through coaxial cables, and the coaxial cables may be electrically connected to the electrical connection structures of the radio frequency modules 100a-1 and 100 a-2.
For example, the frequency of the base signal may be within baseband and may be a frequency corresponding to an Intermediate Frequency (IF) (e.g., several GHz). The frequency of the RF signal (e.g., 28GHz, 39 GHz) may be higher than IF and may correspond to millimeter waves (mmWave).
The wiring layers, vias, and patterns disclosed herein may be formed using a metal material (e.g., a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc.), and may be formed according to a plating method such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), sputtering, subtractive, additive, semi-additive (SAP), modified semi-additive (MSAP), etc., but are not limited thereto.
The insulating layer disclosed herein may be realized by prepreg, FR4, thermosetting resin (such as epoxy resin), thermoplastic resin, or resin formed by impregnating these resins together with an inorganic filler in a core material (such as glass fiber, glass cloth, glass fabric, or the like) (for example, ABF (Ajinomoto Build-up Film) resin, bismaleimide Triazine (BT) resin, photosensitive dielectric (PID) resin, copper Clad Laminate (CCL), ceramic-based insulating material, or the like).
The RF signals mentioned herein may have a format according to the following protocol: wi-Fi (IEEE 802.11 family, etc.), worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long Term Evolution (LTE), ev-DO, hspa+, hsdpa+, hsupa+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols specified after the above protocols, but are not limited thereto. Further, the frequency of the RF signal (e.g., 24GHz, 28GHz, 36GHz, 39GHz, 60 GHz) is greater than the frequency of the IF signal (e.g., 2GHz, 5GHz, 10GHz, etc.).
As set forth in the examples, the chip radio frequency package and the radio frequency module may have improved processing performance (e.g., power efficiency, amplification efficiency, frequency conversion efficiency, heat dissipation efficiency, noise robustness, etc.) for radio frequency signals or the chip radio frequency package and the radio frequency module may have reduced dimensions.
While this disclosure includes particular examples, it will be apparent to those skilled in the art after understanding the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in descriptive sense only and not for purposes of limitation. The description of features or aspects in each example will be considered applicable to similar features or aspects in other examples. Suitable results may be obtained if the described techniques are performed in a different order and/or if components in the described systems, architectures, devices or circuits are combined in a different manner and/or replaced or added by other components or their equivalents. Thus, the scope of the disclosure is not to be limited by the specific embodiments, but by the claims and their equivalents, and all modifications within the scope of the claims and their equivalents are to be construed as being included in the disclosure.
Claims (38)
1. A chip radio frequency package, comprising:
a substrate including a first cavity, a first connection member, and a second connection member, and including a core member disposed between the first connection member and the second connection member;
a radio frequency integrated circuit disposed on an upper surface of the substrate; and
A first front-end integrated circuit disposed in the first cavity,
Wherein the core member includes a core insulating layer and a core via provided to penetrate the core insulating layer,
The first connection member has a first stacked structure in which at least one first insulating layer and at least one first wiring layer are alternately stacked, and the at least one first wiring layer is electrically connected to the core via,
The second connection member has a second stacked structure in which at least one second insulating layer and at least one second wiring layer are alternately stacked, and the at least one second wiring layer is electrically connected to the core via,
The radio frequency integrated circuit is configured to input or output a base signal and a first radio frequency signal through the at least one second wiring layer, the first radio frequency signal having a frequency higher than that of the base signal, and
The first front-end integrated circuit is configured to input or output the first radio frequency signal and a second radio frequency signal having a power different from a power of the first radio frequency signal.
2. The chip radio frequency package of claim 1, wherein the first connection member is disposed on a lower surface of the core member and the second connection member is disposed on an upper surface of the core member.
3. The chip radio frequency package according to claim 1, further comprising a third connection member having a third stacked structure in which at least one third insulating layer and at least one third wiring layer are alternately stacked, and the third connection member is provided on a lower surface of the first connection member,
Wherein the first front end integrated circuit is disposed on an upper surface of the third connection member.
4. The chip radio frequency package of claim 3, wherein the first front-end integrated circuit is configured to input or output the first radio frequency signal and the second radio frequency signal in a downward direction.
5. The chip radio frequency package of claim 3, wherein the first connection member is disposed below the core member,
The second connecting member is disposed above the core member, and
The third connecting member is disposed below the core member.
6. The chip radio frequency package of claim 2, wherein the first front end integrated circuit is surrounded by the core member and the first connection member and is disposed on a lower surface of the second connection member.
7. The chip radio frequency package of claim 1, wherein a horizontal width of a portion of the first cavity corresponding to the upper surface of the core member is less than a horizontal width of a portion of the first cavity corresponding to the lower surface of the core member.
8. The chip radio frequency package of claim 1, wherein the substrate further comprises a cavity cover layer, at least a portion of the cavity cover layer being disposed on an upper surface of the first cavity, and the cavity cover layer being surrounded by the core member or the second connection member.
9. The chip radio frequency package of claim 8, wherein the cavity cover layer is electrically connected to the radio frequency integrated circuit.
10. The chip radio frequency package of claim 8, further comprising a second front-end integrated circuit disposed in the second cavity of the substrate,
Wherein a portion of the cavity cover layer is disposed on an upper surface of the second cavity.
11. The chip radio frequency package of claim 1, further comprising a second front end integrated circuit disposed in a second cavity of the core member.
12. The chip radio frequency package of claim 11, wherein the first cavity and the second cavity are spaced apart from each other, and
The respective side surfaces of the first and second cavities are inclined.
13. The chip radio frequency package of claim 11, wherein the second front-end integrated circuit is configured to input or output a third radio frequency signal and a fourth radio frequency signal, wherein the fourth radio frequency signal has a different power than the third radio frequency signal, and
The frequency of the third radio frequency signal and the frequency of the fourth radio frequency signal are different from the frequency of the first radio frequency signal and the frequency of the second radio frequency signal.
14. The chip radio frequency package of claim 11, wherein the second front-end integrated circuit is configured to receive a third radio frequency signal, amplify the third radio frequency signal and output a fourth radio frequency signal,
The first front-end integrated circuit is configured to amplify the first radio frequency signal and output the second radio frequency signal, an
The radio frequency integrated circuit is configured to convert a base signal to the first radio frequency signal and to convert the fourth radio frequency signal to a base signal.
15. The chip radio frequency package of claim 11, wherein at least a portion of at least one of the first front-end integrated circuit and the second front-end integrated circuit overlaps the radio frequency integrated circuit in a vertical direction.
16. A radio frequency module, comprising:
a first substrate including a first cavity, a first connection member, and a second connection member, and including a core member disposed between the first connection member and the second connection member;
A radio frequency integrated circuit disposed on an upper surface of the first substrate;
a first front-end integrated circuit disposed in the first cavity;
A second substrate having an upper surface, the first substrate being disposed on the upper surface of the second substrate; and
An electrical connection structure configured to form an electrical connection between the second substrate and the first substrate,
Wherein the core member includes a core insulating layer and a core via provided to penetrate the core insulating layer, the first connection member has a first stacked structure in which at least one first insulating layer and at least one first wiring layer are alternately stacked, and the at least one first wiring layer is electrically connected to the core via,
The second connection member has a second stacked structure in which at least one second insulating layer and at least one second wiring layer are alternately stacked, and the at least one second wiring layer is electrically connected to the core via,
The radio frequency integrated circuit is configured to input or output a base signal and a first radio frequency signal through the at least one second wiring layer, the first radio frequency signal having a frequency higher than that of the base signal, and
The first front-end integrated circuit is configured to input or output the first and second radio frequency signals from or to the second substrate, the second radio frequency signal having a power different from a power of the first radio frequency signal.
17. The radio frequency module of claim 16, wherein the first connection member is disposed on a lower surface of the core member and the second connection member is disposed on an upper surface of the core member.
18. The radio frequency module of claim 16, wherein the second substrate comprises:
a patch antenna pattern configured to transmit or receive the first radio frequency signal or the second radio frequency signal; and
And a feed via connected to the patch antenna pattern.
19. The radio frequency module of claim 16, further comprising a second front end integrated circuit disposed in a second cavity of the core member.
20. The radio frequency module of claim 16, further comprising an encapsulation that encapsulates at least a portion of the radio frequency integrated circuit on an upper surface of the first substrate.
21. The radio frequency module of claim 16, wherein a lower surface of the first substrate is smaller than an upper surface of the second substrate.
22. A radio frequency module, comprising:
A first substrate including a first connection member and a second connection member, and including a core member disposed between the first connection member and the second connection member and having a first cavity;
A radio frequency integrated circuit disposed on an upper surface of the first substrate;
a first front-end integrated circuit disposed in the first cavity; and
A second substrate providing a setting area of the first substrate,
Wherein the core member includes a core insulating layer and a core via provided to penetrate the core insulating layer,
The first connection member has a first stacked structure in which at least one first insulating layer and at least one first wiring layer are alternately stacked, and is disposed on a lower surface of the core member, and the at least one first wiring layer is electrically connected to the core via,
The second connection member has a second stacked structure in which at least one second insulating layer and at least one second wiring layer are alternately stacked, and is disposed on an upper surface of the core member, and the at least one second wiring layer is electrically connected to the core via,
The radio frequency integrated circuit inputs or outputs a base signal and a first radio frequency signal having a frequency higher than that of the base signal through the at least one second wiring layer, and
The first front-end integrated circuit inputs or outputs the first radio frequency signal and a second radio frequency signal having a power different from a power of the first radio frequency signal.
23. The RF module of claim 22 further comprising an electrical connection structure electrically connected between the second substrate and the first substrate,
Wherein the first substrate is disposed on an upper surface of the second substrate.
24. The radio frequency module of claim 22, wherein the second substrate comprises:
A patch antenna pattern configured to transmit or receive the second radio frequency signal; and
And a feeding via configured to feed the patch antenna pattern.
25. The radio frequency module of claim 22, further comprising a patch antenna disposed on the second substrate and configured to transmit or receive the second radio frequency signal and having a dielectric constant higher than a dielectric constant of the second substrate,
Wherein the second substrate comprises a feed via configured to feed the chip antenna.
26. The radio frequency module of claim 22, further comprising a second front end integrated circuit disposed in a second cavity of the core member.
27. The radio frequency module of claim 26, wherein the second substrate comprises:
at least four patch antenna patterns configured to transmit or receive the second radio frequency signal; and
At least four feed vias configured to feed to corresponding ones of the at least four patch antenna patterns, respectively,
Wherein at least two of the at least four feed-through vias are electrically connected to the first front-end integrated circuit and a remaining portion of the at least four feed-through vias are electrically connected to the second front-end integrated circuit.
28. The radio frequency module of claim 26, the radio frequency module further comprising:
At least four patch antennas disposed on the second substrate and configured to transmit or receive the second radio frequency signal and having a dielectric constant higher than that of the second substrate; and
At least four feed vias configured to feed respective ones of the at least four patch antennas,
Wherein at least two of the at least four feed-through vias are electrically connected to the first front-end integrated circuit and a remaining portion of the at least four feed-through vias are electrically connected to the second front-end integrated circuit.
29. The radio frequency module of claim 22, further comprising an encapsulation that encapsulates at least a portion of the radio frequency integrated circuit on an upper surface of the first substrate.
30. The radio frequency module of claim 22, wherein a lower surface of the first substrate is smaller than an upper surface of the second substrate.
31. The radio frequency module of claim 22, wherein the first substrate comprises a plurality of first substrates spaced apart from one another,
The first front-end integrated circuit is disposed on one of the plurality of first substrates,
The radio frequency module further includes a second front-end integrated circuit disposed on another first substrate of the plurality of first substrates,
The second substrate includes a plurality of second substrates spaced apart from each other, an
Each of the plurality of second substrates provides at least one of a first set region of a patch antenna pattern configured to transmit or receive the second radio frequency signal and a second set region of a patch antenna configured to transmit or receive the second radio frequency signal and having a dielectric constant higher than that of the second substrate.
32. The radio frequency module of claim 31, wherein the plurality of second substrates comprises at least three second substrates spaced apart from one another, and
At least one of the at least three second substrates is spaced apart from the plurality of first substrates.
33. A radio frequency module, comprising:
A first substrate including a first connection member and a second connection member, and including a core member disposed between the first connection member and the second connection member and having a first cavity;
a first front-end integrated circuit disposed in the first cavity;
A radio frequency integrated circuit electrically connected to the first front end integrated circuit;
a base substrate providing a setting region of the first substrate; and
A plurality of antenna modules disposed on the base substrate, spaced apart from each other, and electrically connected to the first front-end integrated circuit, and configured to transmit or receive second radio frequency signals, respectively,
Wherein the core member includes a core insulating layer and a core via provided to penetrate the core insulating layer,
The first connection member has a first stacked structure in which at least one first insulating layer and at least one first wiring layer are alternately stacked, and is disposed on a lower surface of the core member, and the at least one first wiring layer is electrically connected to the core via,
The second connection member has a second stacked structure in which at least one second insulating layer and at least one second wiring layer are alternately stacked, and is disposed on an upper surface of the core member, and the at least one second wiring layer is electrically connected to the core via,
The RF integrated circuit inputs or outputs a base signal and a first RF signal having a frequency higher than that of the base signal, and
The first front-end integrated circuit inputs or outputs the first radio frequency signal and the second radio frequency signal, the second radio frequency signal having a power different from a power of the first radio frequency signal.
34. The radio frequency module of claim 33, wherein at least one of the plurality of antenna modules comprises:
A second substrate including a plurality of feed-through vias electrically connected to the base substrate; and
A plurality of patch antenna patterns fed through Kong Kuidian from a corresponding one of the plurality of feed vias.
35. The radio frequency module of claim 33, wherein at least one of the plurality of antenna modules comprises:
a second substrate including a plurality of feed-through holes electrically connected to the base substrate, and
A plurality of chip antennas disposed on the second substrate and configured to transmit or receive the second radio frequency signal and having a dielectric constant higher than that of the second substrate.
36. The RF module of claim 33 further comprising a second front end integrated circuit disposed in the second cavity of the core member,
Wherein the plurality of antenna modules includes at least three antenna modules, and
At least one of the first front-end integrated circuit and the second front-end integrated circuit is electrically connected to at least two antenna modules of the at least three antenna modules.
37. The radio frequency module of claim 33, wherein the plurality of antenna modules are arranged to transmit or receive the second radio frequency signal in directions different from each other.
38. The RF module of claim 37 further comprising a communication modem disposed on the base substrate,
Wherein the base substrate provides a setting area of the radio frequency integrated circuit.
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| KR20200013914 | 2020-02-05 | ||
| KR10-2020-0013914 | 2020-02-05 | ||
| KR10-2020-0088717 | 2020-07-17 | ||
| KR1020200088717A KR20210099989A (en) | 2020-02-05 | 2020-07-17 | Chip radio frequency package and radio frequency module |
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| JP2002344146A (en) * | 2001-05-15 | 2002-11-29 | Tdk Corp | High frequency module and its manufacturing method |
| KR102019354B1 (en) * | 2017-11-03 | 2019-09-09 | 삼성전자주식회사 | Antenna module |
| US11088468B2 (en) * | 2017-12-28 | 2021-08-10 | Samsung Electro-Mechanics Co., Ltd. | Antenna module |
| KR102017159B1 (en) * | 2018-03-12 | 2019-09-02 | 삼성전자주식회사 | Antenna module |
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