CN113205943A

CN113205943A - Laminated chip inductor

Info

Publication number: CN113205943A
Application number: CN202110591555.8A
Authority: CN
Inventors: 程桥; 肖倩; 刘季超; 徐鹏飞; 徐妍; 王智会
Original assignee: Shenzhen Zhenhua Ferrite and Ceramic Electronics Co Ltd
Current assignee: Shenzhen Zhenhua Ferrite and Ceramic Electronics Co Ltd
Priority date: 2021-05-28
Filing date: 2021-05-28
Publication date: 2021-08-03

Abstract

The invention belongs to the technical field of inductors, and particularly relates to a laminated chip inductor which comprises a plurality of insulating layers and a plurality of coil groups, wherein the insulating layers are sequentially laminated in the vertical direction, at least one coil group in each coil group comprises at least two pattern coils connected in parallel, the pattern coils are respectively and sequentially arranged on the laminated insulating layers, and the coil groups are connected in series. In the laminated chip inductor, the traditional design of a single coil is replaced by a mode of arranging the parallel-connected pattern coils to form a coil group, and then all the coil groups are connected in series, so that the laminated chip inductor structurally adopts a traditional laminated chip structure, and has the advantages of low cost, high yield and good reliability; through the structural improvement of the coil group, the high-frequency inductor similar to a winding is formed, namely the coil group with the same parallel connection quantity is arranged, so that the direct-current resistance is reduced by times, and the Q value is greatly improved.

Description

Laminated chip inductor

Technical Field

The invention belongs to the technical field of inductors, and particularly relates to a laminated chip inductor.

Background

The laminated chip inductor made of low dielectric constant ceramic has relatively high self-resonant frequency, and may be used in submicron wave to microwave band, and is suitable for mobile telephone to develop high frequency and network. In order to improve communication quality, transmission distance and transmission capacity, the transmission frequency of the current communication products is developing to high frequency, for example, 5G communication is actively being developed, and the highest communication frequency band reaches 5 GHz. Under the push of the trend of high frequency development of electronic and communication products, the application frequency of the inductor itself must be increased, and the current self-resonant frequency of the laminated ceramic inductor is increased from about 1GHz to over 6GHz, and is developing towards 10GHz and higher.

In a laminated chip inductor applied to a smart phone, a tablet terminal, a high frequency module, bluetooth, a W-LAN, and the like, in addition to a suitable inductance, a higher self-resonant frequency (SRF) needs to be ensured, and a higher quality factor (Q for short) is also required.

The conventional laminated chip inductor with a vertical structure is different from a conventional laminated chip inductor with a horizontal structure (shown in figure 1), a conductor layer printed on the laminated chip inductor with the vertical structure (shown in figures 2-3) is positioned on a plane determined by the length and the thickness (W multiplied by T) of the laminated chip inductor, although the structure can effectively improve the SRF of the laminated chip inductor, the winding area of a coil is small, the direct-current resistance is higher, and the Q value of a product is lower.

The Q value is an important index for measuring the inductor, and it represents the ratio of the energy stored in the inductor to the energy consumed by the inductor at a specific frequency.

Among them, the high-frequency inductor of the wire winding is the inductor applied to the high-frequency circuit with the highest Q value, but the cost is high, the yield is low, and the reliability is low.

The laminated chip high-frequency inductor can make up for the defects, has low cost, high yield and high structural reliability, but has low Q value and is only suitable for occasions with low electrical property requirements.

Disclosure of Invention

The invention aims to solve the technical problem of making up for the defects of the prior art and provides a high-frequency high-quality-factor vertical-structure laminated chip inductor.

In order to achieve the above object, an embodiment of the present invention provides a stacked chip inductor, which includes a plurality of insulating layers and a plurality of coil groups, wherein the insulating layers are sequentially stacked in a vertical direction, at least one of the coil groups includes at least two parallel pattern coils, the pattern coils are sequentially disposed on the stacked insulating layers, and the coil groups are connected in series.

Optionally, the shape of each pattern coil of each coil group is the same.

Optionally, the pattern coils of different coil groups are different in shape.

Optionally, the insulating layer is a ceramic sheet, and the pattern coil is disposed on the corresponding ceramic sheet in a printing manner.

Optionally, the ceramic pieces are rectangular parallelepiped shaped.

Optionally, the ceramic pieces in the shape of a cuboid have a length of 1.00 ± 0.15mm, a width of 0.5 ± 0.15mm and a thickness of 0.5 ± 0.15 mm.

Optionally, a pitch between adjacent ones of the pattern coils is 10 μm.

Optionally, the pattern coil has a width of 80 μm and a thickness of 15 μm.

Optionally, in each of the coil sets, the number of the pattern coils of at least two of the coil sets is the same.

Optionally, in each of the coil sets, the number of the pattern coils of at least two of the coil sets is different.

One or more technical solutions in the multilayer chip inductor provided by the embodiment of the present invention at least have one of the following technical effects: in the laminated chip inductor, the traditional design of a single coil is replaced by a mode of arranging the parallel-connected pattern coils to form a coil group, and then all the coil groups are connected in series, so that the laminated chip inductor structurally adopts a traditional laminated chip structure, and has the advantages of low cost, high yield and good reliability; through the structural improvement of the coil group, the high-frequency inductor similar to a winding is formed, namely the coil group with the same parallel connection quantity is arranged, so that the direct-current resistance is reduced by times, and the Q value is greatly improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a front view of a conventional horizontal type stacked chip inductor.

Fig. 2 is a front view of a conventional vertical stacked chip inductor.

Fig. 3 is an exploded view of the vertical stacked chip inductor in fig. 2.

Fig. 4 is a schematic perspective view of a stacked chip inductor according to an embodiment of the present invention.

Fig. 5 is a front view of a stacked chip inductor according to an embodiment of the present invention.

Fig. 6 is a top view of a stacked chip inductor according to an embodiment of the present invention.

Fig. 7 is an exploded view of the stacked chip inductor of fig. 4.

Wherein, in the figures, the respective reference numerals:

1-electrode 2-insulating layer 3-coil group

3-aa, 3-ab, 3-ac, 3-ad, 3-ae, 3-af, 3-ag-pattern coils.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to fig. 1-7 are exemplary and intended to be used to illustrate embodiments of the invention, and should not be construed as limiting the invention.

In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the embodiments of the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless specifically limited otherwise.

In the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. Specific meanings of the above terms in the embodiments of the present invention can be understood by those of ordinary skill in the art according to specific situations.

In an embodiment of the present invention, as shown in fig. 1 to 2, a stacked chip inductor is provided, which includes a plurality of insulating layers 2 and a plurality of coil sets 3, each of the insulating layers 2 is sequentially stacked in a vertical direction, at least one of the coil sets 3 in each of the coil sets 3 includes at least two parallel-connected pattern coils 3-b/3-c/3-d/3-e/3-f/3-g, each of the pattern coils 3-a/3-b/3-c/3-d/3-e/3-f/3-g is sequentially disposed on each of the stacked insulating layers 2, and each of the coil sets 3 is connected in series. The coil group 3 is formed by pattern coils 3-a/3-b/3-c/3-d/3-e/3-f/3-g and is connected with the electrodes 1 at two ends outside the laminated chip inductor to form a complete loop.

In the laminated chip inductor provided by the embodiment of the invention, the traditional design of a single coil is replaced by a mode of arranging the pattern coils 3-b/3-c/3-d/3-e/3-f/3-g connected in parallel to form a coil group 3, and then all the coil groups 3 are connected in series, so that the structure of the laminated chip inductor adopts a traditional laminated chip structure, and the laminated chip inductor is low in cost, high in yield and good in reliability; through the structural improvement of the coil group 3, a high-frequency inductor similar to a winding is formed, namely the coil group 3 with the same parallel connection quantity is arranged, so that the direct current resistance is reduced by times, and the Q value is greatly improved.

The laminated chip inductor provided by the embodiment of the invention is based on the fact that the Q value is the ratio of the stored energy to the consumed energy of the inductor, so that the Q value needs to be greatly improved, and the loss of the inductance can be reduced as much as possible by optimizing the structure of the laminated chip inductor. In the frequency range of 0-3GHz, the resistive loss of the conductive electrode 1 is the main loss, so the focus of the embodiment of the invention is to reduce the resistive loss of the conductive electrode 1, namely, the conductive electrode is connected in a parallel mode by two or more pattern coils 3-b/3-c/3-d/3-e/3-f/3-g in the coil group 3.

In another embodiment of the present invention, as shown in FIGS. 1-2, the pattern coils 3-b/3-c/3-d/3-e/3-f/3-g of each coil set 3 have the same shape. Specifically, each pattern coil 3-a of a single coil group 3 is designed to be the same, which facilitates the manufacture thereof, i.e. at least one same pattern coil 3-b/3-c/3-d/3-e/3-f/3-g coil group 3 is added to form one coil group 3 on the basis of the original one coil, and the pattern coils 3-b/3-c/3-d/3-e/3-f/3-g of the same group need to be connected in parallel.

Further, the high-frequency high-quality-factor multilayer chip inductor provided by the embodiment of the invention meets the requirement of the length and width of the multilayer chip inductor with the conventional size in the industry, for example, the length of the multilayer chip inductor with the specification of 1005 metric (British 0402) is 1.00 +/-0.15 mm, the width of the multilayer chip inductor with the specification of 0.50 +/-0.15 mm, the length of the multilayer chip inductor with the specification of 1608 metric (British 0603) is 1.60 +/-0.15 mm, and the width of the multilayer chip inductor with the specification of 0.80 +/-0.15 mm.

In another embodiment of the present invention, as shown in FIGS. 1-2, the pattern coils 3-b/3-c/3-d/3-e/3-f/3-g of different coil sets 3 have different shapes. Specifically, by designing the shapes of the pattern coils 3-a of the respective groups of coil groups 3 to be different, the respective coil groups 3 after being stacked can be made to form winding groups that meet the requirements, so that it can satisfy the requirements for the Q value. And, also makes the design of high frequency high quality factor laminated chip inductor more flexible.

In another embodiment of the present invention, as shown in fig. 1 to 2, the insulation layer 2 is a ceramic sheet, and the pattern coils 3-a/3-b/3-c/3-d/3-e/3-f/3-g are disposed on the corresponding ceramic sheet by printing. The pattern coils 3-a/3-b/3-c/3-d/3-e/3-f/3-g are processed in a printing mode, so that the pattern coils are convenient and efficient, and the pattern coils are more stably combined with the porcelain piece.

In another embodiment of the present invention, as shown in fig. 1 to 2, the ceramic pieces have a rectangular parallelepiped shape. The rectangular shape is regular and consistent, which is beneficial to production and processing.

In another embodiment of the present invention, as shown in fig. 1 to 2, the ceramic pieces in the rectangular parallelepiped shape have a length of 1.00 ± 0.15mm, a width of 0.5 ± 0.15mm, and a thickness of 0.5 ± 0.15 mm. The set specification of the porcelain body piece is the specification of the porcelain body piece of the conventional vertical laminated chip inductor, namely, the specification of the porcelain body piece does not need to be changed, the specification of the original porcelain body piece is utilized, the production mode does not need to be changed, and the production cost is reduced.

In another embodiment of the present invention, as shown in FIGS. 1-2, the distance between adjacent pattern coils 3-a/3-b/3-c/3-d/3-e/3-f/3-g is 10 μm.

In another embodiment of the present invention, as shown in FIGS. 1 to 2, the pattern coil 3-a/3-b/3-c/3-d/3-e/3-f/3-g has a width of 80 μm and a thickness of 15 μm.

In another embodiment of the present invention, as shown in fig. 1-2, in each of the coil sets 3, at least two of the coil sets 3 have the same number of pattern coils 3-b/3-c/3-d/3-e/3-f/3-g. That is, in the plurality of coil sets 3, the number of the pattern coils 3-b/3-c/3-d/3-e/3-f/3-g of the coil set 3 of two of the plurality of coil sets is the same, for example, two pattern coils 3-b of the first coil set 3 and two pattern coils 3-c of the second coil set 3.

In another embodiment of the present invention, as shown in fig. 1 to 2, in each coil set 3, at least two coil sets 3 have different numbers of pattern coils 3-b/3-c/3-d/3-e/3-f/3-g. That is, in the multiple coil sets 3, the number of the pattern coils 3-b/3-c/3-d/3-e/3-f/3-g of the two coil sets 3 is different, for example, two pattern coils 3-b of the first coil set 3 and three pattern coils 3-c/3-d/3-e/3-f/3-g of the second coil set 3 (not shown).

In other embodiments, the number of repetitions of the different pattern coils 3-b/3-c/3-d/3-e/3-f/3-g may not be uniform.

The present invention is not limited to the above-described embodiments, and design changes can be made without departing from the scope of the present invention. For example, the number of times the pattern of the different electrodes 1 of the first embodiment is repeated may not be uniform.

The following is illustrated by way of comparative examples:

first comparative example:

the traditional high stray capacitance of the horizontal inductor shown in fig. 1 results in low SRF of the product, so that the laminated chip inductor (shown in fig. 2-3) with a vertical structure appears in the market, and the mode can effectively reduce the internal stray capacitance of the product and improve the SRF of the product. However, the multilayer inductor with this structure has a small coil surrounding area and a high direct current resistance, resulting in a low Q value of the inductor.

Fig. 2 to 3 show a common vertical structure laminated chip inductor, in which the inner coil is formed by connecting coils of seven patterns, i.e., 3-a, 3-b, 3-c, 3-d, 3-e, 3-f, and 3-g, in series, the width of the electrode 1 is 50um, the thickness of the electrode 1 is 15um, and the vertical distance between the patterns of the electrode 1 is 10um, and the simulation results are shown in table 1 by using three-dimensional electromagnetic field simulation software.

The first embodiment:

fig. 4 to 7 are schematic diagrams of a first embodiment of the present invention, except for the 3-a electrode 1 pattern, each electrode 1 pattern of 3-b, 3-c, 3-d, 3-e, 3-f, and 3-g is connected in parallel with N (N is 1) identical coil patterns on the original basis, so that the resistance of the inductor can be effectively reduced on the original basis, the Q value of the multilayer chip inductor can be increased, the width and thickness of the electrode 1, and the vertical spacing of the electrode 1 patterns can be kept unchanged, and a simulation result is shown in table 1 below by using three-dimensional electromagnetic field simulation software. The method can not only ensure that the SRF of the laminated chip inductor is not reduced, but also effectively improve the Q value of the product.

Second comparative example + second embodiment:

the structure is consistent with the above mode, only the arrangement sequence and the number of the patterns of the inner electrode 1 are different, and the comparison result is detailed in table 2.

The comparative analysis of tables 1 to 2 shows that the Q value of the high-frequency high-quality-factor vertical laminated chip inductor of the embodiment of the invention is greatly higher than that of the common vertical laminated chip inductor in the whole application frequency band.

TABLE 1

TABLE 2

In summary, the laminated chip inductor of the embodiment of the invention is a laminated chip inductor with a high-frequency high-quality-factor vertical structure, and the Q value of the laminated chip inductor is obviously improved relative to that of a laminated chip inductor with a common vertical structure pair in an application frequency band. The material and the manufacturing process of the laminated chip inductor are the same as those of the existing common laminated chip inductor, and the coil structure design is different, so the manufacturing cost is basically equal to that of the common laminated chip inductor.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A laminated chip inductor, characterized by: the coil comprises a plurality of insulating layers and a plurality of coil groups, wherein the insulating layers are sequentially stacked in the vertical direction, each coil group comprises at least two parallel-connected pattern coils, each pattern coil is sequentially arranged on each stacked insulating layer, and the coil groups are connected in series.

2. The laminated chip inductor of claim 1, wherein: the shape of each pattern coil of each coil group is the same.

3. The laminated chip inductor of claim 1, wherein: the pattern coils of different coil groups are different in shape.

4. The laminated chip inductor of claim 1, wherein: the insulating layer is a porcelain body piece, and the pattern coils are arranged on the corresponding porcelain body pieces in a printing mode.

5. The laminated chip inductor of claim 4, wherein: the porcelain piece is cuboid.

6. The laminated chip inductor of claim 5, wherein: the length of the cuboid-shaped porcelain piece is 1.00 +/-0.15 mm, the width of the cuboid-shaped porcelain piece is 0.5 +/-0.15 mm, and the thickness of the cuboid-shaped porcelain piece is 0.5 +/-0.15 mm.

7. The laminated chip inductor according to any one of claims 1 to 6, wherein: the pitch between adjacent pattern coils was 10 μm.

8. The laminated chip inductor according to any one of claims 1 to 6, wherein: the pattern coil had a width of 80 μm and a thickness of 15 μm.

9. The laminated chip inductor according to any one of claims 1 to 6, wherein: in each coil group, the number of the pattern coils of at least two coil groups is the same.

10. The laminated chip inductor according to any one of claims 1 to 6, wherein: in each coil group, the number of the pattern coils of at least two coil groups is different.