CN113193043B - Trench gate IGBT device with diode clamping carrier storage layer - Google Patents

Abstract

The invention belongs to the technical field of power semiconductors, and provides a slot-gate IGBT device with a diode-clamped carrier storage layer, which is used to solve the problems of high conduction voltage drop, slow turn-off speed, small short-circuit safe working area and problems existing in the traditional structure. Gate drive power consumption and other issues. The present invention integrates a series connection of PN junction diodes and p-type Schottky diodes, or two series connection of p-type Schottky diodes on the surface of the silicon chip to clamp the potential of the P-type electric field shielding region, thereby shielding the CSL potential. Thus, the doping concentration of the CSL can be greatly increased; the heavy doping of the CSL layer can improve the electron injection efficiency of the IGBT emitter junction, and greatly optimize the compromise between the IGBT's turn-on voltage drop and turn-off speed; in addition, due to The drain voltage of the MOS channel, that is, the CSL potential is shielded at a very low value, which can greatly reduce the saturation current density of the IGBT, and is conducive to increasing the short-circuit safe working area.

Description

A slot-gate IGBT device with a diode-clamped carrier storage layer

technical field

The invention belongs to the technical field of power semiconductors and relates to a high-voltage semiconductor device, in particular to a slot-gate IGBT device with a diode-clamped carrier storage layer.

Background technique

IGBT integrates BJT's small conduction voltage drop, large current capability, MOSFET's low driving power, and fast switching speed, so it is widely used in electronic power systems. The design of the IGBT requires the device to have low turn-on voltage drop, low turn-off loss, large safe operating area and low gate drive loss; because the collector injects a large number of unbalanced carriers into the withstand voltage region during the IGBT turn-on period to reduce Turn-on voltage drop, it takes a long time for the unbalanced carriers injected during turn-off to disappear, which reduces the switching speed of the IGBT and increases the turn-off loss; the turn-on voltage drop can be reduced by increasing the channel current density , but this will increase the saturation current density of the device, resulting in the reduction of the short-circuit safe operating area of the IGBT, and will also increase the gate drive loss.

In order to optimize the above characteristics, an IGBT device with a carrier storage layer (Carrier Stored Layer: CSL) is proposed, as shown in Figure 3, the carrier storage layer is used to improve the injection efficiency of the IGBT emitter junction, and the same conduction The injection efficiency of the collector junction can be reduced under the voltage drop; thus, when the IGBT is in the turn-off process, due to the reduction of the injection efficiency of the collector junction, the device turns off faster and the turn-off loss is lower; and the increase of the CSL doping concentration can further reduce The turn-on voltage drop increases the turn-off speed of the device, but if the CSL concentration is too high, the withstand voltage of the device will decrease sharply.

In order to increase the doping concentration of CSL, the document "R.Y.Ma, et al. "Carrier Stored trench-gate bipolar transistor with p-floating layer", Journal of Semiconductor, 31.2(2010): 024004" proposed a floating p-region electric field The trench gate IGBT of the shielding layer, this structure can further increase the CSL concentration and optimize the device performance; however, the CSL concentration of this structure should not be too high. In order to further optimize device performance, the literature "Li P, Lyu X, Cheng, et al. "A low on-state voltage and saturation current TIGBT with self-biased pMOS," IEEE Electron Device Letters, 2016,37(11):1470- 1472" proposed a structure with a self-biased pMOS clamped CSL layer, which solved the problem that the concentration of the CSL layer should not be too high.

Contents of the invention

Aiming at the problems of high turn-on voltage drop, slow turn-off speed, small short-circuit safe working area, and large gate drive power consumption of traditional slot-gate IGBT devices with carrier storage layers, the present invention proposes a new type with diode clamp A trench gate IGBT device with a carrier storage layer; the trench gate IGBT device process of the present invention is compatible with the existing process, by integrating a series-connected PN junction diode and a p-type Schottky diode, or two series-connected Schottky diodes on the surface of a silicon wafer The p-type Schottky diode is used to clamp the potential of the P-type electric field shielding region, and then shield the CSL potential, so that the doping concentration of the CSL can be greatly increased; the heavy doping of the CSL layer can improve the electron injection efficiency of the IGBT emitter junction , which greatly optimizes the trade-off relationship between the turn-on voltage drop and turn-off speed of the IGBT; in addition, since the drain voltage of the MOS channel, that is, the CSL potential is shielded at a very low value, the IGBT can be greatly reduced. The saturation current density is conducive to increasing the short-circuit safe working area.

In order to achieve the above-mentioned purpose of the invention, the technical scheme adopted in the present invention is:

A trench gate IGBT device with a diode-clamped carrier storage layer, the cell structure of which includes:

N-type pressure-resistant layer 1;

An N-type buffer layer 2 arranged on the lower surface of the N-type voltage-resistant layer, a P-type collector region 3 arranged on the lower surface of the N-type buffer layer, and a collector metal 4 arranged on the lower surface of the P-type collector region;

A P-type electric field shielding region 5 is arranged in the N-type withstand voltage layer 1, an N-type carrier storage layer 6 covering the upper surface of the N-type withstand voltage layer 1 and the P-type electric field shielding region 5, and an N-type carrier storage layer 6 covering the upper surface of the N-type withstand voltage layer 1. P-type semiconductor base region 7 on the upper surface of carrier storage layer 6;

1 slot grid and n-1 isolation slots arranged on the surface of the cell deep into the P-type electric field shielding area, n≥3; the n-1 isolation slots are located on the same side of the slot grid, and the isolation slots and the slot grid Using the same structure, they are all composed of a gate dielectric layer 10 located on the groove wall and a polysilicon gate 11 located in the groove. The upper surface of the polysilicon gate of the groove gate is covered with a gate metal 12, and the upper surface of the isolation groove is covered. There is an emitter metal 13; the groove gate and the isolation groove separate the N-type carrier storage layer 6 and the P-type semiconductor base region 7, and sequentially form the first to n+1th N-type carrier storage layer sub-regions , the first to n+1th subregions of the P-type semiconductor base region;

The lower surface of the first N-type carrier storage layer sub-region is in contact with the N-type withstand voltage layer 1 and the P-type electric field shielding region 5, and the upper surface of the first P-type semiconductor base sub-region is provided with adjacent The first heavily doped N-type semiconductor region 8 and the first heavily doped P-type semiconductor region 9 are connected, and the upper surfaces of both are covered with emitter metal 13;

The lower surfaces of the 2nd to nth N-type carrier storage layer subregions are in contact with the P-type electric field shielding region 5, and the upper surfaces of the 2nd to nth P-type semiconductor base region subregions are respectively provided with The second to nth heavily doped P-type semiconductor regions 9, and the upper surfaces of the second to nth heavily doped P-type semiconductor regions are all covered with emitter metal 13;

The lower surface of the n+1th N-type carrier storage layer subregion is in contact with the P-type electric field shielding region 5, and the upper surface of the n+1th P-type semiconductor base region subregion is provided with adjacent The second heavily doped N-type semiconductor region 8 and the n+1th heavily doped P-type semiconductor region 9; the other side of the n+1th heavily doped P-type semiconductor region is provided with a deep P-type The floating metal 14 in the electric field shielding area, and the floating metal 14 is connected with the n+1th heavily doped P-type semiconductor region, the n+1th N-type carrier storage layer sub-region, and the n+1th P-type Both the semiconductor base subregion and the electric field shielding region are in contact with each other.

A trench gate IGBT device with a diode-clamped carrier storage layer, the cell structure of which includes:

N-type pressure-resistant layer 1;

An N-type buffer layer 2 arranged on the lower surface of the N-type voltage-resistant layer, a P-type collector region 3 arranged on the lower surface of the N-type buffer layer, and a collector metal 4 arranged on the lower surface of the P-type collector region;

A P-type electric field shielding region 5 is arranged in the N-type voltage-resistant layer 1, and is located on a part of the upper surface of the N-type voltage-resistant layer 1, covering the N-type voltage-resistant layer 1 and part of the upper surface of the P-type electric field shielding region 5. type carrier storage layer 6, and a P-type semiconductor base region 7 covering the upper surface of the N-type carrier storage layer 6 and the P-type electric field shielding region 5;

1 slot grid and n-1 isolation slots arranged on the surface of the cell deep into the P-type electric field shielding area, n≥3; the n-1 isolation slots are located on the same side of the slot grid, and the isolation slots and the slot grid Using the same structure, they are all composed of a gate dielectric layer 10 located on the groove wall and a polysilicon gate 11 located in the groove. The upper surface of the polysilicon gate of the groove gate is covered with a gate metal 12. The first to n-th The upper surface of the two isolation grooves is covered with emitter metal as an external port, and the upper surface of the n-1th isolation groove is covered with a floating emitter metal; the groove grid and the isolation groove connect N-type carriers The storage layer 6 and the P-type semiconductor base region 7 are separated, and the 1st to nth N-type carrier storage layer subregions and the 1st to n+1th P-type semiconductor base region subregions are sequentially formed;

The lower surface of the first N-type carrier storage layer sub-region is in contact with the N-type withstand voltage layer 1 and the P-type electric field shielding region 5, and the upper surface of the first P-type semiconductor base sub-region is provided with adjacent The first heavily doped N-type semiconductor region 8 and the first heavily doped P-type semiconductor region 9 are connected, and the upper surfaces of both are covered with emitter metal 13;

The lower surface of the 2nd to n-1th N-type carrier storage layer subregions is in contact with the P-type electric field shielding region 5, and the second to n-1th P-type semiconductor base region subregions The surface is respectively provided with the 2nd to n-1th heavily doped P-type semiconductor regions 9, and the upper surface of the 2nd to n-1th heavily doped P-type semiconductor regions is covered with emitter metal 13;

The lower surface of the nth N-type carrier storage layer subregion is in contact with the P-type electric field shielding region 5, and the upper surface part of the nth P-type semiconductor body subregion covers the first floating Metal, and is in contact with the emitter metal 13 on the surface of the n-2th isolation groove; the nth heavily doped P-type semiconductor region is set in the nth P-type semiconductor body region sub-region, and the nth The upper surface of a heavily doped P-type semiconductor region is covered with a floating emitter metal and is not in contact with the first floating metal;

The lower surface of the n+1th P-type semiconductor base sub-region is in contact with the P-type electric field shielding region 5, and the upper surface is covered with a second floating metal, and the second floating metal is connected to the floating emission pole metal contact.

The beneficial effects of the present invention are:

The slot gate IGBT device provided by the present invention has a diode-clamped carrier storage layer. When withstand voltage, the PN junction diode and the P-type Schottky diode connected in series or two P-type Schottky diodes connected in series will The potential clamp of the P-type electric field shielding area is near the conduction voltage drop of the two series diodes, thereby forming an electric field shield for the carrier storage layer, thereby avoiding premature breakdown of the carrier storage layer due to excessive doping concentration; The heavy doping of the storage layer can further reduce the turn-on voltage drop and turn-off loss; when turned on, the potential of the P-type electric field shielding region is also connected to the PN junction diode and Schottky diode in series or two P-type diodes in series The Schottky diode is clamped near the conduction voltage drop of the two series diodes, thereby forming an electric field shield for the carrier storage layer 6, and the low potential of the carrier storage layer leads to a very low saturation current density, which is beneficial to increase the short circuit of the IGBT safe work area.

In summary, the present invention provides a trench-gate IGBT device with a diode-clamped carrier storage layer. Compared with the traditional structure, the trade-off relationship between the turn-on voltage drop and turn-off speed of the device can be greatly optimized, and the turn-off loss of the device can be greatly reduced, and the short-circuit safe working area of the device can be significantly increased.

Description of drawings

FIG. 1 is a schematic structural diagram of a trench-gate IGBT device with a P-type Schottky diode and a PN junction diode connected in series to clamp a carrier storage layer according to Embodiment 1 of the present invention.

2 is a schematic structural diagram of a trench-gate IGBT device with two P-type Schottky diodes connected in series to clamp the carrier storage layer according to Embodiment 2 of the present invention.

FIG. 3 is a schematic structural diagram of a conventional trench-gate IGBT with a carrier storage layer.

FIG. 4 is a comparison diagram of the trade-off relationship between turn-on voltage drop (V _on ) and turn-off loss (E _off ) simulated by devices with a withstand voltage level of 1200V in this embodiment and the existing structure.

FIG. 5 is a comparison chart of the trade-off relationship between the withstand short-circuit time (t _sc ) and conduction voltage drop of the simulated device with a withstand voltage of 1200V in this embodiment and a traditional structure (as shown in FIG. 3 ).

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Example 1

This embodiment provides a trench gate IGBT device with a series connection of P-type Schottky diodes and PN junction diodes to clamp the carrier storage layer. Its structure is shown in FIG. The same reference number is used for the same type of semiconductor regions; specifically, the cells include:

N-type pressure-resistant layer 1;

An N-type buffer layer 2 arranged on the lower surface of the N-type voltage-resistant layer, a P-type collector region 3 arranged on the lower surface of the N-type buffer layer, and a collector metal 4 arranged on the lower surface of the P-type collector region;

The P-type electric field shielding region 5 is arranged in the N-type voltage-resistant layer 1, and is located on the upper surface part of the N-type voltage-resistant layer 1, covering the N-type voltage-resistant layer 1 and the upper surface of the P-type electric field shielding region 5. The carrier storage layer 6, and the P-type semiconductor base region 7 covering the upper surface of the N-type carrier storage layer 6;

One groove grid and three isolation grooves arranged on the surface of the cell deep into the P-type electric field shielding area; the three isolation grooves are located on the same side of the groove grid, and the isolation groove and the groove grid adopt the same structure, and are located The gate dielectric layer 10 on the groove wall is composed of a polysilicon gate 11 located in the groove, the upper surface of the polysilicon gate of the groove gate is covered with a gate metal 12, and the upper surface of the isolation groove is covered with an emitter metal 13; Both the groove gate and the isolation groove completely separate the N-type carrier storage layer 6 and the P-type semiconductor base region 7 on both sides thereof, and sequentially form the first to fifth N-type carrier storage layer sub-regions, the first to the fifth The fifth P-type semiconductor base sub-region;

The lower surface of the first N-type carrier storage layer sub-region is in contact with the N-type withstand voltage layer 1 and the P-type electric field shielding region 5, and the upper surface of the first P-type semiconductor base sub-region is provided with adjacent The first heavily doped N-type semiconductor region 8 and the first heavily doped P-type semiconductor region 9 are connected; the first heavily doped N-type semiconductor region 8 is in contact with the gate dielectric layer of the groove gate, as The source region of the N-type MOSFET; the upper surface of the first heavily doped N-type semiconductor region 8 and the first heavily doped P-type semiconductor region 9 is covered with an emitter metal 13;

The lower surfaces of the 2nd to 4th N-type carrier storage layer subregions are in contact with the P-type electric field shielding region 5, and the upper surfaces of the 2nd to 4th P-type semiconductor base region subregions are respectively provided with The second to fourth heavily doped P-type semiconductor regions 9, the upper surfaces of the second to fourth heavily doped P-type semiconductor regions are covered with emitter metal 13;

The lower surface of the fifth N-type carrier storage layer sub-region is in contact with the P-type electric field shielding region 5, and the upper surface of the fifth P-type semiconductor base sub-region is provided with an adjacent second The heavily doped N-type semiconductor region 8 and the fifth heavily doped P-type semiconductor region 9; the second heavily doped N-type semiconductor region is in contact with the gate dielectric layer of the third isolation trench, and the fifth The other side of the first heavily doped P-type semiconductor region is provided with a floating metal 14 that goes deep into the P-type electric field shielding region 5, and the floating metal 14 is connected with the fifth heavily doped P-type semiconductor region and the fifth N-type carrier. The carrier storage layer subregion, the fifth P-type semiconductor base region subregion, and the electric field shielding region 5 are all in contact.

In terms of working principle:

In this embodiment, the feature of the P-type electric field shielding region 5 is that it clamps its potential at the conduction voltage drop of the two series-connected diodes through the series-connected P-type Schottky diode and PN junction diode integrated on the surface of the silicon chip. nearby. More precisely, the P-type electric field shielding region 5 is clamped by a series connection of P-type Schottky diodes and PN junction diodes integrated on the surface of the silicon chip; the contact surface of the floating metal 14 and the P-type electric field shielding region 5 is formed P-type Schottky contact, that is, the contact surface is a p-type Schottky diode; the second heavily doped N-type semiconductor region 8 and the fifth heavily doped P-type semiconductor region 9 form a PN diode; The p-type Schottky diode and the PN junction diode are connected in series through the floating metal 14, and the potential of the electric field shielding region 5 is clamped near the conduction voltage drop of the two diodes, thereby shielding the CSL potential, thereby greatly Amplitude increases the doping concentration of CSL. The heavy doping of the CSL layer can improve the electron injection efficiency of the IGBT emitter junction, and greatly optimize the trade-off relationship between the turn-on voltage drop and turn-off speed of the IGBT; in addition, due to the drain voltage of the MOS channel, that is, the CSL potential It is clamped at a very low value, which can greatly reduce the saturation current density of the IGBT, which is beneficial to increase the short-circuit safe working area.

As shown in Fig. 4, it is a comparison chart of the trade-off relationship between the turn-on voltage drop (V _on ) and the turn-off loss (E _off ) of the simulated device with a withstand voltage of 1200V in this embodiment and the traditional structure (as shown in Fig. 3 ). , it can be seen from the figure that under the same conduction voltage drop, the turn-off loss of the present invention is greatly reduced.

As shown in FIG. 5, it is a comparison chart of the trade-off relationship between the withstand short-circuit time (t _sc ) and the conduction voltage drop of the simulated device of the device with a withstand voltage of 1200V in this embodiment and the traditional structure (as shown in FIG. 3 ), It can be seen from the figure that under the same conduction voltage drop, the withstand short-circuit time of the present invention is greatly improved.

Example 2

This embodiment provides a slot gate IGBT device with two P-type Schottky diodes connected in series to clamp the carrier storage layer, its structure is shown in Figure 2, and the cells include:

N-type pressure-resistant layer 1;

An N-type buffer layer 2 arranged on the lower surface of the N-type voltage-resistant layer, a P-type collector region 3 arranged on the lower surface of the N-type buffer layer, and a collector metal 4 arranged on the lower surface of the P-type collector region;

A P-type electric field shielding region 5 is arranged in the N-type voltage-resistant layer 1, and is located on a part of the upper surface of the N-type voltage-resistant layer 1, covering the N-type voltage-resistant layer 1 and part of the upper surface of the P-type electric field shielding region 5. type carrier storage layer 6, and a P-type semiconductor base region 7 covering the upper surface of the N-type carrier storage layer 6 and the P-type electric field shielding region 5;

One groove grid and three isolation grooves arranged on the surface of the cell deep into the P-type electric field shielding area; the three isolation grooves are located on the same side of the groove grid, and the isolation groove and the groove grid adopt the same structure, and are located The gate dielectric layer 10 on the groove wall is composed of a polysilicon gate 11 located in the groove, the upper surface of the polysilicon gate of the groove gate is covered with a gate metal 12, and the upper surface of the first to second isolation grooves is covered with an emitter Metal 13, the upper surface of the third isolation groove is covered with floating emitter metal 16; the groove gate and the isolation groove completely separate the N-type carrier storage layer 6 and the P-type semiconductor base region 7 on both sides, sequentially forming the first to fourth N-type carrier storage layer sub-regions and the first to fifth P-type semiconductor base region sub-regions;

The lower surface of the first N-type carrier storage layer sub-region is in contact with the N-type withstand voltage layer 1 and the P-type electric field shielding region 5, and the upper surface of the first P-type semiconductor base sub-region is provided with adjacent The first heavily doped N-type semiconductor region 8 and the first heavily doped P-type semiconductor region 9 are connected; the first heavily doped N-type semiconductor region 8 is in contact with the gate dielectric layer of the groove gate, as The source region of the N-type MOSFET; the upper surface of the first heavily doped N-type semiconductor region 8 and the first heavily doped P-type semiconductor region 9 is covered with an emitter metal 13;

The lower surfaces of the 2nd to 3rd N-type carrier storage layer subregions are in contact with the P-type electric field shielding region 5, and the upper surfaces of the 2nd to 3rd P-type semiconductor base region subregions are respectively provided with The second to third heavily doped P-type semiconductor regions, the upper surfaces of the second to third heavily doped P-type semiconductor regions are covered with emitter metal 13;

The lower surface of the fourth N-type carrier storage layer sub-region is in contact with the P-type electric field shielding region 5, and the upper surface of the fourth P-type semiconductor body sub-region is adjacent to the part of the second isolation groove The area covers the first floating metal 15 and is in contact with the emitter metal 13 on the second isolation groove; the fourth heavily doped P-type semiconductor region is set in the fourth P-type semiconductor body sub-region , the upper surface of the fourth heavily doped P-type semiconductor region is covered with a floating emitter metal and is not in contact with the first floating metal 15;

The lower surface of the fifth P-type semiconductor base sub-region is in contact with the P-type electric field shielding region 5, and the upper surface is covered with the second floating metal 15 and the second floating metal 15 floating emitter metal 16 contacts.

In terms of working principle:

In this embodiment, the characteristic of the P-type electric field shielding region 5 is that it clamps its potential near the conduction voltage drop of the two series-connected diodes through the two series-connected P-type Schottky diodes integrated on the surface of the silicon wafer. . More precisely, the floating metal 15 forms a p-type Schottky contact with the P-type semiconductor base sub-region, and the floating metal forms the first p-type Schottky contact with the fifth P-type semiconductor base sub-region. Tertky diode, the floating metal and the fourth P-type semiconductor base sub-region form a second p-type Schottky diode, and the first and second P-type Schottky diodes are connected in series through the floating metal , to clamp the potential of the electric field shielding region 5 near the conduction voltage drop of the two diodes.

Based on the above working principle, compared with the existing structure, the slot-gate IGBT device in this embodiment can also greatly reduce the turn-off loss and greatly increase the tolerable short-circuit time under the same turn-on voltage drop.

In addition, the emitter metal 13 , the floating metal 14 and the floating metal 15 may be the same metal or different metals.

The above is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless specifically stated, can be replaced by other equivalent or alternative features with similar purposes; all the disclosed features, or All method or process steps may be combined in any way, except for mutually exclusive features and/or steps.

Claims (2)

1. A trench gate IGBT device with a diode-clamped carrier storage layer, its cell structure comprising: N-type pressure-resistant layer (1); An N-type buffer layer (2) disposed on the lower surface of the N-type voltage-resistant layer, a P-type collector region (3) disposed on the lower surface of the N-type buffer layer, and a collector metal disposed on the lower surface of the P-type collector region (4); The P-type electric field shielding region (5) arranged in the N-type voltage withstand layer (1), the N-type carrier storage layer ( 6), and a P-type semiconductor base region (7) covering the upper surface of the N-type carrier storage layer (6); 1 slot grid and n-1 isolation slots arranged on the surface of the cell deep into the P-type electric field shielding area, n≥3; the n-1 isolation slots are located on the same side of the slot grid, and the isolation slots and the slot grid Using the same structure, they are all composed of a gate dielectric layer (10) located on the groove wall and a polysilicon gate (11) located in the groove, and the upper surface of the polysilicon gate of the groove gate is covered with a gate metal (12). The upper surface of the isolation groove is covered with emitter metal (13); the groove gate and the isolation groove separate the N-type carrier storage layer (6) and the P-type semiconductor base region (7), sequentially forming the first to nth +1 N-type carrier storage layer sub-region, 1st to n+1th P-type semiconductor base sub-regions; The lower surface of the first N-type carrier storage layer sub-region is in contact with the N-type withstand voltage layer (1) and the P-type electric field shielding region (5), and the upper surface of the first P-type semiconductor base sub-region The first heavily doped N-type semiconductor region (8) and the first heavily doped P-type semiconductor region (9) adjacent to each other are provided, and the upper surfaces of both are covered with emitter metal (13); The lower surfaces of the 2nd to nth N-type carrier storage layer subregions are in contact with the P-type electric field shielding region (5), and the upper surfaces of the 2nd to nth P-type semiconductor base subregions are respectively The second to nth heavily doped P-type semiconductor regions (9) are provided, and the upper surfaces of the second to nth heavily doped P-type semiconductor regions are all covered with emitter metal (13); The lower surface of the n+1th N-type carrier storage layer subregion is in contact with the P-type electric field shielding region (5), and the upper surface of the n+1th P-type semiconductor base region subregion is provided with a corresponding The second adjacent heavily doped N-type semiconductor region (8) and the n+1th heavily doped P-type semiconductor region (9); the other of the n+1th heavily doped P-type semiconductor region The side is provided with a floating metal (14) deep into the P-type electric field shielding region, and the floating metal (14) is connected with the n+1th heavily doped P-type semiconductor region and the n+1th N-type carrier storage layer The sub-region, the n+1th P-type semiconductor base sub-region, and the electric field shielding region are all in contact; the contact surface of the floating metal (14) and the P-type electric field shielding region (5) forms a P-type Schottky contact, Form a P-type Schottky diode. 2. A trench gate IGBT device with a diode-clamped carrier storage layer, its cell structure comprising: N-type pressure-resistant layer (1); An N-type buffer layer (2) disposed on the lower surface of the N-type voltage-resistant layer, a P-type collector region (3) disposed on the lower surface of the N-type buffer layer, and a collector metal disposed on the lower surface of the P-type collector region (4); The P-type electric field shielding area (5) arranged in the N-type voltage-resistant layer (1), and the P-type electric field-shielding area (5) are located on the upper surface part of the N-type voltage-resistant layer (1), covering the N-type voltage-resistant layer (1) and the N-type carrier storage layer (6) on the upper surface of part of the P-type electric field shielding region (5), and covering the N-type carrier storage layer (6) and the P-type electric field shielding region (5) The P-type semiconductor base region (7) on the surface; 1 slot grid and n-1 isolation slots arranged on the surface of the cell deep into the P-type electric field shielding area, n≥3; the n-1 isolation slots are located on the same side of the slot grid, and the isolation slots and the slot grid Using the same structure, they are all composed of a gate dielectric layer (10) located on the groove wall and a polysilicon gate (11) located in the groove, and the upper surface of the polysilicon gate of the groove gate is covered with a gate metal (12). The upper surface of the first to n-2 isolation grooves is covered with an emitter metal, and the upper surface of the n-1 isolation groove is covered with a floating emitter metal; the groove grid and the isolation groove connect the N-type carrier The carrier storage layer (6) and the P-type semiconductor base region (7) are separated to form the 1st to nth N-type carrier storage layer subregions and the 1st to n+1th P-type semiconductor base region subregions in sequence. district; The lower surface of the first N-type carrier storage layer sub-region is in contact with the N-type withstand voltage layer (1) and the P-type electric field shielding region (5), and the upper surface of the first P-type semiconductor base sub-region The first heavily doped N-type semiconductor region (8) and the first heavily doped P-type semiconductor region (9) adjacent to each other are provided, and the upper surfaces of both are covered with emitter metal (13); The lower surface of the 2nd to n-1th N-type carrier storage layer sub-regions is in contact with the P-type electric field shielding region (5), and the 2nd to n-1th P-type semiconductor base sub-regions The upper surfaces of the regions are respectively provided with the 2nd to n-1th heavily doped P-type semiconductor regions (9), and the upper surfaces of the 2nd to n-1th heavily doped P-type semiconductor regions are all covered with emitter metal ( 13); The lower surface of the nth N-type carrier storage layer subregion is in contact with the P-type electric field shielding region (5), and the upper surface part of the nth P-type semiconductor body subregion covers the first Floating metal, and the first floating metal is in contact with the emitter metal (13); the nth heavily doped P-type semiconductor region is set in the nth P-type semiconductor body region sub-region, and the first The upper surface of n heavily doped P-type semiconductor regions is covered with floating emitter metal and is not in contact with the first floating metal; the first floating metal is in contact with the nth P-type semiconductor body sub-region Form a P-type Schottky contact on the surface to form a P-type Schottky diode; The lower surface of the n+1th P-type semiconductor base sub-region is in contact with the P-type electric field shielding region (5), and the upper surface is covered with a second floating metal, and the second floating metal is in contact with the floating metal. The empty emitter metal is in contact; the second floating metal forms a P-type Schottky contact with the contact surface of the n+1th P-type semiconductor base sub-region, forming a P-type Schottky diode.

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