CN113192921A - Packaging frame structure, manufacturing method and chip packaging structure - Google Patents
Packaging frame structure, manufacturing method and chip packaging structure Download PDFInfo
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- CN113192921A CN113192921A CN202110707526.3A CN202110707526A CN113192921A CN 113192921 A CN113192921 A CN 113192921A CN 202110707526 A CN202110707526 A CN 202110707526A CN 113192921 A CN113192921 A CN 113192921A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 114
- 238000000034 method Methods 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000005538 encapsulation Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 18
- 238000007639 printing Methods 0.000 claims description 16
- 238000001723 curing Methods 0.000 claims description 13
- 239000000047 product Substances 0.000 claims description 13
- 239000011265 semifinished product Substances 0.000 claims description 12
- 238000009713 electroplating Methods 0.000 claims description 7
- 230000001680 brushing effect Effects 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 5
- 238000000016 photochemical curing Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 31
- 238000003466 welding Methods 0.000 description 14
- 230000007797 corrosion Effects 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- 238000005286 illumination Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical group [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical group [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 229910000029 sodium carbonate Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a packaging frame structure, a manufacturing method and a chip packaging structure, and belongs to the field of semiconductor packaging. The invention provides a packaging frame structure, a manufacturing method and a chip packaging structure, aiming at the problems that a high-temperature resistant film is pasted on the back surface of a frame in the prior art, the high-temperature resistant film has high cost, is softened after being heated at high temperature, has poor ball bonding and routing operability, is easy to generate flash during packaging, and stains finished products, and reduces the packaging yield, wherein the packaging frame structure, the manufacturing method and the chip packaging structure comprise a substrate, wherein an ink layer is arranged on the front surface of a substrate, the ink layer covers the surface of a front metal region and the side surfaces of front pins, and the front pins protrude out of the ink layer; the back of the substrate is provided with an ink layer, the ink layer covers the surface of the back metal area and the side faces of the back pins, and the back pins protrude out of the ink layer. The method can avoid the use of the high-temperature film of the original frame, reduce the cost of the frame, improve the operability of ball bonding and avoid the reduction of the product yield caused by encapsulation flash.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a packaging frame structure, a manufacturing method and a chip packaging structure.
Background
For decades, the technology of packaging integrated circuits has been developed following the development of integrated circuits, and people have sought the best balance between small size and high performance. From the DIP plug-in package of the 70 s to the SOP surface mount package and then to the QFP flat type patch package of the 80 s, the package volume of the chip is developing towards miniaturization all the time, and the structural performance is continuously improved. In the past 90 s, the quad flat no-lead package (QFN) appeared, and output pins around the package were originally stored at the bottom of the package on the basis of QFP, so that the occupied space during the chip mounting operation was greatly reduced. The QFN package effectively utilizes the packaging space of the terminal pins, thereby greatly improving the packaging efficiency.
The manufacturing process of the packaging frame in the prior art comprises the following steps: taking a substrate, carrying a bare chip on the front surface of the substrate, connecting an external circuit on the back surface of the substrate, pasting a dry film on the front surface of the substrate, forming a shape to be etched on the front surface of the substrate through exposure and development, etching the front surface of the substrate, not etching the area covered by the dry film, and recessing the etched area so as to expose a front surface pin, and pasting, exposing and etching the back surface of the substrate by the same process to expose a back surface pin. In the prior art, the area without pins on the front surface of the substrate is not processed, the substrate is directly exposed, the subsequent ball bonding and routing are easy to cause short circuit, and the subsequent insulation deterioration and corrosion can be caused by external environmental factors such as dust, moisture and the like.
In the prior art, in order to avoid plastic package tree from flowing to a lead pin during encapsulation, a high-temperature-resistant adhesive tape is pasted on the back of a frame, such as the Chinese utility model patent, publication No. CN202259243U, published No. 2012-05-30 discloses a frame film packaging part after ball welding, the scheme carries out frame film pasting after ball welding, the problem of ball welding operation phase difference caused by softening of a pin back adhesive film caused by overhigh welding temperature during ball welding can be avoided, but the frame is processed by a former process, has the deformation problem, the film is pasted after ball welding, the frame is poor in combination with the film, and the defects of plastic package flash and the like are easily aggravated.
Disclosure of Invention
1. Technical problem to be solved
The invention provides a packaging frame structure, a manufacturing method and a chip packaging structure, aiming at the problems that the front side of a substrate is not protected and the ball bonding and routing operability is poor in the prior art, and the problems that a high-temperature resistant film is pasted on the back side of a frame for back side protection, the bonding force between the film and the substrate is reduced, flash is easily generated in packaging, the finished product is polluted, and the packaging yield is reduced. It sets up back printing ink layer at the back of base plate, avoids the use of original frame back high temperature membrane, and on the temperature was too high when solving ball bonding and lead to the basis of the low problem of product yield, can also reduce cost.
2. Technical scheme
The purpose of the invention is realized by the following technical scheme.
A package frame structure comprising:
the PCB packaging structure comprises a substrate, a PCB and a packaging substrate, wherein one surface of the substrate, which bears a bare chip, is a front surface, the other surface of the substrate is a back surface, the front surface of the substrate is provided with front surface pins, the back surface of the substrate is provided with back surface pins, the front surface pins are used for chip mounting and routing, and the back surface pins are used for the PCB after subsequent packaging and electroplating;
the front side ink layer covers the region of the front side of the substrate except the front side pins, and the front side pins protrude out of the front side ink layer;
the back ink layer covers the region of the back of the substrate except the back pins, and the back pins protrude out of the back ink layer;
and the metal coating is arranged on the front pin.
The manufacturing method of the packaging frame structure comprises the following steps:
taking a substrate, wherein the substrate mainly plays a role in bearing and protecting a bare chip (die) before packaging and electrically connecting the bare chip (die) and a circuit board;
sticking a dry film on the front surface of the substrate, wherein the dry film is tightly stuck to the front surface of the substrate, the dry film is a photosensitive material, and a shape to be etched can be formed on the surface of the substrate through subsequent exposure;
baking the dry film, wherein the dry film is dried to be beneficial to subsequent development, and incomplete development can be caused if the dry film is not dried;
carrying out illumination exposure on the dry film, aligning the negative film with the dry film, and transferring the negative film pattern to the photosensitive dry film through illumination;
developing the dry film by a developing solution, washing the unexposed dry film by the developing solution, reserving the exposed part, removing the dry film covering the area needing etching by the developing solution to expose the area needing etching on the front surface of the substrate;
etching the front surface of the substrate, wherein the area covered by the dry film cannot be etched, and the etched area is sunken so as to expose the front surface pins;
the front side of the substrate is provided with a front side ink layer which is used as a protective layer and coated on a circuit and a base material of a printed circuit board which do not need to be welded.
Further, the method for setting the front ink layer and the back ink layer is the same, and the specific method is as follows:
brushing a layer of printing ink on the surface of a substrate, wherein the surface of the substrate is a front surface or a back surface;
pre-curing, exposing, developing and photo-curing the surface of the substrate, and removing redundant ink on the surface of the pin to enable the pin to be higher than the ink;
curing the printing ink for one time through primary baking;
exposing and developing the cured printing ink to show the pins;
and (5) secondary baking, namely curing the printing ink for the second time, hardening the printing ink by the secondary baking, and fixing the printing ink on the substrate.
Sticking a dry film on the back of the substrate, wherein the dry film is tightly stuck to the back of the substrate and is a photosensitive material;
baking the dry film, wherein the dry film is dried to be beneficial to subsequent development, and incomplete development can be caused if the dry film is not dried;
carrying out illumination exposure on the dry film, aligning the negative film with the dry film, and transferring the negative film pattern to the photosensitive dry film through illumination;
developing the dry film by a developing solution, wherein the exposed area is an area needing etching, and the dry film covering the area needing etching is removed by developing to expose the area needing etching on the back surface of the substrate;
etching the back surface of the substrate, wherein the area covered by the dry film cannot be etched, and the etched area is sunken so as to expose the back surface pins;
the back side ink layer is arranged on the back side of the substrate, the specific method for arranging the back side ink layer is the same as the method for arranging the front side ink layer on the front side of the substrate, and the back side ink layer arranged on the back side of the substrate can avoid the use of a high-temperature-resistant film in the prior art.
The front pin is electroplated with a metal coating which can enhance the conductivity, corrosion resistance and wear resistance of the front pin.
A chip packaging structure is characterized in that chip implantation is carried out on the front surface of a substrate to form an array type assembly semi-finished product of an integrated circuit or discrete components;
routing the semi-finished product which has finished the chip implantation operation to form a lead;
encapsulating the semi-finished product after routing, and then curing to form an encapsulation;
electroplating metal on the pins on the back of the substrate;
and cutting the semi-finished product to form a single product.
3. Advantageous effects
The front side ink layer is arranged on the front side of the substrate, and can ensure that short circuit caused by bridging can be prevented in a welding process; welding is only carried out on the part which needs to be welded, so that waste of welding flux is avoided; copper pollution to the welding material groove is reduced; insulation deterioration and corrosion caused by external environmental factors such as dust, moisture and the like are prevented; the high insulation property enables the high density of the circuit; and the ball bonding and routing process is strong in operability, high in routing speed and high in quality. The ink layer is arranged on the back surface of the substrate, so that the use of a high-temperature-resistant film is avoided, the production cost of the frame is reduced, the bonding force between the film and the substrate is prevented from being reduced due to the high temperature of ball bonding, and flash cannot be generated during subsequent encapsulation.
Drawings
FIG. 1 is a schematic view of a substrate structure according to the present invention;
FIG. 2 is a schematic structural view of the front surface of the substrate with a dry film attached thereon according to the present invention;
FIG. 3 is a schematic diagram of the front side dry film exposure and development structure of the substrate according to the present invention;
FIG. 4 is a schematic diagram of the structure of the front side of the substrate after etching according to the present invention;
FIG. 5 is a schematic structural diagram of a front side of a substrate according to the present invention after being printed with ink;
FIG. 6 is a schematic structural view of the front surface of the substrate with the leads exposed;
FIG. 7 is a schematic view of a structure of the substrate according to the present invention after a dry film is attached to the back surface of the substrate;
FIG. 8 is a schematic view of the structure of the backside of the substrate after dry film exposure and development according to the present invention;
FIG. 9 is a schematic diagram of the structure of the substrate after etching according to the present invention;
FIG. 10 is a schematic view of a back side of a substrate printed with ink according to the present invention;
FIG. 11 is a schematic view of the structure of the substrate with the leads exposed on the back surface thereof according to the present invention;
FIG. 12 is a schematic diagram of a structure of the front surface of the substrate after the lead is plated.
The reference numbers in the figures illustrate: 1. a substrate; 2. drying the film; 3. a front pin; 4. a front ink layer; 5. a back pin; 6. a back ink layer; 7. and (5) plating a metal layer.
Detailed Description
The invention is described in detail below with reference to the drawings and specific examples.
Example 1
A packaging frame structure is manufactured by the following steps:
as shown in fig. 1, a substrate 1 is taken, the substrate 1 mainly plays a role of carrying and protecting a die (die) before packaging, electrically connecting the die (die) and a circuit board, the substrate 1 is generally made of copper, the thickness is generally 0.1mm, 0.127mm, 0.152mm or 0.203 mm, and the size of the substrate 1 is generally 258mm 78mm, 258mm 83mm, 300mm 93mm or 300mm 100 mm.
As shown in fig. 2, a Dry film 2 is attached to the front surface of a substrate 1, the Dry film 2 is attached to the front surface of the substrate, the Dry film 2 (Dry film) is relative to a Wet film (Wet film) in coating, the Dry film 2 is a high molecular compound, and after being irradiated by ultraviolet rays, a polymerization reaction (a reaction process of synthesizing a polymer from a monomer) can be generated to form a stable substance to be attached to the surface of the substrate, so that the functions of resisting electroplating and etching are achieved.
And baking the dry film 2, wherein the dry film 2 is dried to be beneficial to subsequent development, and incomplete development can be caused if the dry film 2 is not dried.
And (3) carrying out illumination exposure on the dry film 2, aligning the negative film with the dry film 2, and transferring the negative film graph to the dry film 2 through illumination.
As shown in fig. 3, the dry film 2 is developed by the developing solution, the unexposed dry film 2 is washed away by the developing solution, the exposed portion remains, the unexposed portion is the area to be etched, and the dry film 2 covering the area to be etched is removed by the developing solution, so that the area to be etched on the front surface of the substrate 1 is exposed.
As shown in fig. 4, the front surface of the substrate 1 is etched, in which the metal is exposed to the chemical solution to dissolve and corrode the metal, thereby forming a recess, and the area covered by the dry film 2 is not etched, and the etched area is recessed, thereby exposing the front surface leads 3.
The front side ink layer 4 is arranged on the front side of the substrate 1, and the front side ink layer 4 can ensure that short circuit caused by bridging can be prevented in a welding process; welding is only carried out on the part which needs to be welded, so that waste of welding flux is avoided; copper pollution to the welding material groove is reduced; insulation deterioration and corrosion caused by external environmental factors such as dust, moisture and the like are prevented; has high insulation and can realize high density of circuit.
The specific method for setting the front ink layer 4 is as follows:
as shown in fig. 5, a layer of ink is brushed on the front surface of the substrate 1; the ink can be directly brushed by using SMT brushing equipment, the ink is a photosensitive material and is a liquid photoimaging solder resist ink, and a proper ink, namely the acrylic oligomer in the embodiment, is selected according to a series of characteristics of the product, such as electrical property, heat-resisting temperature, flame retardance, reliability and the like. As a protective layer, it is coated on the circuit and substrate of the printed circuit board which do not need to be soldered, or used as a solder resist, in order to protect the formed circuit pattern for a long time.
As shown in fig. 6, the front surface of the substrate 1 is pre-cured, exposed, developed, and photo-cured, and excess ink on the surface of the front surface pins 3 is removed, so that the front surface pins 3 are higher than the front surface ink layer 4.
And curing the ink once after primary baking, wherein the primary baking temperature is 75 +/-5 ℃ and the primary baking time is 50 +/-10 min.
The pins of the solidified printing ink are exposed and developed, and the developing liquid medicine is sodium carbonate during development.
And (2) secondary baking, wherein the secondary baking temperature is 175 +/-5 ℃, the time is 4 hours, the secondary baking enables the ink to be hardened and fixed on the substrate 1, and due to the baking, the ink shrinks by about 40%, and the secondary curing and exposure developing method is adopted, so that the ink can not fall off, the subsequent process is ensured to be smoothly carried out, and the ink on the front pin 3 is removed.
As shown in fig. 7, a dry film is attached to the back surface of the substrate 1, the dry film is baked, and the dry film is exposed by light.
As shown in fig. 8, the dry film is developed by a developer, the unexposed area is the area to be etched, and the development removes the dry film covering the area to be etched, exposing the area to be etched on the back surface of the substrate 1.
As shown in fig. 9, the back surface of the substrate 1 is etched in the same process as the front surface etching, the area covered with the dry film is not etched, and the etched area is recessed to expose the back surface leads 5.
As shown in fig. 10 and 11, the back ink layer 6 is disposed on the back surface of the substrate 1, and the specific method for disposing the back ink layer 6 is the same as the method for disposing the front ink layer 4, and the provision of the back ink layer 6 on the back surface of the substrate 1 can avoid the use of the high-temperature film of the original frame, reduce the cost of the frame, secondly improve the workability of ball bonding, and avoid the reduction of the yield of products caused by the encapsulation flash.
As shown in fig. 12, the front pin 3 is electroplated with a metal plating layer 7, the plating layer is silver, and the conductivity, corrosion resistance and wear resistance of the front pin 3 can be enhanced, the reliability of the chip can be enhanced, and the service life of the chip can be prolonged.
After the packaging frame structure is manufactured, chip implantation is carried out on the front surface of a substrate 1 of the frame to form an array type aggregate semi-finished product of an integrated circuit or discrete components;
routing the semi-finished product after the chip implantation operation is finished, and connecting the chip and the front pin by using a lead, wherein the lead is a gold wire, a silver wire, a copper wire or an aluminum wire;
encapsulating the semi-finished product after routing, and then curing to form an encapsulation;
electroplating metal on the pins 5 on the back surface of the substrate to form a metal coating 7, wherein the metal is silver, and the conductivity, corrosion resistance and wear resistance of the pins 5 on the back surface can be enhanced through electroplating, so that the reliability of a product after being coated with a PCB (printed circuit board) is improved;
and cutting the semi-finished product, and separating the product to form a single product.
The back printing ink layer 6 is arranged on the back of the substrate 1, so that the use of a high-temperature-resistant film is avoided, the production cost of the frame is reduced, the bonding force between the film and the substrate 1 caused by high temperature of ball bonding is prevented from being reduced, and flash cannot be generated during subsequent encapsulation.
Example 2
Example 2 is substantially the same as example 1, and further preferably, step a further includes placing the substrate 1 after the ink application in a vacuum box, and performing vacuum pumping. During vacuumizing, 0.08-0.1MPa is selected, the time is within 5-10min, and in the process of brushing ink, because bubbles exist in the ink, the substrate 1 after being brushed with the ink is placed in a vacuum box for vacuumizing, so that the generation of bubbles in the product is effectively prevented, the quality of the product is ensured, and new defects are prevented from being introduced. And because the baking steps of the front step and the back step and the vacuumizing step also effectively prevent that in the baking stage, bubbles cause the fragmentation and the unevenness of an ink layer during baking to influence the overall performance, the height inconsistency during ink shrinkage to cause the protrusion height of pins is also prevented, the glue brushing defect can be caused in the subsequent process, and a new short circuit defect is introduced, such as the tin quantity difference on a plurality of pins, so that the reliability risks of slippage, tombstoning and the like can be caused after SMT reflow soldering of a product.
The invention and its embodiments have been described above schematically, without limitation, and the invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The representation in the drawings is only one of the embodiments of the invention, the actual construction is not limited thereto, and any reference signs in the claims shall not limit the claims concerned. Therefore, if a person skilled in the art receives the teachings of the present invention, without inventive design, a similar structure and an embodiment to the above technical solution should be covered by the protection scope of the present patent. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Several of the elements recited in the product claims may also be implemented by one element in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (10)
1. A package frame structure, comprising:
the die comprises a substrate (1), wherein one surface of the substrate (1) for bearing a bare chip is a front surface, the other surface of the substrate is a back surface, front surface pins (3) are arranged on the front surface of the substrate (1), and back surface pins (5) are arranged on the back surface of the substrate (1);
the front side ink layer (4), the front side ink layer (4) covers the region of the front side of the substrate (1) except the front side pins (3), and the front side pins (3) protrude out of the front side ink layer (4).
2. The package frame structure of claim 1, further comprising a back side ink layer (6), wherein the back side ink layer (6) covers a region of the back side of the substrate (1) except the back side leads (5), and the back side leads (5) protrude from the back side ink layer (6).
3. The package frame structure according to claim 1, further comprising a metal plating layer (7), wherein the metal plating layer (7) is disposed on the front leads (3).
4. A manufacturing method of a packaging frame structure is characterized in that: etching the front surface of the substrate (1) to expose the front surface pins (3), arranging a front surface ink layer (4), wherein the front surface ink layer (4) covers the sunken area of the front surface of the substrate (1) after etching, and the front surface pins (3) protrude out of the front surface ink layer (4); the back of the substrate (1) is etched, the back pins (5) are exposed, a back printing ink layer (6) is arranged, the back printing ink layer (6) covers the sunken area of the etched back of the substrate (1), and the back pins (5) protrude out of the back printing ink layer (6).
5. The method for manufacturing a package frame structure according to claim 4, wherein the method for disposing the front ink layer (4) and the back ink layer (6) comprises:
brushing a layer of printing ink on the surface of the substrate (1);
carrying out pre-curing, exposure, development and photocuring on the surface of the substrate (1), and removing redundant ink on the surface of the pin to enable the pin to be higher than the ink;
curing the printing ink for one time through primary baking;
exposing and developing the cured printing ink to show the pins;
and secondary baking, namely performing secondary curing on the ink, hardening the ink by secondary baking, and fixing the ink on the substrate (1).
6. The method of claim 5, wherein: the ink is black ink.
7. The method of claim 5, wherein: after a layer of ink is brushed on the front surface of the substrate (1), the substrate (1) is placed in a vacuum box for vacuumizing.
8. The method of claim 5, wherein: the primary baking temperature is 75 +/-5 ℃ for 50 +/-10 min, and the secondary baking temperature is 175 +/-5 ℃ for 4 h.
9. A method for manufacturing a package frame structure according to any one of claims 4 to 8, the overall implementation method is as follows:
taking a substrate (1);
sticking a dry film (2) on the front surface of the substrate (1);
baking the dry film (2);
carrying out light exposure on the dry film (2);
developing the dry film (2) by a developing solution to remove the dry film (2) covering the area needing to be etched and expose the area needing to be etched on the front surface of the substrate (1);
etching the front surface of the substrate (1), wherein the area covered by the dry film (2) is not etched, and the etched area is sunken so as to expose the front surface pins (3);
printing ink on the front surface of the substrate (1);
pre-curing, exposing, developing and photo-curing the front surface of the substrate (1) to remove redundant ink on the surface of the front surface pin (3) so that the front surface pin (3) is higher than the ink;
sticking a dry film on the back of the substrate (1);
baking the dry film;
carrying out light exposure on the dry film;
developing the dry film through a developing solution to remove the dry film covering the area needing to be etched and expose the area needing to be etched on the back surface of the substrate (1);
etching the back surface of the substrate (1), wherein the area covered by the dry film is not etched, and the etched area is sunken, so that the back surface pins (5) are exposed;
brushing black ink on the back of the substrate (1);
carrying out pre-curing, exposure, development and photocuring on the back surface of the substrate (1), and removing redundant ink on the surface of the back surface pin (5) to enable the back surface pin (5) to be higher than the ink;
and electroplating metal on the front-surface pin (3).
10. A chip package structure, characterized in that, the package frame structure of any one of claims 1 to 8 is adopted to perform chip implantation on the front surface of a substrate (1) to form an array type assembly semi-finished product of an integrated circuit or discrete components;
routing the semi-finished product which has finished the chip implantation operation to form a lead;
encapsulating the semi-finished product after routing, and then curing to form an encapsulation;
electroplating metal on the pins (5) on the back of the substrate;
and cutting the semi-finished product to form a single product.
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| TW201123385A (en) * | 2009-12-31 | 2011-07-01 | Siliconware Precision Industries Co Ltd | Semiconductor package structure and fabrication method thereof |
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| CN108389805A (en) * | 2018-04-28 | 2018-08-10 | 长电科技（滁州）有限公司 | A kind of high reliability planar salient point type encapsulating method and structure |
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| US20050287710A1 (en) * | 2004-06-29 | 2005-12-29 | Advanced Semiconductor Engineering, Inc. | Leadless semiconductor package and method for manufacturing the same |
| TW201123385A (en) * | 2009-12-31 | 2011-07-01 | Siliconware Precision Industries Co Ltd | Semiconductor package structure and fabrication method thereof |
| CN108010899A (en) * | 2016-10-31 | 2018-05-08 | 长华科技股份有限公司 | Separated pre-formed packaging lead frame and manufacturing method thereof |
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