CN113178929B - Power device and battery management system - Google Patents

Abstract

The present disclosure provides a power device, which is used to detect the charging current and discharging current of a battery pack. The power device includes: a discharge control transistor and a charge control transistor, which are connected in series to form a control series circuit, and the series circuit is connected in a current loop between the battery pack side and the load/charger side; a charge detection transistor, the drain of the charge detection transistor is connected to the drain of the charge control transistor, and the source of the charge detection transistor is used as a charge current detection terminal; a discharge detection transistor, the drain of the discharge detection transistor is connected to the drain of the discharge control transistor, and the source of the discharge detection transistor is used as a discharge current detection terminal. The present disclosure also provides a battery management system.

Description

Power devices and battery management systems

Technical Field

The present disclosure provides a power device and a battery management system.

Background Art

Currently, rechargeable batteries are widely used in various fields. Rechargeable batteries are used to provide electrical energy to loads, and rechargeable batteries can also be charged by chargers.

During the charging and discharging process of a rechargeable battery, excessive charging current or discharging current may cause a safety accident. Therefore, it is necessary to detect the charging current and discharging current of the rechargeable battery to avoid the occurrence of safety accidents.

In the current detection process of the prior art, if a detection circuit with a large detection current is used, very high requirements will be placed on the subsequent circuits. If a small current is used for detection, the detection accuracy is not high.

Summary of the invention

In order to solve one of the above technical problems, the present disclosure provides a power device and a battery management system.

According to one aspect of the present disclosure, a power device is provided, the power device being used to detect a charging current and a discharging current of a battery pack, the power device comprising:

A discharge control transistor and a charge control transistor, wherein the discharge control transistor and the charge control transistor are connected in series to form a control series circuit, and the series circuit is connected in a current loop between the battery pack side and the load/charger side;

A charging detection transistor, wherein the drain of the charging detection transistor is connected to the drain of the charging control transistor, and the source of the charging detection transistor serves as a charging current detection terminal;

a discharge detection transistor, wherein the drain of the discharge detection transistor is connected to the drain of the discharge control transistor, and the source of the discharge detection transistor serves as a discharge current detection terminal; and

A sampling unit, wherein the sampling unit is connected to the discharge current detection terminal and the charge current detection terminal respectively,

Among them, the sampling unit includes a discharge sampling branch connected to the discharge current detection end and a charging sampling branch connected to the charging current detection end, and the sampling unit includes a sampling resistor. When the discharge current is sampled, the discharge current is sampled according to the voltage generated by the sampling resistor, and when the charging current is sampled, the charging current is sampled according to the voltage generated by the sampling resistor.

According to at least one embodiment of the present disclosure, the discharge sampling branch includes a first voltage fixing circuit and a first current mirror circuit.

The first voltage fixing circuit is directly or indirectly connected to the discharge current detection terminal, and the first voltage fixing circuit makes the source voltage of the discharge detection transistor equal to the source voltage of the discharge control transistor, and the first voltage fixing circuit allows the discharge detection current detected by the discharge detection transistor to flow into the first current mirror circuit, and the first current mirror circuit is used to mirror the discharge detection current to the sampling resistor.

According to at least one embodiment of the present disclosure, the first voltage fixing circuit includes a first operational amplifier and a first PMOS transistor, the source of the first PMOS transistor is connected to the source of the discharge detection transistor, the output of the first operational amplifier is connected to the gate of the first PMOS transistor, and the positive input of the first operational amplifier is connected to the negative voltage end of the battery pack, the negative input of the first operational amplifier is connected to the source of the first PMOS transistor, and the drain of the first PMOS transistor is connected to the inflow end of the first current mirror circuit.

According to at least one embodiment of the present disclosure, the charging sampling branch includes a second voltage fixing circuit, a second current mirror circuit and a third current mirror circuit.

The second voltage fixing circuit is directly or indirectly connected to the charging current detection terminal, and the second voltage fixing circuit makes the source voltage of the charging detection transistor equal to the source voltage of the charging control transistor, and the second voltage fixing circuit allows the charging detection current detected by the charging detection transistor to flow into the second current mirror circuit, the second current mirror circuit is used to mirror the charging detection current to the third current mirror circuit, and the third current mirror circuit is used to mirror the charging detection current to the sampling resistor.

According to at least one embodiment of the present disclosure, the second voltage fixing circuit includes a second operational amplifier and a second PMOS transistor, the source of the second PMOS transistor is connected to the source of the charging detection transistor, the output of the second operational amplifier is connected to the gate of the second PMOS transistor, and the positive input of the second operational amplifier is connected to the negative voltage end of the load/charger side, the negative input of the second operational amplifier is connected to the source of the second PMOS transistor, and the drain of the second PMOS transistor is connected to the inflow end of the second current mirror circuit.

According to at least one embodiment of the present disclosure, the method further includes:

a first charge pump circuit and a second charge pump circuit, wherein the first charge pump circuit generates a voltage lower than the negative voltage terminal voltage of the battery pack and provides the voltage to the outflow terminal of the first current mirror circuit, and the second charge pump circuit generates a voltage lower than the negative voltage terminal voltage of the load/charger side and provides the voltage to the outflow terminal of the second current mirror circuit; or

A charge pump circuit generates a voltage lower than the negative voltage terminal voltage of the battery pack and lower than the negative voltage terminal voltage of the load/charger side, and provides the voltage to the outflow terminals of the first current mirror circuit and the second current mirror circuit.

According to at least one embodiment of the present disclosure, the discharge sampling branch includes a first voltage fixing circuit and a first current mirror circuit.

The first voltage fixing circuit is directly or indirectly connected to the discharge current detection terminal, and the first voltage fixing circuit makes the source voltage of the discharge detection transistor equal to the source voltage of the discharge control transistor, and the first voltage fixing circuit allows the discharge detection current detected by the discharge detection transistor to flow into the first current mirror circuit, and the first current mirror circuit is used to mirror the discharge detection current to the sampling resistor.

According to at least one embodiment of the present disclosure, the first voltage fixing circuit includes a first operational amplifier and a first NMOS transistor, the source of the first NMOS transistor is connected to the source of the discharge detection transistor, the output of the first operational amplifier is connected to the gate of the first NMOS transistor, and the positive input of the first operational amplifier is connected to the negative voltage end of the battery pack, the negative input of the first operational amplifier is connected to the source of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the output of the first current mirror circuit.

According to at least one embodiment of the present disclosure, the charging sampling branch includes a second voltage fixing circuit, which is directly or indirectly connected to the charging current detection terminal, and the second voltage fixing circuit makes the source voltage of the charging detection transistor equal to the source voltage of the charging control transistor, and the second voltage fixing circuit allows the charging detection current detected by the charging detection transistor to flow to the sampling resistor.

According to at least one embodiment of the present disclosure, the second voltage fixing circuit includes a second operational amplifier and a second NMOS transistor, the source of the second NMOS transistor is connected to the source of the charging detection transistor, the output of the second operational amplifier is connected to the gate of the second NMOS transistor, and the positive input of the second operational amplifier is connected to the negative voltage terminal of the load/charger, the negative input of the second operational amplifier is connected to the source of the second NMOS transistor, and the drain of the second NMOS transistor is connected to the sampling resistor.

According to at least one embodiment of the present disclosure, a third operational amplifier is further included, wherein the sampling resistor is connected between one input terminal and the input terminal of the third operational amplifier, and the other input terminal of the third operational amplifier is connected to a first voltage, wherein the voltage value of the first voltage is less than the power supply voltage and greater than the ground voltage.

According to at least one embodiment of the present disclosure, the first voltage is a common mode voltage; and/or the sampling resistor is connected in parallel with a filter capacitor.

According to at least one embodiment of the present disclosure, a channel length-to-width ratio of the charge detection transistor and a channel length-to-width ratio of the charge control transistor are 1:M, where M is greater than 1.

According to at least one embodiment of the present disclosure, the number of the charging detection transistors is N, where N is an integer greater than or equal to 1, and the channel aspect ratio of the Nth charging detection transistor and the channel aspect ratio of the charging control transistor are 1:M to the N-1th power.

According to at least one embodiment of the present disclosure, the charge control transistor and the charge detection transistor are NMOS transistors, and the M value is 100.

According to at least one embodiment of the present disclosure, the number of the discharge detection transistors is N, where N is an integer greater than or equal to 1, and the channel aspect ratio of the Nth discharge detection transistor and the channel aspect ratio of the discharge control transistor are 1:M to the N-1th power.

According to at least one embodiment of the present disclosure, the discharge control transistor and the discharge detection transistor are NMOS transistors, and the M value is 100.

According to at least one embodiment of the present disclosure, a Zener diode is connected between the gate and the source of the charge control transistor, the charge detection transistor, the discharge control transistor, and the discharge detection transistor.

According to at least one embodiment of the present disclosure, the gates of the charge control transistor and the charge detection transistor are respectively connected to a charge control signal and a charge detection control signal through resistors, the charge control signal and the charge detection control signal are the same control signal or different control signals, and/or the charge detection control signals of the N charge detection transistors are the same control signal or different control signals; and

The gates of the discharge control transistor and the discharge detection transistor are respectively connected to a discharge control signal and a discharge detection control signal through resistors, and the discharge control signal and the discharge detection control signal are the same control signal or different control signals, and/or the discharge detection control signals of the N discharge detection transistors are the same control signal or different control signals.

According to at least one embodiment of the present disclosure, it also includes a first gating unit and a second gating unit, the first gating unit is respectively connected to N discharge detection transistors so that the N discharge detection transistors are switched through the first gating unit; the second gating unit is respectively connected to N charge detection transistors so that the N charge detection transistors are switched through the second gating unit.

According to another aspect of the present disclosure, a battery management system includes:

A power device as described in any one of the above items;

A current collection unit, wherein the current collection unit is connected to the charging current detection terminal and the discharging current detection terminal of the power device so as to collect the charging current and the discharging current of the battery pack.

According to at least one embodiment of the present disclosure, the method further includes:

A control unit provides the charging control signal, the charging detection control signal, the discharging control signal and the discharging detection control signal to the power device so as to control the charging and discharging of the battery pack.

According to at least one embodiment of the present disclosure, when the power device includes N charging detection transistors and/or N discharge detection transistors, the battery management system also includes a gating unit, and the gating unit selects one charging detection transistor and/or one discharge detection transistor among the N charging detection transistors and/or the N discharge detection transistors to obtain a current detection signal of the charging current and/or the discharging current.

According to at least one embodiment of the present disclosure, it also includes a detection current judgment unit, which is used to judge the size of the current detection signal, and the selection unit selects one charging detection transistor and/or one discharge detection transistor among the N charging detection transistors and/or the N discharge detection transistors based on the size of the current detection signal.

According to at least one embodiment of the present disclosure, the system further includes an analog-to-digital conversion unit, which converts the output signal of the current acquisition unit into a digital signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

FIG. 1 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

FIG. 2 shows a circuit diagram of a sampling unit according to an embodiment of the present disclosure.

FIG. 3 shows a circuit diagram of a sampling unit according to an embodiment of the present disclosure.

FIG. 4 shows a circuit diagram of a sampling unit according to an embodiment of the present disclosure.

FIG. 5 shows a circuit diagram of a sampling unit according to an embodiment of the present disclosure.

FIG. 6 shows a schematic diagram of a power device according to an embodiment of the present disclosure.

FIG. 7 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

FIG8 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

FIG. 9 shows a schematic diagram of an electric device according to an embodiment of the present disclosure.

FIG. 10 shows a schematic diagram of a power device according to an embodiment of the present disclosure.

FIG. 11 shows a schematic diagram of a power device according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

The present disclosure is further described in detail below in conjunction with the accompanying drawings and implementations. It is understood that the specific implementations described herein are only used to explain the relevant content, rather than to limit the present disclosure. It should also be noted that, for ease of description, only the parts related to the present disclosure are shown in the accompanying drawings.

It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure can be combined with each other. The technical solution of the present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

Unless otherwise specified, the exemplary embodiments/embodiments shown will be understood as providing exemplary features of various details of some ways in which the technical concept of the present disclosure can be implemented in practice. Therefore, unless otherwise specified, the features of the various embodiments/embodiments can be combined, separated, interchanged and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the accompanying drawings is generally used to make the boundaries between adjacent components clear. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the components shown, and/or any other characteristics, attributes, properties, etc. of the components. In addition, in the accompanying drawings, the sizes and relative sizes of the components may be exaggerated for clarity and/or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed in a different order than described. For example, two successively described processes can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same figure numbers represent the same components.

When a component is referred to as being "on" or "over," "connected to," or "coupled to" another component, the component may be directly on, directly connected to, or directly coupled to the other component, or intervening components may be present. However, when a component is referred to as being "directly on," "directly connected to," or "directly coupled to" another component, there are no intervening components. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, etc., with or without intervening components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "under," "beneath," "under," "down," "over," "upper," "above," "higher," and "side (e.g., as in "sidewall")," to describe the relationship of one component to another (other) component as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, components described as "under" or "beneath" other components or features would subsequently be positioned "over" the other components or features. Thus, the exemplary term "under" can encompass both the "above" and "below" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

The terms used here are for the purpose of describing specific embodiments, and are not intended to be restrictive. As used here, unless the context clearly indicates otherwise, the singular forms "one (kind, person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and/or "include" and their variations are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, parts, assemblies and/or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, parts, assemblies and/or their groups. It should also be noted that, as used here, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, so that they are used to explain the inherent deviations of the measured values, calculated values and/or the values provided that will be recognized by those of ordinary skill in the art.

According to one embodiment of the present disclosure, a power device is provided, which can be used to detect a charging current and a discharging current of a battery pack.

FIG1 shows a power device according to an embodiment of the present disclosure, which may include a discharge control transistor 1000 , a charge control transistor 2000 , a discharge detection transistor 3000 , a charge detection transistor 4000 , and a sampling unit 5000 .

Although FIG1 shows a plurality of discharge detection transistors 3010, 3020, ..., 30n0 and charge detection transistors 4010, 4020, ..., 40n0, one charge detection transistor and one discharge detection transistor may also be used in the present disclosure. The following will first be described by taking one charge detection transistor and one discharge detection transistor as an example.

The discharge control transistor 1000 and the charge control transistor 2000 are connected in series to form a control series circuit, and the series circuit is connected in the current loop between the battery pack side and the load/charger side. For example, in the present disclosure, the discharge control transistor 1000 and the charge control transistor 2000 can be NMOS transistors. Of course, those skilled in the art should understand that PMOS transistors can also be used. The discharge control transistor 1000 and the charge control transistor 2000 are connected in series to form a control series circuit that can be set in the loop on the low voltage side, and the discharge control transistor 1000 and the charge control transistor 2000 are connected in series to form a control series circuit that can be set in the loop on the high voltage side. The following will be explained by taking NMOS transistors and setting the low voltage side as an example. For PMOS transistors, or when they are set on the high voltage side, the principle is the same and will not be repeated here.

The drain of the discharge detection transistor 3000 is connected to the drain (D terminal) of the discharge control transistor 1000 , and the source of the discharge detection transistor 3000 serves as a discharge current detection terminal.

The drain of the charge detection transistor 4000 is connected to the drain (D terminal) of the charge control transistor 2000, and the source of the charge detection transistor 4000 serves as a charge current detection terminal.

The sampling unit 5000 is connected to the discharge current detection terminal and the charge current detection terminal respectively, wherein the sampling unit 5000 includes a discharge sampling branch connected to the discharge current detection terminal and a charge sampling branch connected to the charge current detection terminal, and the sampling unit 5000 includes a sampling resistor, and when the discharge current is sampled, the discharge current is sampled according to the voltage generated by the sampling resistor, and when the charge current is sampled, the charge current is sampled according to the voltage generated by the sampling resistor. The sampling resistor can be a built-in resistor of the device or an external resistor.

2 and 3 show circuit diagrams of a sampling unit according to an embodiment of the present disclosure.

FIG. 2 shows a discharge current detection situation, and FIG. 3 shows a charge current detection situation.

The discharge sampling branch includes a first voltage fixing circuit 5010 and a first current mirror circuit 5020. The first voltage fixing circuit 5010 is directly or indirectly connected to the discharge current detection terminal (the source of the transistor 300), and the first voltage fixing circuit 5010 makes the source voltage of the discharge detection transistor 3000 equal to the source voltage of the discharge control transistor 1000, and the first voltage fixing circuit 5010 allows the discharge detection current I _DS detected by the discharge detection transistor 3000 to flow into the first current mirror circuit 5020, and the first current mirror circuit 5020 is used to mirror the discharge detection current to the sampling resistor 5030.

The first voltage fixing circuit 5010 includes a first operational amplifier 5011 and a first PMOS transistor 5012, the source of the first PMOS transistor 5012 is connected to the source of the discharge detection transistor 3000, the output of the first operational amplifier 5011 is connected to the gate of the first PMOS transistor 5012, and the positive input of the first operational amplifier 5011 is connected to the negative voltage terminal B- of the battery pack, the negative input of the first operational amplifier 511 is connected to the source of the first PMOS transistor 5012, and the drain of the first PMOS transistor 5012 is connected to the inflow end of the first current mirror circuit 5020.

The first current mirror circuit includes an NMOS transistor 5021 and an NMOS transistor 5022, wherein the gates of the NMOS transistor 5021 and the NMOS transistor 5022 are connected, the drain of the NMOS transistor 5021 is connected to the output end of the first voltage fixing circuit 5010, the source of the NMOS transistor 5021 is connected to the -VDD end, the source of the NMOS transistor 5022 is connected to the -VDD end, the drain of the NMOS transistor 5022 is connected to one end of the sampling resistor 5030, and the other end of the sampling resistor 5030 can be grounded.

In this way, the corresponding detection value of the discharge current can be obtained by detecting the voltage VSNS formed on the sampling resistor by the discharge current.

As shown in FIG. 3 , the charging sampling branch includes a second voltage fixing circuit 5040 , a second current mirror circuit 5050 and a third current mirror circuit 5060 .

The second voltage fixing circuit 5040 is directly or indirectly connected to the charging current detection terminal (the source of the charging detection transistor 4000), and the second voltage fixing circuit 5040 makes the source voltage of the charging detection transistor 4000 equal to the source voltage of the charging control transistor, and the second voltage fixing circuit 5040 allows the charging detection current I _CS detected by the charging detection transistor 4000 to flow into the second current mirror circuit 5050, and the second current mirror circuit 5050 is used to mirror the charging detection current to the third current mirror circuit 5060, and the third current mirror circuit 5060 is used to mirror the charging detection current to the sampling resistor.

The second voltage fixing circuit 5040 includes a second operational amplifier 5041 and a second PMOS transistor 5042, the source of the second PMOS transistor 5042 is connected to the source of the charging detection transistor, the output of the second operational amplifier 5041 is connected to the gate of the second PMOS transistor 5042, and the positive input of the second operational amplifier 5041 is connected to the negative voltage end of the load/charger side, the negative input of the second operational amplifier 5041 is connected to the source of the second PMOS transistor 5042, and the drain of the second PMOS transistor 5042 is connected to the inflow end of the second current mirror circuit 5050.

The second current mirror circuit 5050 includes an NMOS transistor 5051 and an NMOS transistor 5052, wherein the gates of the NMOS transistor 5051 and the NMOS transistor 5052 are connected and connected to the drain of the NMOS transistor 5051, the drain of the NMOS transistor 5051 is connected to the output end of the second voltage fixing circuit 5040, the source of the NMOS transistor 5051 is connected to the -VDD end, the source of the NMOS transistor 5052 is connected to the -VDD end, and the drain of the NMOS transistor 5052 is connected to the third mirror circuit 5060.

The third current mirror circuit 5060 includes a PMOS transistor 5061 and a PMOS transistor 5062. The gates of the PMOS transistor 5061 and the PMOS transistor 5062 are connected, and the drain of the PMOS transistor 5061 is connected. The sources of the PMOS transistor 5061 and the PMOS transistor 5062 are connected to the power supply voltage VDD. The drain of the PMOS transistor 5062 is connected to one end of the sampling resistor 5030, and the other end of the sampling resistor 5030 can be grounded.

In this way, the corresponding discharge current detection value can be obtained by detecting the voltage VSNS formed on the sampling resistor by the charging detection current.

According to a further embodiment of the present disclosure, it further includes: a first charge pump circuit CP1 and a second charge pump circuit CP2, the first charge pump circuit CP1 generates a voltage (-VDD) lower than the voltage of the negative voltage terminal B- of the battery pack and provides it to the outflow end of the first current mirror circuit 5020, and the second charge pump circuit CP2 generates a voltage (-VDD) lower than the voltage of the negative voltage terminal P- on the load/charger side and provides it to the outflow end of the second current mirror circuit 5050. Although shown in the form of voltage (-VDD) in the figure, the charge pump can also generate voltages of other voltage values.

According to a further embodiment, the above two charge pump circuits can be implemented by a charge pump circuit, which generates a voltage lower than the negative voltage terminal voltage of the battery pack and lower than the negative voltage terminal voltage of the load/charger side, and is provided to the outflow end of the first current mirror circuit 5020 and the second current mirror circuit 5050.

According to another embodiment of the present disclosure, a circuit diagram of another sampling unit is shown in Figures 4 and 5. Figure 4 shows a discharge detection situation, and Figure 5 shows a charge detection situation.

The discharge sampling branch includes a first voltage fixing circuit 5010 and a first current mirror circuit 5020.

The first voltage fixing circuit 5010 is directly or indirectly connected to the discharge current detection end, and the first voltage fixing circuit 5010 makes the source voltage of the discharge detection transistor equal to the source voltage of the discharge control transistor, and the first voltage fixing circuit 5010 allows the discharge detection current detected by the discharge detection transistor to flow into the first current mirror circuit 5020, and the first current mirror circuit 5020 is used to mirror the discharge detection current to the sampling resistor 5030.

The first voltage fixing circuit 5010 includes a first operational amplifier 5011 and a first NMOS transistor 5012, the source of the first NMOS transistor 5012 is connected to the source of the discharge detection transistor, the output of the first operational amplifier 5011 is connected to the gate of the first NMOS transistor 5012, and the positive input of the first operational amplifier 5011 is connected to the negative voltage end of the battery pack, the negative input of the first operational amplifier 5011 is connected to the source of the first NMOS transistor 5012, and the drain of the first NMOS transistor 5012 is connected to the output of the first current mirror circuit 5020.

The charging sampling branch includes a second voltage fixing circuit 5040, which is directly or indirectly connected to the charging current detection terminal, and the second voltage fixing circuit 5040 makes the source voltage of the charging detection transistor equal to the source voltage of the charging control transistor, and the second voltage fixing circuit 5040 allows the charging detection current detected by the charging detection transistor to flow to the sampling resistor 5030.

The second voltage fixing circuit 5040 includes a second operational amplifier 5041 and a second NMOS transistor 5042, the source of the second NMOS transistor 5042 is connected to the source of the charging detection transistor 4000, the output of the second operational amplifier 5041 is connected to the gate of the second NMOS transistor 5042, and the positive input of the second operational amplifier 5041 is connected to the negative voltage end of the load/charger, the negative input of the second operational amplifier 5041 is connected to the source of the second NMOS transistor 5042, and the drain of the second NMOS transistor 5042 is connected to the sampling resistor 5030.

The third operational amplifier 5070 is also included. The sampling resistor 5030 is connected between one input terminal and the input terminal of the third operational amplifier 5070. The other input terminal of the third operational amplifier 5070 is connected to a first voltage. The voltage value of the first voltage is less than the power supply voltage and greater than the ground voltage. The first voltage can be a common mode voltage V _CM .

In addition, in FIG. 4 and FIG. 5 , as shown in FIG. 4 , a filter capacitor 5080 may be connected in parallel at both ends of the sampling resistor.

According to one embodiment of the present disclosure, a power device is provided.

6 shows a power device 10 according to an embodiment of the present disclosure. The power device is used to control the charging and discharging of a battery pack and detect the charging current and the discharging current of the battery pack.

As shown in Fig. 6, the power device 10 may include: a charge control transistor 110 and a charge detection transistor 120. In the present disclosure, an NMOS transistor is used as an example for description, but those skilled in the art should understand that it may also be a PMOS transistor.

The gate of the charge control transistor 110 is connected to the charge control signal GMA to control the charging of the battery pack, wherein the source of the charge control transistor 110 is connected to one end SMA of the battery pack. When only the charge control transistor is included, the drain of the charge control transistor can be connected to the load/charger terminal. The charge control transistor can include a parasitic diode.

In addition, a voltage regulator diode 510 may be connected between the gate and source of the charge control transistor 110 to prevent the gate of the charge control transistor 110 from being broken down. In FIG6 , a Zener diode is shown, and other types of diodes may also be selected, which may include two Zener diodes connected in reverse series.

Furthermore, the gate of the charging control transistor 110 may be connected to the charging control signal GMA via a resistor 111 to provide electrostatic protection, wherein the resistance of the resistor 111 may be 1K ohm.

The charging detection transistor 120 detects the charging current of the battery pack, the drain of the charging detection transistor 120 is connected to the drain of the charging control transistor 110, the gate of the charging detection transistor 120 is connected to the charging control signal GMA, and the source of the charging detection transistor serves as the charging current detection terminal SMA1. The charging detection transistor 120 may include a parasitic diode.

In addition, a voltage regulator diode 411 may be connected between the gate and source of the charge detection transistor 120 to prevent the gate of the charge detection transistor 120 from being broken down. In FIG6 , a Zener diode is shown, and other types of diodes may also be selected, which may include two Zener diodes connected in reverse series.

Furthermore, the gate of the charge detection transistor 120 may be connected to the charge control signal GMA via a resistor 311 to provide electrostatic protection, wherein the resistance of the resistor 111 may be 100K ohms.

The channel length-to-width ratio of the charge detection transistor 211 and the channel length-to-width ratio of the charge control transistor 110 are 1:M, where M is greater than 1. For example, the value of M may be 100, 1000, 10000, and so on.

The number of the charge detection transistors 211 is N, where N is an integer greater than or equal to 1, and the channel length-to-width ratio of the Nth charge detection transistor and the channel length-to-width ratio of the charge control transistor are 1:M to the N-1th power, where i is an integer greater than or equal to 1, and the value of i changes with the value of N. For example, the figure shows that N charge detection transistors 211, 212, ..., 21n are included, and they have corresponding resistors 311, 312, ..., 31n, and corresponding diodes 411, 412, ..., 41n. The connection method of each charge detection transistor is the same, and the difference lies in the different ratios of the channel length-to-width ratio with the charge control transistor 110. The connection method will not be repeated here.

The value of M is an integer multiple of 10, preferably 100. The channel length-to-width ratio of the Nth charge detection transistor to the charge control transistor is 1:M to the power of N-1.

For example, the channel length-width ratio of transistor 211 to transistor 110 is 1:100, the channel length-width ratio of transistor 212 to transistor 110 is 1:1000, the channel length-width ratio of the third transistor to transistor 110 is 1:10000, and the channel length-width ratio of the Nth transistor 21n to transistor 110 is 1:100 to the N-1th power.

According to a further embodiment of the present disclosure, the power device 10 further includes: a discharge control transistor 120, the gate of which is connected to a discharge control signal GMB to control the discharge of the battery pack, wherein the drain of the discharge control transistor 120 is connected to the drain of the charge control transistor 110, and the source of the discharge control transistor 120 is connected to a terminal SMB of the load/charger. The discharge control transistor may include a parasitic diode.

In addition, a voltage regulator diode 520 may be connected between the gate and source of the discharge control transistor 120 to prevent the gate of the discharge control transistor 120 from being broken down. In FIG6 , a Zener diode is shown, and other types of diodes may also be selected, which may include two Zener diodes connected in reverse series.

Furthermore, the gate of the discharge control transistor 120 may be connected to the discharge control signal GMB via a resistor 121 to provide electrostatic protection, wherein the resistance of the resistor 121 may be 1K ohm.

In addition, a voltage regulator diode 421 may be connected between the gate and source of the discharge detection transistor 221 to prevent the gate of the discharge detection transistor 221 from being broken down. In FIG6 , a Zener diode is shown, and other types of diodes may also be selected, which may include two Zener diodes connected in reverse series.

Furthermore, the gate of the discharge detection transistor 221 may be connected to the discharge control signal GMB via a resistor 321 to provide electrostatic protection, wherein the resistance of the resistor 321 may be 100K ohms.

The channel length-to-width ratio of the discharge detection transistor 221 and the channel length-to-width ratio of the discharge control transistor 120 are 1:M, where M is greater than 1. For example, the value of M may be 100, 1000, 10000, and so on.

The number of discharge detection transistors 221 is N, where N is an integer greater than or equal to 1, and the channel length-width ratio of the Nth discharge detection transistor and the channel length-width ratio of the discharge control transistor are 1:M to the N-1th power, where i is an integer greater than or equal to 1, and the value of i changes with the value of N. For example, the figure shows N discharge detection transistors 221, 222, ..., 22n, and they have corresponding resistors 321, 322, ..., 32n, and corresponding diodes 421, 422, ..., 42n. The connection method of each discharge detection transistor is the same, and the difference lies in the different ratios of the channel length-width ratio to the discharge control transistor 120. The connection method will not be repeated here.

The value of M is an integer multiple of 10, preferably 100. The channel length-to-width ratio of the Nth discharge detection transistor to the discharge control transistor is 1:M to the power of N-1.

For example, the channel length-width ratio of transistor 221 to transistor 120 is 1:100, the channel length-width ratio of transistor 222 to transistor 120 is 1:1000, the channel length-width ratio of the third transistor to transistor 120 is 1:10000, and the channel length-width ratio of the Nth transistor 22n to transistor 120 is 1:100 to the N-1th power.

The first temperature detection unit 610 is connected to the source of the charge control transistor 110 and the second temperature detection unit 620 is connected to the source of the discharge control transistor 120. The first temperature detection unit and the second temperature detection unit are used to detect the temperature of the battery pack. The first temperature detection unit is a first diode, and the second temperature detection unit is a second diode. The cathode of the first diode is connected to the source of the charge control transistor, and the cathode of the second diode is connected to the source of the discharge control transistor, and the anodes of the first diode and the second diode serve as temperature detection output terminals. The temperature detection output terminal of the first temperature detection unit is D1P, and the temperature detection output terminal of the second temperature detection unit is D2P. The anode of the first diode can be connected to the resistor 611, and the other end of the resistor 611 can be used as the temperature detection output terminal D1P, and the anode of the second diode can be connected to the resistor 612, and the other end of the resistor 612 can be used as the temperature detection output terminal D2P.

In the present disclosure, the charge control transistor and the charge detection transistor are transistors of the same type, the discharge control transistor and the discharge detection transistor are transistors of the same type, or all four are MOS transistors of the same type.

Those skilled in the art will understand that the larger the channel width-to-length ratio of a MOS transistor is, the smaller the on-resistance is, and thus the larger the current flowing through it is. In the present disclosure, by using a charging and discharging control transistor with a large width-to-length ratio, its on-resistance will be very small, so that the energy consumed in the charging and discharging circuit is very small. When it is necessary to detect the current, a detection transistor with a relatively small channel width-to-length ratio is used, so that its on-resistance is large, and thus the current flowing through it is small, which can facilitate detection without the need for subsequent acquisition units and other requirements for withstanding large currents. At the same time, since the detection transistor is in the detection branch, this will not affect the normal charging and discharging circuit, such as consuming the battery's electrical energy.

In the case of including multiple charging detection transistors, through the external circuit of the device, it is possible to switch which charging detection transistor to use for detection according to the size of the detected charging current. For example, the detection current is obtained through transistor 211. When the detection current is too large, it can be switched to transistor 212 to obtain the detection current. When it is larger, it can also be switched to other transistors. When the detected charging current is too small, it can also be switched in reverse order. In addition, it is possible to select which charging detection transistor to use to detect the charging current according to the specific value of the detected charging current.

In the case of including multiple discharge detection transistors, through the external circuit of the device, it is possible to switch which discharge detection transistor to use for detection according to the size of the detected discharge current. For example, the detection current is obtained through transistor 221. When the detection current is too large, it can be switched to transistor 222 to obtain the detection current. When it is larger, it can also be switched to other transistors. When the detected discharge current is too small, it can also be switched in reverse order. In addition, it is possible to select which discharge detection transistor to use to detect the discharge current according to the specific value of the detected discharge current.

FIG. 7 shows a schematic block diagram of a battery management system according to an embodiment of the present disclosure.

The power device 10 can be connected in series between the battery pack 20 and the charger/load to control charging and discharging, detect charging current and discharging current, and detect temperature. The temperature detection terminal can be connected to an external acquisition unit.

The control unit 30 may provide control signals GMA and GMB to the power device 10 .

FIG8 shows a schematic block diagram of a battery management system according to an embodiment of the present disclosure.

The battery management system may include the above-mentioned power device. The description of the above-mentioned power device is incorporated into this section as a whole.

The battery management system may include a current acquisition unit, which is connected to a charging current detection terminal and a discharging current detection terminal of a power device so as to acquire a charging current and a discharging current of a battery pack.

The battery management system may further include: a control unit, which provides a charging control signal and a discharging control signal to the power device so as to control the charging and discharging of the battery pack.

When the power device includes N charging detection transistors and/or N discharge detection transistors, the battery management system may further include a gating unit, and the gating unit selects one charging detection transistor and/or one discharge detection transistor among the N charging detection transistors and/or the N discharge detection transistors to obtain a current detection signal of the charging current and/or the discharging current.

The battery management system may further include a detection current judgment unit, which is used to judge the size of a current detection signal, and a selection unit to select a charging detection transistor and/or a discharge detection transistor among N charging detection transistors and/or N discharge detection transistors based on the size of the current detection signal.

The battery management system may further include an analog-to-digital conversion unit, which converts the output signal of the current acquisition unit into a digital signal.

For example, the current judgment unit controls the switching of the gating unit according to the charging current and discharging current collected by the collection unit to determine which charging detection transistor and/or discharging detection transistor to select. In this way, a current of a suitable size can be selected for collection to prevent damage to the device when the current is too large and loss of sampling accuracy when the current is too small.

In addition, the present disclosure may further include an adjustment unit after the analog-to-digital conversion unit to adjust the current detection value according to the ratio of the channel width-to-length ratio between the charging control transistor and the charging detection transistor, so that the current detection value truly reflects the actual current.

For example, at a certain stage, the detection is performed with the transistor 211 whose width-to-length ratio is 100 times of the charging control transistor 110, and at another stage, the detection is performed with the transistor 212 whose width-to-length ratio is 1000 times of the charging control transistor 110. If no adjustment is made later, the ratio of the two values will not be consistent. Therefore, in the present disclosure, the subsequent current detection value can be adjusted according to the setting of the width-to-length ratio.

In addition, the above description is made in the form of a power device, but in the present disclosure, each transistor does not need to be made into a power device, but can be made into a detection circuit. Below, the detection circuit is briefly described, and the overall content of the power device is introduced in this section, and other parts will not be repeated.

The detection circuit is used to detect the charging current and discharging current of the battery pack. The charging control transistor controls the discharging of the battery pack. The gate of the charging control transistor is connected to the charging control signal to control the charging of the battery pack, wherein the source of the charging control transistor is connected to one end of the battery pack. The discharging control transistor controls the discharging of the battery pack. The gate of the discharging control transistor is connected to the discharging control signal to control the discharging of the battery pack. The drain of the discharging control transistor is connected to the drain of the charging control transistor, and the source of the discharging control transistor is connected to one end of the load/charger. The detection circuit includes: a charging detection transistor, the charging detection transistor detects the charging current of the battery pack, the drain of the charging detection transistor is connected to the drain of the charging control transistor, the gate of the charging detection transistor is connected to the charging control signal, and the source of the charging detection transistor serves as a charging current detection end; and

A discharge detection transistor, the discharge detection transistor detects the discharge current of the battery pack, the drain of the discharge detection transistor is connected to the drain of the discharge control transistor, the gate of the discharge detection transistor is connected to the discharge control signal, and the source of the discharge detection transistor serves as a discharge current detection terminal, wherein the channel length-to-width ratio of the charge detection transistor and the channel length-to-width ratio of the charge control transistor are 1:M, and the channel length-to-width ratio of the discharge detection transistor and the channel length-to-width ratio of the discharge control transistor are 1:M, wherein M is greater than 1.

The number of charge detection transistors is N, where N is an integer greater than or equal to 1, and the channel length-to-width ratio of the Nth discharge detection transistor is 1:M to the N-1th power; and the number of discharge detection transistors is N, where N is an integer greater than or equal to 1, and the channel length-to-width ratio of the Nth discharge detection transistor is 1:M to the N-1th power.

The charge control transistor and the charge detection transistor are NMOS transistors, and the M value is an integer multiple of 10, preferably 100; the discharge control transistor and the discharge detection transistor are NMOS transistors, and the M value is an integer multiple of 10, preferably 100.

A first temperature detection unit is connected to the source of the charge control transistor and a second temperature detection unit is connected to the source of the discharge control transistor. The first temperature detection unit and the second temperature detection unit are used to detect the temperature of the battery pack.

The first temperature detection unit is a first diode, the second temperature detection unit is a second diode, the cathode of the first diode is connected to the source of the charge control transistor, the cathode of the second diode is connected to the source of the discharge control transistor, and the anodes of the first diode and the second diode serve as temperature detection output terminals.

A Zener diode is connected between the gate and source of the charge control transistor, the charge detection transistor, the discharge control transistor and the discharge detection transistor.

The gates of the charge control transistor and the charge detection transistor are connected to the charge control signal through resistors, respectively. The gates of the discharge control transistor and the discharge detection transistor are connected to the discharge control signal through resistors, respectively.

The present disclosure also provides an electric device, such as an electric tool, a portable terminal, an electric car, etc. As shown in FIG9 , the electric device may include the above-mentioned power device, battery, battery management system, or detection circuit, etc.

In addition, Figures 10 and 11 show optional implementations according to the present disclosure. The difference between Figure 6 and Figure 10 is that the charge control transistor is controlled by a separate control signal GMA, while multiple charge detection transistors are controlled by the same control signal GMA1; the discharge control transistor is controlled by a separate control signal GMB, while multiple discharge detection transistors are controlled by the same control signal GMB1. The difference between Figure 11 and Figure 10 is that multiple charge detection transistors are controlled by multiple control signals GMA1, GMA2, ..., GMAn respectively; multiple discharge detection transistors are controlled by multiple control signals GMB1, GMB2, ..., GMBn respectively.

In the description of this specification, the description with reference to the terms "one embodiment/method", "some embodiments/methods", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment/method or example are included in at least one embodiment/method or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment/method or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments/methods or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments/methods or examples described in this specification and the features of the different embodiments/methods or examples, unless they are contradictory.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Those skilled in the art should understand that the above embodiments are only for the purpose of clearly illustrating the present disclosure, and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications may be made based on the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims (23)

1. A power device, characterized in that the power device is used to detect the charging current and discharging current of a battery pack, and the power device comprises: A discharge control transistor and a charge control transistor, wherein the discharge control transistor and the charge control transistor are connected in series to form a control series circuit, and the series circuit is connected in a current loop between the battery pack side and the load/charger side; A charging detection transistor, wherein the drain of the charging detection transistor is connected to the drain of the charging control transistor, and the source of the charging detection transistor serves as a charging current detection terminal; a discharge detection transistor, wherein the drain of the discharge detection transistor is connected to the drain of the discharge control transistor, and the source of the discharge detection transistor serves as a discharge current detection terminal; and A sampling unit, wherein the sampling unit is connected to the discharge current detection terminal and the charge current detection terminal respectively, Wherein, the sampling unit includes a discharge sampling branch connected to the discharge current detection end and a charge sampling branch connected to the charge current detection end, and the sampling unit includes a sampling resistor, when the discharge current is sampled, the discharge current is sampled according to the voltage generated by the sampling resistor, and when the charge current is sampled, the charge current is sampled according to the voltage generated by the sampling resistor; The discharge sampling branch includes a first voltage fixing circuit and a first current mirror circuit, the first voltage fixing circuit is directly or indirectly connected to the discharge current detection terminal, and the first voltage fixing circuit makes the source voltage of the discharge detection transistor equal to the source voltage of the discharge control transistor, and the first voltage fixing circuit allows the discharge detection current detected by the discharge detection transistor to flow into the first current mirror circuit, and the first current mirror circuit is used to mirror the discharge detection current to the sampling resistor; The charging sampling branch includes a second voltage fixing circuit, a second current mirror circuit and a third current mirror circuit. The second voltage fixing circuit is directly or indirectly connected to the charging current detection terminal, and the second voltage fixing circuit makes the source voltage of the charging detection transistor equal to the source voltage of the charging control transistor, and the second voltage fixing circuit allows the charging detection current detected by the charging detection transistor to flow into the second current mirror circuit. The second current mirror circuit is used to mirror the charging detection current to the third current mirror circuit, and the third current mirror circuit is used to mirror the charging detection current to the sampling resistor. 2. The power device as described in claim 1 is characterized in that the first voltage fixing circuit includes a first operational amplifier and a first PMOS transistor, the source of the first PMOS transistor is connected to the source of the discharge detection transistor, the output of the first operational amplifier is connected to the gate of the first PMOS transistor, and the positive input of the first operational amplifier is connected to the negative voltage end of the battery pack, the negative input of the first operational amplifier is connected to the source of the first PMOS transistor, and the drain of the first PMOS transistor is connected to the inflow end of the first current mirror circuit. 3. The power device according to claim 1, characterized in that the second voltage fixing circuit includes a second operational amplifier and a second PMOS transistor, the source of the second PMOS transistor is connected to the source of the charging detection transistor, the output of the second operational amplifier is connected to the gate of the second PMOS transistor, and the positive input of the second operational amplifier is connected to the negative voltage end of the load/charger side, the negative input of the second operational amplifier is connected to the source of the second PMOS transistor, and the drain of the second PMOS transistor is connected to the inflow end of the second current mirror circuit. 4. The power device according to claim 2 or 3, further comprising: a first charge pump circuit and a second charge pump circuit, wherein the first charge pump circuit generates a voltage lower than the negative voltage terminal voltage of the battery pack and provides the voltage to the outflow terminal of the first current mirror circuit, and the second charge pump circuit generates a voltage lower than the negative voltage terminal voltage of the load/charger side and provides the voltage to the outflow terminal of the second current mirror circuit; or A charge pump circuit generates a voltage lower than the negative voltage terminal voltage of the battery pack and lower than the negative voltage terminal voltage of the load/charger side, and provides the voltage to the outflow terminals of the first current mirror circuit and the second current mirror circuit. 5. The power device according to claim 1, wherein the discharge sampling branch comprises a first voltage fixing circuit and a first current mirror circuit. The first voltage fixing circuit is directly or indirectly connected to the discharge current detection terminal, and the first voltage fixing circuit makes the source voltage of the discharge detection transistor equal to the source voltage of the discharge control transistor, and the first voltage fixing circuit allows the discharge detection current detected by the discharge detection transistor to flow into the first current mirror circuit, and the first current mirror circuit is used to mirror the discharge detection current to the sampling resistor. 6. The power device as described in claim 5 is characterized in that the first voltage fixing circuit includes a first operational amplifier and a first NMOS transistor, the source of the first NMOS transistor is connected to the source of the discharge detection transistor, the output of the first operational amplifier is connected to the gate of the first NMOS transistor, and the positive input of the first operational amplifier is connected to the negative voltage end of the battery pack, the negative input of the first operational amplifier is connected to the source of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the output of the first current mirror circuit. 7. The power device according to claim 1 is characterized in that the charging sampling branch includes a second voltage fixing circuit, the second voltage fixing circuit is directly or indirectly connected to the charging current detection terminal, and the second voltage fixing circuit makes the source voltage of the charging detection transistor equal to the source voltage of the charging control transistor, and the second voltage fixing circuit allows the charging detection current detected by the charging detection transistor to flow to the sampling resistor. 8. The power device according to claim 7, characterized in that the second voltage fixing circuit includes a second operational amplifier and a second NMOS transistor, the source of the second NMOS transistor is connected to the source of the charging detection transistor, the output of the second operational amplifier is connected to the gate of the second NMOS transistor, and the positive input of the second operational amplifier is connected to the negative voltage terminal of the load/charger, the negative input of the second operational amplifier is connected to the source of the second NMOS transistor, and the drain of the second NMOS transistor is connected to the sampling resistor. 9. The power device according to any one of claims 5 to 8, characterized in that it also includes a third operational amplifier, wherein the sampling resistor is connected between one input terminal and the input terminal of the third operational amplifier, and the other input terminal of the third operational amplifier is connected to a first voltage, and the voltage value of the first voltage is less than the power supply voltage and greater than the ground voltage. 10. The power device according to claim 9, characterized in that: The first voltage is a common mode voltage; and/or The sampling resistor is connected in parallel with a filter capacitor. 11 . The power device according to claim 1 , wherein a channel length-to-width ratio of the charge detection transistor and a channel length-to-width ratio of the charge control transistor are 1:M, wherein M is greater than 1. 12. The power device according to claim 1, characterized in that the number of the charging detection transistors is N, wherein N is an integer greater than or equal to 1, and the channel length-to-width ratio of the Nth charging detection transistor and the channel length-to-width ratio of the charging control transistor are 1:M to the N-1th power. 13 . The power device according to claim 12 , wherein the charge control transistor and the charge detection transistor are NMOS transistors, and the M value is 100. 14. The power device according to claim 13, characterized in that the number of the discharge detection transistors is N, wherein N is an integer greater than or equal to 1, and the channel length-to-width ratio of the Nth discharge detection transistor and the channel length-to-width ratio of the discharge control transistor are 1:M to the N-1th power. 15 . The power device according to claim 14 , wherein the discharge control transistor and the discharge detection transistor are NMOS transistors, and the M value is 100. 16 . The power device according to claim 15 , wherein a Zener diode is connected between the gate and source of the charge control transistor, the charge detection transistor, the discharge control transistor and the discharge detection transistor. 17. The power device according to claim 15, characterized in that: The gates of the charge control transistor and the charge detection transistor are respectively connected to the charge control signal and the charge detection control signal through resistors, the charge control signal and the charge detection control signal are the same control signal or different control signals, and/or the charge detection control signals of the N charge detection transistors are the same control signal or different control signals; and The gates of the discharge control transistor and the discharge detection transistor are respectively connected to a discharge control signal and a discharge detection control signal through resistors, and the discharge control signal and the discharge detection control signal are the same control signal or different control signals, and/or the discharge detection control signals of the N discharge detection transistors are the same control signal or different control signals. 18. The power device as described in claim 17 is characterized in that it also includes a first gating unit and a second gating unit, the first gating unit is connected to N discharge detection transistors respectively so that the connection of the N discharge detection transistors is switched through the first gating unit; the second gating unit is connected to N charge detection transistors respectively so that the connection of the N charge detection transistors is switched through the second gating unit. 19. A battery management system, comprising: A power device as claimed in any one of claims 1 to 18; A current collection unit, wherein the current collection unit is connected to the charging current detection terminal and the discharging current detection terminal of the power device so as to collect the charging current and the discharging current of the battery pack. 20. The battery management system according to claim 19, further comprising: A control unit provides a charging control signal, a charging detection control signal, a discharging control signal and a discharging detection control signal to the power device so as to control the charging and discharging of the battery pack. 21. The battery management system as described in claim 20 is characterized in that when the power device includes N charging detection transistors and/or N discharge detection transistors, the battery management system also includes a gating unit, and the gating unit selects one charging detection transistor and/or one discharge detection transistor among the N charging detection transistors and/or the N discharge detection transistors to obtain a current detection signal of the charging current and/or the discharging current. 22. The battery management system as described in claim 21 is characterized in that it also includes a detection current judgment unit, which is used to judge the size of the current detection signal, and the selection unit selects a charging detection transistor and/or a discharge detection transistor among the N charging detection transistors and/or the N discharge detection transistors based on the size of the current detection signal. 23 . The battery management system according to claim 19 , further comprising an analog-to-digital conversion unit, which converts the output signal of the current acquisition unit into a digital signal.