CN113176799B - A chip pin circuit, chip and device - Google Patents

Abstract

An embodiment of the present invention discloses a chip pin circuit, comprising: a chip pin, a reference voltage circuit, and a comparison circuit, wherein the comparison circuit includes a plurality of comparators, and each of the comparators is connected to the chip pin and receives the first signal from the chip pin, the reference voltage circuit generates a plurality of reference voltages and outputs them to the corresponding comparators, one of the comparators compares the first signal and the reference voltage, The first control signal is generated and transmitted to the internal circuit of the chip and the other comparator, and the internal circuit of the chip and the other comparator are controlled. In the chip pin circuit provided by the embodiment of the present invention, after the chip pin receives a signal, only part of the comparison circuit can be turned on to receive and convert the signal, so as to achieve the purpose of saving power consumption.

Description

A chip pin circuit, chip and device

technical field

The present invention relates to the technical field of integrated circuits, and in particular, to a chip pin circuit and a chip and device including the same.

Background technique

With the development of information technology, the chip needs to integrate more and more functions, and it needs to receive and convert more digital control signals or analog signals. The number of pins on the chip is also increasing. Power consumption is also increasing.

SUMMARY OF THE INVENTION

The problem solved by the present invention is to achieve the purpose of saving power consumption while not affecting the signal received and converted by the chip pin circuit.

In order to solve the above problem, an embodiment of the present invention provides a chip pin circuit, which includes: a chip pin, a reference voltage circuit, and a comparison circuit, wherein the comparison circuit includes a plurality of comparators, and each of the comparators Connecting to the chip pins and receiving the first signal from the chip pins, the reference voltage circuit generates a plurality of reference voltages and outputs them to the corresponding comparators, one of the comparators compares the first signals and the reference voltage, generate a first control signal and transmit it to the internal circuit of the chip and the other comparator, and control the internal circuit of the chip and the other comparator.

An embodiment of the present invention further provides a chip, including the above-mentioned chip pin circuit.

An embodiment of the present invention further provides an apparatus, including the above chip pin circuit.

Compared with the prior art, the present invention has at least one of the following advantages:

The chip pin circuit provided by the embodiment of the present invention controls another comparator through one comparator. After the chip pin receives a signal, only part of the comparators can be turned on to realize the control and conversion of signal transmission. Compared with the prior art In the technical solution that the comparators need to be all turned on to detect the received signal and then convert it, the technical solution of the embodiment of the present invention can achieve the purpose of saving power consumption without affecting the chip pin circuit to receive and convert the signal.

Description of drawings

Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following drawings, wherein like reference numerals refer to like parts throughout, unless otherwise indicated. Components in the figures are not drawn to scale and may be drawn out of scale to facilitate an understanding of embodiments of the present disclosure.

1 is a schematic diagram of a chip pin circuit in the prior art;

2 is a schematic diagram of a chip pin circuit provided by an embodiment of the present invention;

3 is a schematic diagram of a comparator circuit in the chip pin circuit provided in FIG. 2;

4 is a schematic diagram of a chip pin circuit provided by another embodiment of the present invention;

FIG. 5 is a schematic diagram of a comparator circuit in the chip pin circuit provided in FIG. 4 .

Detailed ways

The following description is presented for the purpose of illustrating the general principles of the invention, and is not intended to limit the inventive concepts claimed herein. Furthermore, certain features described herein may be used in combination with other described features in each of the various possible combinations and permutations.

Unless specifically defined otherwise herein, all terms are to be given their broadest interpretation, including the meanings implied by this specification and the meanings understood by those skilled in the art and/or as defined in dictionaries, papers, and the like. In order to describe the technical content, structural features, achieved objects and effects of the present invention in detail, the following will be described in detail with reference to the embodiments and the accompanying drawings.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a chip pin circuit in the prior art, including a certain pin PWR_AB of the chip; a comparison reference voltage generating circuit, which includes a DC power supply Vdd and a parallel connection with the DC power supply Vdd. The connected series branch, the series branch is composed of six resistors R with equal resistance value connected in series, the six resistors R are respectively resistor R10, resistor R20, resistor R30, resistor R40, resistor R50 and resistor R60, DC power supply The positive terminal of Vdd is connected to the resistor R10, and the negative terminal of the DC power supply Vdd is connected to the resistor R60; in fact, it uses the resistor dividing method to generate the first reference voltage VREF1 and the second reference voltage VREF2; a pull-up resistor Rp, which One end is connected to the DC power supply Vdd, and the other end is connected to the pin PWR_AB; a first voltage comparator A1, the inverting end of which is connected between the resistor R10 and the resistor R20 of the series branch to obtain the first reference voltage, namely The first reference voltage is five-sixths of the DC power supply Vdd, and its non-inverting terminal is connected to the pin PWR_AB, which is used to compare the first reference voltage with the input voltage of the pin PWR_AB and output the first level signal AB to the internal circuitry of the chip. In the prior art, each voltage comparator independently compares according to the input voltage of the pin and then outputs a level signal to the internal circuit of the chip, so that the pin of one chip realizes the function of the original multiple pins of the chip, that is, the pin of the chip. Each time a signal is received, all comparators need to be turned on to compare the signal and then output a control signal to the internal circuit of the chip, which consumes a lot of power and takes time.

Embodiments of the present invention will be described below with reference to the accompanying drawings. As shown in FIG. 2, FIG. 2 is a schematic diagram of a chip pin circuit provided by an embodiment of the present invention, including: a chip pin VIN, a reference voltage circuit 1, a comparison circuit 3, and a comparison circuit control circuit 2, wherein the comparison circuit 3 Connect the chip pin VIN and receive the first signal from the chip pin VIN, the reference voltage circuit 1 generates a reference voltage and outputs it to the comparison circuit 3, the comparison circuit 3 compares the first signal and the reference voltage, generates a first control signal and transmits it to the chip The internal circuit module and the comparison circuit control circuit 2, the comparison circuit control circuit 2 receives the first control signal and generates a second control signal for controlling the comparison circuit. The reference voltage circuit 1 generates n comparison reference voltages VREF1 to VREFn by means of a resistance voltage division method, respectively for the n comparators. In this embodiment, the reference voltage circuit 1 includes a first DC power supply VSS, a ground terminal and a first DC A plurality of equal-resistance resistors R1~R4 between the power supply VSS and the ground terminal generate a first reference voltage VREF1, a second reference voltage VREF2, and a third reference voltage VREF3, that is, the first reference voltage VREF1 is a quarter of the DC power supply VSS. 3. The second reference voltage VREF2 is two-quarters of the DC power supply VSS, and the third reference voltage VREF3 is one-fourth of the DC power supply VSS. This embodiment is only an example, and the resistor divider can also be adjusted to multiple Series or parallel resistors create a reference voltage.

The comparison circuit 3 includes n (n>1) comparators, and the mth (1<m<n) comparator includes a first input terminal V+, a second input terminal V-, a control terminal VEN and a first output terminal COUTm, The first input terminal V+ is connected to the chip pin VIN to receive the first signal, the control terminal VEN is connected to the comparison circuit control circuit 2 to receive the second control signal, the second input terminal V- is connected to the reference voltage circuit 1 to receive the reference voltage, the first The output terminal COUTm outputs the first control signal to the chip internal circuit and the comparison circuit control circuit 2 to control the chip internal circuit and the m+1th comparator respectively. As shown in FIG. 2, this embodiment takes three comparators as an example. The first comparator C1 includes a first input terminal V+, a second input terminal V-, a control terminal VEN and a first output terminal COUT1, and the first input terminal V+ Connected to the chip pin VIN to receive the first signal, the control terminal VEN is connected to the external circuit to receive the third control signal EN, the second input terminal V- is connected to the reference voltage circuit 1 to receive the reference voltage, and the first output terminal COUT1 outputs a control signal To the internal circuit of the chip and the comparison circuit control circuit 2, to control the internal circuit of the chip and the second comparator respectively. The second comparator C2 includes a first input terminal V+, a second input terminal V-, a control terminal VEN and a first output terminal COUT2. The first input terminal V+ is connected to the chip pin VIN to receive the first signal, and the control terminal VEN is connected to To the comparison circuit control circuit 2 to receive the control signal, the second input terminal V- is connected to the reference voltage circuit 1 to receive the reference voltage, the first output terminal COUT2 outputs a control signal to the chip internal circuit module and the comparison circuit control circuit 2, respectively, control the chip Internal circuit and 3rd comparator. The last comparator, that is, the third comparator C3 includes a first input terminal V+, a second input terminal V-, a control terminal and a first output terminal COUT3. The first input terminal V+ is connected to the chip pin VIN to receive the first signal , the control terminal VEN is connected to the comparison circuit control circuit 2 to receive the control signal, the second input terminal V- is connected to the reference voltage circuit 1 to receive the reference voltage, the first output terminal COUT3 outputs the first control signal to the internal circuit module of the chip, and controls the internal circuit.

In this embodiment, the comparison circuit control circuit includes n-1 logic controllers, each of the logic controllers includes a third input terminal and a second output terminal, and the third input terminal of the logic controller is connected to a The comparator receives the first control signal, and the second output terminal outputs a second control signal to the other comparator to control the other comparator. Please continue to refer to FIG. 2 , the comparison circuit control circuit 2 includes two logic controllers. The input end of the first logic controller INV1 is connected to the first output end COUT1 of the first comparator to receive a control signal, and the output end outputs another A control signal is sent to the control terminal VEN of the second comparator, the input terminal of the second logic controller INV2 is connected to the first output terminal COUT2 of the second comparator to receive a control signal, and the output terminal outputs another control signal to The control terminal VEN of the third comparator.

In the example of FIG. 2 , the first reference voltage VREF1>the second reference voltage VREF2>the third reference voltage VREF3, and the reference voltages VREF1~VREF3 are respectively connected to the second input terminals V- of the comparators C1~C3, and the comparator C1 The first input terminal V+ of ~C3 is connected to the chip pin VIN to receive the first signal. When the first signal voltage is greater than the first reference voltage VREF1, the comparator C1 outputs a high level. Since the first reference voltage VREF1 > the second reference voltage VREF2 > the third reference voltage VREF3, the comparator C2 and the comparator C3 also output a high level level.

It can be seen from the above analysis that when the output terminal of the comparator C1 is at a high level, it can be determined that the output terminals of the comparator C2 and the comparator C3 are at a high level at this time. Therefore, in this working state, only the comparator C1 can be turned on, and the output of the comparator C1 can be used to control the power-on enable and logic output of the comparators C2 and C3, so that the comparators C2 and C3 are turned off, so as to realize the output result. The purpose of reducing power consumption without changing.

Please refer to FIG. 3 , which is a schematic diagram of a comparator circuit in the chip pin circuit provided in FIG. 2 . The comparator includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor Transistor M10, eleventh transistor M11, twelfth transistor M12, thirteenth transistor M13, fourteenth transistor M14, second DC power supply VDD, ground terminal GND and output terminal VOUT, wherein the drain of the first transistor M1 The reference voltage circuit is connected, the source of the first transistor M1 is connected to the drain of the second transistor M2, the gate of the first transistor M1 receives the control signal EN, the gate of the second transistor M2 is connected to its drain, and the second transistor M2 The source of the second transistor M2 is connected to the ground terminal GND, the gate of the second transistor M2 is also connected to the drain of the third transistor M3 and the gate of the fourth transistor M4, the gate of the third transistor M3 receives the control signal EN_N, and the third transistor M3 The source of the fourth transistor M4 is connected to the ground terminal GND, the source of the fourth transistor M4 is connected to the ground terminal GND, the drain of the fourth transistor M4 is connected to the source of the fifth transistor M5 and the source of the sixth transistor M6, and the drain of the fifth transistor M5 The gate and the gate of the sixth transistor M6 are both connected to the chip pins, the drain of the fifth transistor M5 is connected to the drain of the seventh transistor M7, the drain of the sixth transistor M6 is connected to the drain of the eighth transistor M8, The gate of the seventh transistor M7 is connected to the gate of the eighth transistor M8 and the drain of the ninth transistor M9, the gate of the seventh transistor M7 is also connected to its drain, and the source of the seventh transistor M7 is connected to the second DC power supply VDD, the source of the eighth transistor M8 is connected to the second DC power supply VDD, the gate of the ninth transistor M9 receives the control signal EN, the source of the ninth transistor M9 is connected to the second DC power supply VDD, and the gate of the tenth transistor M10 receives the control signal EN Control signal EN, the source of the tenth transistor M10 is connected to the second DC power supply VDD, the drain of the tenth transistor M10 is connected to the gate of the eleventh transistor M11, the gate of the twelfth transistor M12, and the drain of the sixth transistor M6 and the drain of the eighth transistor M8, the source of the eleventh transistor M11 is connected to the second DC power supply VDD, the drain of the eleventh transistor M11 is connected to the drain of the twelfth transistor M12 and the drain of the thirteenth transistor M13 The gate is connected to the gate of the fourteenth transistor M14, the source of the twelfth transistor M12 is connected to the ground terminal GND, the source of the thirteenth transistor M13 is connected to the second DC power supply VDD, and the drain of the thirteenth transistor M13 is connected to the ground terminal GND. The drain of the fourteenth transistor M14 is connected to the output terminal COUT, and the source of the fourteenth transistor M14 is connected to the ground terminal GND. The control signal EN and the control signal EN_N are mutually inverse signals, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the twelfth transistor M12 and the fourteenth transistor M14 are NMOS (NMOS: N-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) transistors, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the tenth transistor The first transistor M11 and the thirteenth transistor M13 are PMOS (P-Metal-Oxide-Semiconductor, P-type metal-oxide-semiconductor) transistors.

When the control signal EN is connected to a high level, the comparator works normally; when the control signal EN is connected to a low level, the fourth transistor M4 and the eighth transistor M8 are respectively controlled by the control signal EN signal and the control signal EN_N to turn off when the power is off. , the fifth transistor M5 and the sixth transistor M6 of the comparator are powered off to stop working, and the tenth transistor M10 is turned on when the control signal EN is at a low level, thereby connecting the V1p point to a high level VDD, and V1p is passed through by the eleventh transistor. The two-stage inverter composed of M11 ~ the fourteenth transistor M14 makes the output terminal COUT output a high level when the power is off. The two-stage inverter composed of the eleventh transistor M11 ~ the fourteenth transistor M14 can shape the electric wave. , reduce interference and ensure correct logic.

Figure 3 According to the analysis of Figure 2, when the first signal voltage > the first reference voltage VREF1, the output terminal COUT1 of the comparator C1 is at a high level, and the output terminal COUT1 transmits the output signal to the internal circuit module of the chip, and sends it to the comparator at the same time. The circuit control circuit 2 and the comparison circuit control circuit 2 are two sets of inverters. Since the output terminal COUT1 outputs a high level, it is a low level after passing through the inverter, and the low level is input to the control terminal of the comparator C2. After VEN, the comparator C2 is turned off, and at the same time, the output terminal COUT2 of the comparator C2 also outputs a high level; in the same way, the high level output by the output terminal COUT2 is connected to the control terminal VEN of the comparator C3 through the comparison circuit control circuit 2 to make the comparison The device C3 is turned off, and the output terminal COUT3 outputs a high level at the same time.

When the first reference voltage VREF1 > the first signal voltage > the second reference voltage VREF2 > the third reference voltage VREF3, it can be seen from the analysis in FIG. 2 that the comparator C1 works, the output terminal COUT1 outputs a low level, and the comparator C2 The control terminal VEN of the output terminal COUT1 is connected to the high level of the inverted output of the output terminal, and the comparator C2 works normally. Since the first signal voltage > the second reference voltage VREF2, the output terminal COUT2 outputs a high level, and the control terminal VEN of the comparator C3 is connected to the output Terminal COUT2 inverts the output low level, the comparator C3 is powered off, and the output terminal COUT3 outputs a high level.

When the first reference voltage VREF1 > the second reference voltage VREF2 > the first signal voltage > the third reference voltage VREF3, it can also be seen from the analysis in FIG. 2 that at this time the comparator C1 works and outputs a low level, and the comparator C2 works normally. The second reference voltage VREF2>the first signal voltage, the output terminal COUT2 outputs a low level, the control terminal VEN of the comparator C3 is connected to the high level output by the inverting output of the output terminal COUT2, the comparator C3 works normally, because the first signal voltage> the first signal voltage The three reference voltages VREF3 are compared, and the output terminal COUT3 outputs a high level.

When the first reference voltage VREF1 > the second reference voltage VREF2 > the third reference voltage VREF3 > the first signal voltage, it can also be seen from the analysis in FIG. 2 that at this time the comparator C1 works and outputs a low level, the comparator C2 works normally and outputs The terminal COUT2 outputs a low level, the control terminal VEN of the comparator C3 is connected to the high level of the inverted output of the output terminal COUT2, and the comparator C3 works normally. Since the third reference voltage VREF3> the first signal voltage, through comparison, the output terminal COUT3 output low level.

In addition, when the system needs to close the interface circuit, by connecting the control terminal VEN of the comparator C1 to a low level, the comparator C1 can be powered off and output a high level; the control terminal VEN of the comparator C2 is connected to the output terminal COUT1 to invert the phase After the output of the low level, the comparator C2 is powered off and outputs a high level; the control terminal VEN of the comparator C3 is connected to the low level output after the inversion of the output terminal COUT2, the comparator C3 is powered off and outputs a high level, thus The purpose of powering off the comparators of the entire interface circuit is realized, and the purpose of saving power consumption is achieved without affecting the function of the interface circuit and the output result.

Please refer to FIG. 4. FIG. 4 is a schematic diagram of a chip pin circuit provided by another embodiment of the present invention, including: a chip pin VIN, a reference voltage circuit 1, a comparison circuit 3, and a comparison circuit control circuit 2, wherein the comparison circuit 3 Connect the chip pin VIN and receive the first signal from the chip pin VIN, the reference voltage circuit 1 generates a reference voltage and outputs it to the comparison circuit 3, the comparison circuit 3 compares the first signal and the reference voltage, generates a first control signal and transmits it to the chip The internal circuit module and the comparison circuit control circuit 2, the comparison circuit control circuit 2 receives the first control signal and generates a second control signal for controlling the comparison circuit. The reference voltage circuit 1 generates n comparison reference voltages VREF1 to VREFn by means of the resistance voltage division method to be respectively supplied to the n comparators. A plurality of equal-resistance resistors R1~R4 generate a first reference voltage VREF1, a second reference voltage VREF2, and a third reference voltage VREF3, that is, the first reference voltage VREF1 is a quarter of the DC power supply VSS, and the second reference voltage VREF2 It is two-quarters of the DC power supply VSS, and the third reference voltage VREF3 is three-quarters of the DC power supply VSS. This embodiment is only an example, and the resistor divider can also be adjusted to multiple series or parallel resistors as needed to generate a reference Voltage.

For the implementation of the comparison circuit 3 in this embodiment, please refer to the comparison circuit of the previous embodiment. The comparison circuit control circuit 2 in this embodiment does not perform inversion processing on the first control signal, that is, the second control signal output by the comparison circuit control circuit 2 is in phase with the input first control signal, and the embodiment in FIG. 4 is a direct connection Of course, one or two stages of inverters can be connected between the output terminals and the control terminals of two adjacent comparators to shape the signal, reduce interference, and ensure correct logic.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a comparator circuit in the chip pin circuit provided in FIG. 4. The comparator in this embodiment includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor. M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, eighth transistor M8, ninth transistor M9, tenth transistor M10, eleventh transistor M11, twelfth transistor M12, thirteenth transistor M13, The fourteenth transistor M14, the second DC power supply VDD, the ground terminal GND and the output terminal VOUT, wherein the drain of the first transistor M1 is connected to the reference voltage circuit, the source of the first transistor M1 is connected to the drain of the second transistor M2, The gate of the first transistor M1 receives the control signal EN, the gate of the second transistor M2 is connected to its drain, the source of the second transistor M2 is connected to the ground terminal GND, and the gate of the second transistor M2 is also connected to the third transistor M3 The drain of the fourth transistor M4 is connected to the gate of the fourth transistor M4, the gate of the third transistor M3 receives the control signal EN_N, the source of the third transistor M3 is connected to the ground terminal GND, the source of the fourth transistor M4 is connected to the ground terminal GND, and the third transistor M3 is connected to the ground terminal GND. The drain of the four transistors M4 is connected to the source of the fifth transistor M5 and the source of the sixth transistor M6, the gate of the fifth transistor M5 and the gate of the sixth transistor M6 are both connected to the chip pins, and the fifth transistor M5 The drain of the seventh transistor M7 is connected to the drain of the seventh transistor M7, the drain of the sixth transistor M6 is connected to the drain of the eighth transistor M8, the gate of the seventh transistor M7 is connected to the gate of the eighth transistor M8, and the gate of the ninth transistor M9 The drain is connected to the drain, the gate of the seventh transistor M7 is also connected to its drain, the source of the seventh transistor M7 is connected to the second DC power supply VDD, the source of the eighth transistor M8 is connected to the second DC power supply VDD, and the ninth transistor M9 The gate of the ninth transistor M9 receives the control signal EN, the source of the ninth transistor M9 is connected to the second DC power supply VDD, the gate of the tenth transistor M10 receives the control signal EN_N, the source of the tenth transistor M10 is connected to the ground terminal GND, and the The drain is connected to the gate of the eleventh transistor M11, the gate of the twelfth transistor M12, the drain of the sixth transistor M6, and the drain of the eighth transistor M8, and the source of the eleventh transistor M11 is connected to the second DC Power supply VDD, the drain of the eleventh transistor M11 is connected to the drain of the twelfth transistor M12, the gate of the thirteenth transistor M13, the gate of the fourteenth transistor M14, and the source of the twelfth transistor M12 is connected to ground Terminal GND, the source of the thirteenth transistor M13 is connected to the second DC power supply VDD, the drain of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14 and the output terminal COUT, and the source of the fourteenth transistor M14 is connected to Ground terminal GND. The control signal EN and the control signal EN_N are mutually inverse signals, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the tenth transistor M10, The twelfth transistor M12 and the fourteenth transistor M14 are NMOS transistors, and the seventh transistor M7 , the eighth transistor M8 , the ninth transistor M9 , the eleventh transistor M11 , and the thirteenth transistor M13 are PMOS transistors.

When the control signal EN is connected to a high level, the comparator works normally; when the control signal EN is connected to a low level, the fourth transistor M4 and the eighth transistor M8 are respectively controlled by the control signal EN signal and the control signal EN_N to turn off when the power is off. , the fifth transistor M5 and the sixth transistor M6 of the comparator are powered off and stop working, and the tenth transistor M10 is turned on when the control signal EN_N is at a low level, thereby connecting the V1p point to the low level GND, and V1p is passed through by the eleventh The two-stage inverter composed of the transistor M11 to the fourteenth transistor M14 makes the output terminal COUT output a low level when the power is turned off.

Fig. 5 Combining with Fig. 4, it can be seen that when the first signal voltage < the first reference voltage VREF1, the output terminal COUT1 of the comparator C1 is at a low level, and the output terminal COUT1 transmits this output signal to the internal circuit module of the chip, and at the same time to the comparator Circuit control circuit 2, since the output terminal COUT1 outputs a low level, after the comparison circuit control circuit 2 is still low level, after this low level is input to the control terminal VEN of the comparator C2, the comparator C2 is turned off, and the comparison The output terminal COUT2 of the comparator C2 also outputs a low level; in the same way, the low level output by the output terminal COUT2 is connected to the control terminal VEN of the comparator C3 through the comparison circuit control circuit 2, so that the comparator C3 is turned off, and the output terminal COUT3 outputs a low level. level.

When the first reference voltage VREF1 < the first signal voltage < the second reference voltage VREF2 < the third reference voltage VREF3, it can also be seen from the analysis in FIG. 4 that the comparator C1 works, the output terminal COUT1 outputs a high level, and the comparator C2 The control terminal VEN is connected to the high level output by the output terminal COUT1, and the comparator C2 works normally. Since the first signal voltage < the second reference voltage VREF2, the output terminal COUT2 outputs a low level, and the control terminal VEN of the comparator C3 is connected to the output terminal COUT2. The output low level, the comparator C3 is powered off, and the output terminal COUT3 outputs a low level.

When the first reference voltage VREF1 < the second reference voltage VREF2 < the first signal voltage < the third reference voltage VREF3, it can also be seen from the analysis in FIG. 4 that the comparator C1 works and outputs a high level at this time, and the comparator C2 works normally. The second reference voltage VREF2 < the first signal voltage, the output terminal COUT2 outputs a high level, the control terminal VEN of the comparator C3 is connected to the high level output by the output terminal COUT2, and the comparator C3 works normally, because the first signal voltage < The third reference voltage The voltage VREF3, through comparison, the output terminal COUT3 outputs a low level.

When the first reference voltage VREF1 < the second reference voltage VREF2 < the third reference voltage VREF3 < the first signal voltage, it can also be seen from the analysis in FIG. 4 that at this time the comparator C1 works and outputs a high level, the comparator C2 works normally and outputs The terminal COUT2 outputs a high level, the control terminal VEN of the comparator C3 is connected to the high level output by the output terminal COUT2, and the comparator C3 works normally. Because the third reference voltage VREF3 < the first signal voltage, through comparison, the output terminal COUT3 outputs a high level level.

In addition, when the system needs to close the interface circuit, by connecting the control terminal VEN of the comparator C1 to a low level, the comparator C1 can be powered off and output a low level; the control terminal VEN of the comparator C2 is connected to the output terminal COUT1. Low level, the comparator C2 is powered off and outputs a low level; the control terminal VEN of the comparator C3 is connected to the output terminal COUT2 and outputs a low level, the comparator C3 is powered off and outputs a low level, thus realizing the entire interface circuit. The purpose of power-off and shut-down of all the comparators is realized, and the purpose of saving power consumption is achieved without affecting the function of the interface circuit and the output result.

An embodiment of the present invention further provides a chip, including the chip pin circuit provided by any of the above embodiments.

An embodiment of the present invention further provides an apparatus including the chip pin circuit provided by any of the above embodiments.

Unless the context clearly requires it, throughout this specification and the claims the words "including", "comprising" and the like are to be construed in an inclusive sense, rather than an exclusive or exhaustive sense; that is, "including" , but not limited to". The word "coupled," as generally used herein, refers to two or more elements that may be directly connected or connected through one or more intervening elements. Additionally, the words "herein," "above," "below," etc., when used in this application, shall refer to this application as a whole and not to any particular portions of this application. When the context allows, words in the singular or plural used in the above detailed description may also include the plural or singular, respectively. The term "or" refers to a list of two or more items, and this term encompasses all of the following interpretations of the term: any item in the list, all items in the list, and any combination of items in the list.

The teachings of the invention provided herein may be applied to other systems, not necessarily the systems described above. Elements and acts of the various embodiments described above may be combined to provide still further embodiments.

While some embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in various other forms; furthermore, various omissions, substitutions and changes in the forms of the methods and systems described herein may be made without departing from the spirit of the inventions. The appended claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims (9)

1. A chip pin circuit, comprising: a chip pin, a reference voltage circuit, a comparison circuit, wherein the comparison circuit comprises n comparators, n >1, each comparator is connected with the chip pin and receives a first signal from the chip pin, the reference voltage circuit generates a plurality of reference voltages and outputs the reference voltages to the corresponding comparators respectively, one comparator compares the first signal with the reference voltages and generates a first control signal and transmits the first control signal to a chip internal circuit and the other comparator to control the chip internal circuit and the other comparator, wherein the m-th comparator comprises a first input end, a second input end, a control end and a first output end, 1< m < n, the first input end is connected with the chip pin to receive the first signal, the control end receives the first control signal, the second input end is connected with the reference voltage circuit to receive the reference voltages, the first output end outputs a control signal to the chip internal circuit and the (m + 1) th comparator, and the chip internal circuit and the (m + 1) th comparator are respectively controlled by the first output end; wherein the comparator includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a second dc power supply, and a ground terminal, wherein a second pole of the first transistor is connected to the reference voltage circuit, a first pole of the first transistor is connected to a second pole of the second transistor, a gate of the first transistor receives a control signal, a gate of the second transistor is connected to the second pole thereof, a first pole of the second transistor is connected to the ground terminal, a gate of the second transistor is further connected to a second pole of the third transistor and a gate of the fourth transistor, a gate of the third transistor receives a control signal, a first pole of the third transistor is connected to the ground terminal, and a first pole of the fourth transistor is connected to the ground terminal, a second pole of the fourth transistor is connected to a first pole of the fifth transistor and a first pole of the sixth transistor, the grid electrode of the fifth transistor and the grid electrode of the sixth transistor are both connected with the chip pin, a second pole of the fifth transistor is connected to a second pole of the seventh transistor, a second pole of the sixth transistor is connected to a second pole of the eighth transistor, a gate of the seventh transistor is connected to a gate of the eighth transistor and to a second pole of the ninth transistor, the grid electrode of the seventh transistor is also connected with the second pole thereof, the first pole of the seventh transistor is connected with the second direct current power supply, a first electrode of the eighth transistor is connected to the second dc power supply, a gate of the ninth transistor receives a control signal, and a first electrode of the ninth transistor is connected to the second dc power supply.

2. The chip pin electronics of claim 1, wherein: the reference voltage circuit comprises a first direct current power supply, a grounding end and a plurality of resistors connected in series between the first direct current power supply and the grounding end.

3. The chip pin electronics of claim 1, wherein: the 1 st comparator comprises a first input end, a second input end, a control end and a first output end, wherein the first input end is connected to the chip pin to receive the first signal, the control end is connected to an external circuit to receive a third control signal, the second input end is connected to the reference voltage circuit to receive the reference voltage, and the first output end outputs the first control signal to the chip internal circuit and the 2 nd comparator to respectively control the chip internal circuit and the 2 nd comparator; the nth comparator comprises a first input end, a second input end, a control end and a first output end, wherein the first input end is connected to the chip pin to receive the first signal, the control end receives the control signal output by the nth-1 comparator, the second input end is connected to the reference voltage circuit to receive the reference voltage, and the first output end outputs the control signal to the chip internal circuit to control the chip internal circuit.

4. The chip pin electronics of claim 1, wherein: the comparator further includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, wherein a gate of the tenth transistor receives a control signal, a first pole of the tenth transistor is connected to the second dc power supply, a second pole of the tenth transistor is connected to the gate of the eleventh transistor, the gate of the twelfth transistor, the second pole of the sixth transistor, and the second pole of the eighth transistor, a first pole of the eleventh transistor is connected to the second dc power supply, a second pole of the eleventh transistor is connected to the second pole of the twelfth transistor, the gate of the thirteenth transistor, and the gate of the fourteenth transistor, a first pole of the twelfth transistor is connected to a ground terminal, and a first pole of the thirteenth transistor is connected to the second dc power supply, and a second pole of the thirteenth transistor is connected with a second pole and an output end of the fourteenth transistor, and a first pole of the fourteenth transistor is connected with a ground terminal.

5. The chip pin electronics of claim 4, wherein: the comparator is characterized by further comprising a comparison circuit control circuit, wherein the comparison circuit control circuit comprises a plurality of logic controllers, each logic controller comprises a third input end and a second output end, the third input end of each logic controller is connected with one comparator to receive the first control signal, and the second output end outputs the second control signal to the other comparator to control the other comparator.

6. The chip pin electronics of claim 5, wherein: the logic controller includes an inverter.

7. The chip pin electronics of claim 1, wherein: the comparator further includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, wherein a gate of the tenth transistor receives a control signal, a first pole of the tenth transistor is connected to ground, a second pole of the tenth transistor is connected to the gate of the eleventh transistor, the gate of the twelfth transistor, the second pole of the sixth transistor, and the second pole of the eighth transistor, a first pole of the eleventh transistor is connected to the second dc power supply, a second pole of the eleventh transistor is connected to the second pole of the twelfth transistor, the gate of the thirteenth transistor, and the gate of the fourteenth transistor, a first pole of the twelfth transistor is connected to ground, and a first pole of the thirteenth transistor is connected to the second dc power supply, and the second pole of the thirteenth transistor is connected with the second pole and the output end of the fourteenth transistor, and the first pole of the fourteenth transistor is connected with the ground terminal.

8. A chip, characterized by: comprising the chip pin electronics of claim 1.

9. An apparatus, characterized by: comprising the chip pin electronics of claim 1.

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