CN113162606A - Multi-priority control circuit - Google Patents
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
The invention relates to a multi-priority control circuit mainly used in an automatic control or automatic detection system, aiming at providing a simple and reliable multi-priority control circuit for controlling the on-off of a port, and the invention is realized by the following technical scheme: the multi-stage cascade control circuit is characterized in that each stage of control circuit comprises a two-input AND gate connected with the next stage of control circuit and D triggers connected with two ends of the AND gate, the D triggers are connected with an alternative data selector at the control end in parallel, the first stage of control circuit controls the connection and disconnection of the control end, the multi-stage cascade control circuit controls the connection and disconnection of a preceding stage of control circuit, and the nth stage of control circuit controls the connection and disconnection of the (n-1) th stage of control circuit, so that priority control and connection and disconnection and shielding of the control end are realized. The invention combines multi-stage control circuits, utilizes the association control among stages, and can simply and effectively realize the multi-stage priority control.
Description
Technical Field
The invention relates to a circuit which is mainly used for controlling a plurality of priorities in an automatic control or automatic detection system.
Background
Priority control (priority control) refers to a control method for giving priority to traffic. The voltage first mode should be used in situations where voltage overshoot must be minimal, such as biasing to the core of a low voltage processor or FPGA. The current-first mode should be used if it is desired to minimize current overshoot, or if the device under test is a low impedance device, such as when charging a battery or driving a system containing a large capacitor. Although the priority mode was once implemented by analog design, modern power supplies are highly digitally controlled power supplies that employ Digital Signal Processing (DSP), digital feedback loops, FPGA, and other technologies. The characteristics of the power supply, including the priority mode, can be implemented by digital techniques, so that the schematic block diagram of the power supply is indistinguishable whether it is voltage-priority or current-priority. In other words, in either mode, the power supply does not switch different circuits or transmit signals over different paths. The digital control system commands the power supply to take different actions to achieve either voltage priority or current priority. If it is a low impedance load, RLOAD < (Voltage set/Current set), the voltage will start to operate in Constant Voltage (CV) mode, but low load impedance means that the voltage cannot reach the set value. Instead, the source current will quickly reach the current setting, switching to Constant Current (CC), and the voltage will collapse. In the transient transition from the constant voltage CV mode to the constant current CC mode, the constant current CC loop takes priority, which requires some time to adjust the current to the current setting. This can lead to transient current control instability, which can further produce current overshoot. In short, in the voltage first mode, the voltage exhibits good characteristics with little overshoot. However, during the cross-over transition from the constant voltage CV mode to the constant current CC mode, there is a possibility of current overshoot, since no priority is given to current regulation at this time.
In the control of the interrupt priority of the single chip microcomputer, a hardware priority queuing circuit of the interrupt system of the single chip microcomputer specifies the priority sequence for various interrupt sources. This structure of the interrupt priority has the following features. (1) The hardware queuing circuit does not guarantee the priority of each interrupt source. This is because after an interrupt request from an interrupt source is responded by the CPU, the corresponding bit in INT-PENDING is cleared, which means that the interrupt source being serviced cannot participate in the priority comparison after the new interrupt request, and if no measures are taken, the result is that the interrupt service at a high level is interrupted by the interrupt application at a low level. For example, the external interrupt (with the highest priority) and the timer overflow interrupt (with the lowest priority) are generated simultaneously, when the system opens the interrupt, the application of the external interrupt will be responded by the CPU first, after entering the interrupt service routine, the interrupt application with the timer overflow will be compared by the priority coding circuit, because the bit corresponding to the external interrupt in INT-PRNDING is cleared, only the timer overflow interrupt participating in the priority comparison is interrupted, the service process of the external interrupt is interrupted, the CPU turns to the interrupt service routine with the timer overflow, and the external interrupt will be returned to continue the service until the service is completed. It is easy to see that in the case of multiple interrupt sources issuing an interrupt request, the interrupt source with the lowest level will actually get the full service first, and the interrupt service with the highest level will wait until it can be completed finally. This also means that the interrupt source of the highest level becomes substantially the lowest level. Although a combination of hardware and software may be used to implement a particular priority ranking. As described above, the hardware queuing circuit cannot guarantee that interrupt nesting is implemented in the order of high and low of the designated priority, but certain software measures can be taken to implement the priority queuing order envisioned by the designer.
Generally, a microprocessor reads input information from a peripheral device (e.g., a keyboard) by two methods, namely Polling (Polling) and Interrupt (Interrupt). The polling method is that the CPU inquires whether the I/O of each peripheral device needs to be serviced in sequence according to a certain established rule, in this method, the CPU takes some time to perform inquiry service, and when the I/O devices are increased, the inquiry service time is also increased relatively, so that a lot of CPU time is wasted, and the overall operation efficiency is reduced.
In multi-machine communication, in the existing electronic circuit design, a relatively complex priority algorithm is often adopted for calculating a quantitative result of whether a control loop needs to be maintained or not for the design based on priority, so that maintenance management of the control loop is realized, but corresponding measures need to be taken on software for realizing a specific interrupt priority sequence, and in many simple practical applications, one main problem of the priority algorithm is infinite blocking or starvation. A process that is ready to run, but waiting on the CPU may be considered blocked. The priority algorithm may let a certain low priority process wait indefinitely for the CPU. For an overloaded computer system, a steady flow of higher priority processes may prevent lower priority processes from getting CPU. Generally, two situations occur. Either the process will eventually run (when the system is eventually light-loaded) or the system eventually crashes and loses all outstanding low priority processes. When the algorithm is used for job scheduling, the system selects a plurality of jobs with the highest priority from the back job queue, and the system can load the jobs meeting the resource requirements into the memory for operation; when the algorithm is used for process scheduling, the handler will be assigned to the process with the highest priority in the ready-to-run queue. Two modes of scheduling algorithm, non-preemptive priority algorithm and preemptive priority scheduling algorithm: under the scheduling mode of a non-preemptive priority algorithm, once a system allocates a processor to a process with the highest priority in a ready queue, the process can be executed all the time until the process is finished; or when the process has to abandon a handler by waiting for an event to occur, the system can assign the handler to another ready queue with a high priority, which is commonly used in batch processing systems. Preemptive priority scheduling algorithm: in this scheduling mode, the process scheduler assigns the handler to the ready process with the highest priority at that time for execution. Upon the occurrence of another, higher priority ready process, the process scheduler stops the executing process and assigns the handler to the newly occurring, highest priority ready process. While one process is executing, the system may deprive the CPU of other processes based on some policy. The principle of deprivation is: a priority principle, a short-run priority principle, and a time-slice principle. The scheduling mode is mostly used in a time-sharing system and a real-time system, is usually used in the real-time system with strict real-time requirements and the time-sharing system with high real-time performance requirements. The disadvantages are as follows: the method is not flexible, and the condition that jobs with low priority are not scheduled for a long time and wait is likely to occur.
Disclosure of Invention
In order to overcome the defects in electronic design, the invention provides the multi-priority control circuit which is simple and reliable in circuit, low in occupied resource, high in control precision, capable of reducing resource consumption, easy in engineering application and easy in multi-priority control.
The technical scheme adopted by the invention for solving the technical problems is as follows: a multi-priority control circuit comprises a first-stage control circuit and a multi-stage cascade control circuit, and is characterized in that each stage of control circuit comprises a two-input AND gate connected with a next-stage control circuit and a D trigger connected with two ends of the AND gate, the D trigger is connected with an alternative data selector at a control end in parallel, the multi-stage cascade control circuit controls the on-off of a preceding-stage control circuit, an nth-stage control circuit controls the on-off of an n-1 th-stage control circuit, and a watchdog signal is automatically/manually used as an ENA enabling control signal to realize priority control and the on-off and shielding of the control end.
Compared with the prior art, the invention has the following beneficial effects:
the circuit is simple, and the occupied resource is low. The invention adopts a multi-priority control circuit consisting of a first-stage control circuit and a multi-stage cascade control circuit, combines the multi-stage control circuit, and can simply and effectively realize multi-stage priority control by utilizing the associated control among stages. The circuit is simple, the occupied resource is low, and the realization is easy. Each stage of control circuit only adopts one alternative data selector, one two-input AND gate and one D trigger to realize the control function, so that the resource consumption can be reduced, and the method is simple to use and high in reliability. The process concurrency and the response time characteristic are improved, and therefore the resource utilization rate is improved.
High control precision and easy engineering application. The invention adopts the on-off of the control end of the first-stage control circuit, the multi-stage cascade control circuit controls the on-off of the preceding-stage control circuit, and the on-off control of the nth-1 stage control circuit is realized through the nth-stage control circuit, so that the multi-priority control is realized, the hardware does not need to be changed, and the control precision is high. On the premise of not changing the external hardware pin of the debugging interface, the software method can realize priority control and on-off and shielding of the control end. Thus facilitating engineering applications.
The method of the invention can be realized not only in an ASIC chip of an application specific integrated circuit, but also in an FPGA chip of a programmable gate array chip, and has the advantages of simple structure, less occupied hardware resources and easy engineering application. The method can be used for priority discrimination control of systems such as automatic control and automatic monitoring. The method can also be used for hot backup simulation control of a computer control system.
Drawings
FIG. 1 is a schematic diagram of the multi-priority control circuit of the present invention.
Detailed Description
See fig. 1. In the preferred embodiment described below, a multi-priority control circuit includes a first-stage control circuit and a multi-stage cascade control circuit, each stage of control circuit includes a two-input and gate connected to the next-stage control circuit and a D flip-flop connected to both ends of the and gate, the D flip-flop is connected in parallel with an alternative data selector at the control end, the first-stage control circuit controls the on/off of the control end, the multi-stage cascade control circuit controls the on/off of the preceding-stage control circuit, and the nth-stage control circuit controls the on/off of the (n-1) th-stage control circuit, so as to implement priority control and on/off and shielding of the control end.
The two-out data selector of each stage of control circuit defaults to output as high level through a control end debugging interface, the selection signal is sent to the input end of a D trigger which is connected in parallel, a logic unit of the D trigger is overturned at the front edge of a clock pulse CP, two functions of a 1 end and a 0 end are directly set, the output control signal is sent to the input end of a two-input AND gate, and the control signal from the system and the selection signal of the two-out data selector are input to the output of the two-out data selector of the next stage of control circuit through the other input end of the two-input AND gate.
The nth stage control circuit generates a switching signal by using the input control signal and the selection signal, and the switching signal is directly acted on the nth-1 stage control circuit to control the switching output of the nth-1 stage circuit.
When the first-stage control circuit is in an initial default state, sel _1 is at a low level, the output is 1'b1 after passing through a two-input NAND gate through 1' b1 output of an alternative selector, the result of 1'b1 is latched through a D flip-flop, and the value of a control end s _13 is 1' b 1;
if the value of the output s _13 of the control terminal needs to be changed, sel _1 of the first-stage circuit is configured to be 1'b1, data _1 of the first-stage circuit is configured to be 1' b0, the output s11 of the alternative selector is 1'b0, and the value of the output s _13 of the control terminal is 1' b 0;
the nth stage control circuit: in an initial default state, an input signal sel _ n of the nth-stage control circuit is in a low level, the output s _ n1 of the alternative selector is 1' b1, the output value s _ n2 of the s _ n1 and the output s _ n3 of the D flip-flop after logical AND operation is 1' b1, the value of the output s _ n2 of the two-input AND gate is latched by the D flip-flop, and the value of the output signal s _ n3 of the D flip-flop is 1' b 1;
if the output value of the s _ n3 needs to be changed, the input signal sel _ n of the nth stage control circuit is configured to be high level, the input signal data _ n is configured to be 1'b0, after passing through the alternative selector, the output signal s _ n1 is changed from 1' b1 to 1'b0, and the output value of s _ n3 is 1' b 0; when the nth stage control circuit is in a default state, the control port is opened; when the input signal sel _ n of the control port is at a high level and the input signal data _ n is configured as 1'b0, the input s _ n1 of the alternative selector is 1' b0, the output signal s _ n2 of the two-input AND gate is 1'b0, and the output s _ n3 of the nth-stage control circuit is 1' b 0; when the nth stage control circuit is not opened, the output of the (n-1) th stage circuit is always 1' b0, thereby realizing the hierarchical control function of the circuit.
While the foregoing is directed to the preferred embodiment for implementing a high density, general purpose signal processing device, it is to be understood that the invention is not limited to the form disclosed herein, but is not to be construed as limited to other embodiments, and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A multi-priority control circuit comprises a first-stage control circuit and a multi-stage cascade control circuit, and is characterized in that each stage of control circuit comprises a two-input AND gate connected with a next-stage control circuit and a D trigger connected with two ends of the AND gate, the D trigger is connected with an alternative data selector at a control end in parallel, the multi-stage cascade control circuit controls the on-off of a preceding-stage control circuit, an nth-stage control circuit controls the on-off of an n-1 th-stage control circuit, and a watchdog signal is automatically/manually used as an ENA enabling control signal to realize priority control and the on-off and shielding of the control end.
2. The multi-priority control circuit of claim 1, wherein: the two-out data selector of each stage of control circuit defaults to output as high level through a control end debugging interface, the selection signal is sent to the input end of a D trigger which is connected in parallel, a logic unit of the D trigger is overturned at the front edge of a clock pulse CP, two functions of a 1 end and a 0 end are directly set, the output control signal is sent to the input end of a two-input AND gate, and the control signal from the system and the selection signal of the two-out data selector are input to the output of the two-out data selector of the next stage of control circuit through the other input end of the two-input AND gate.
3. The multi-priority control circuit of claim 1, wherein: the nth stage control circuit generates a switching signal by using the input control signal and the selection signal, and the switching signal is directly acted on the nth-1 stage control circuit to control the switching output of the nth-1 stage circuit.
4. The multi-priority control circuit of claim 3, wherein: when the first stage control circuit is in the initial default state, sel _1 is at low level, the output is 1'b1 after passing through the two-input NAND gate through the alternative selector output 1' b1, the result of 1'b1 is latched through the D flip-flop, and the value of the control end s _13 is 1' b 1.
5. The multi-priority control circuit of claim 4, wherein: if the value of the output s _13 of the control terminal needs to be changed, sel _1 of the first stage circuit is configured to be 1'b1, data _1 of the first stage circuit is configured to be 1' b0, the output s11 of the alternative selector is 1'b0, and the value of the output s _13 of the control terminal is 1' b 0.
6. The multi-priority control circuit of claim, wherein: the nth stage control circuit: in an initial default state, an input signal sel _ n of the nth stage control circuit is at a low level, an output s _ n1 of the alternative selector is 1' b1, an output value s _ n2 of the s _ n1 and an output s _ n3 of the D flip-flop after logical and operation is 1' b1, a value of an output s _ n2 of the two-input AND gate is latched by the D flip-flop, and a value of an output signal s _ n3 of the D flip-flop is 1' b 1.
7. The multi-priority control circuit of claim 6, wherein: if the output value of s _ n3 needs to be changed, the input signal sel _ n of the nth stage control circuit is configured to be high level, the input signal data _ n is configured to be 1'b0, after passing through the alternative selector, the output signal s _ n1 is changed from 1' b1 to 1'b0, and the output value of s _ n3 is 1' b 0.
8. The multi-priority control circuit of claim 1, wherein: when the nth stage control circuit is in a default state, the control port is opened; when the input signal sel _ n of the control port is at a high level and the input signal data _ n is configured as 1'b0, the input s _ n1 of the alternative selector is 1' b0, the output signal s _ n2 of the two-input AND gate is 1'b0, and the output s _ n3 of the nth-stage control circuit is 1' b 0; when the nth stage control circuit is not opened, the output of the (n-1) th stage circuit is always 1' b0, thereby realizing the hierarchical control function of the circuit.
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| CN202110338010.6A CN113162606B (en) | 2021-03-30 | 2021-03-30 | Multi-priority control circuit |
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|---|---|---|---|---|
| GB966706A (en) * | 1959-08-24 | 1964-08-12 | Post Office | Improvements in or relating to electrical circuit arrangements |
| US4001783A (en) * | 1975-03-26 | 1977-01-04 | Honeywell Information Systems, Inc. | Priority interrupt mechanism |
| US4028664A (en) * | 1975-03-26 | 1977-06-07 | Honeywell Information Systems, Inc. | Apparatus for dispatching data of the highest priority process having the highest priority channel to a processor |
| US4533994A (en) * | 1983-09-09 | 1985-08-06 | Avco Corporation | Priority circuit for a multiplexer terminal |
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-
2021
- 2021-03-30 CN CN202110338010.6A patent/CN113162606B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB966706A (en) * | 1959-08-24 | 1964-08-12 | Post Office | Improvements in or relating to electrical circuit arrangements |
| US4001783A (en) * | 1975-03-26 | 1977-01-04 | Honeywell Information Systems, Inc. | Priority interrupt mechanism |
| US4028664A (en) * | 1975-03-26 | 1977-06-07 | Honeywell Information Systems, Inc. | Apparatus for dispatching data of the highest priority process having the highest priority channel to a processor |
| US4533994A (en) * | 1983-09-09 | 1985-08-06 | Avco Corporation | Priority circuit for a multiplexer terminal |
| CN103049323A (en) * | 2012-12-31 | 2013-04-17 | 西安奇维科技股份有限公司 | Multi-interrupt balance management method implemented in FPGA (field programmable gate array) |
| CN106776423A (en) * | 2016-11-25 | 2017-05-31 | 天津大学 | Using the asynchronous arbitration tree circuit of priority automatic switchover arbitration unit |
| CN110083563A (en) * | 2019-04-01 | 2019-08-02 | 吉林大学 | A kind of arbitration circuit for realizing fair arbitration based on circular priority |
Non-Patent Citations (1)
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| 毛保磊等: "面向时序逻辑的门级信息流分析方法", 《空军工程大学学报(自然科学版)》 * |
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