CN113140606A - Display panel, display device and preparation method - Google Patents
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- CN113140606A CN113140606A CN202110418765.7A CN202110418765A CN113140606A CN 113140606 A CN113140606 A CN 113140606A CN 202110418765 A CN202110418765 A CN 202110418765A CN 113140606 A CN113140606 A CN 113140606A
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Abstract
本发明提供一种显示面板、显示装置及制备方法。该显示面板包括衬底基板和制作于衬底基板上的驱动单元、发光器件单元和驱动信号线，所述驱动信号线与所述驱动单元连接，通过所述驱动信号线上的驱动信号，所述驱动单元能够控制所述发光器件单元发光；所述驱动信号线包括扫描信号线和与所述扫描信号线垂直的垂直信号线；所述发光器件单元包括依次制作于所述驱动单元上的第一电极层、发光层和第二电极层；其中，所述垂直信号线与所述第一电极层同层制作。采用该显示面板，能够解决现有技术显示面板中RC Loading较大，导致驱动信号波形畸变严重的问题。
The present invention provides a display panel, a display device and a manufacturing method. The display panel includes a base substrate, a driving unit, a light-emitting device unit, and a driving signal line fabricated on the base substrate. The driving signal line is connected to the driving unit. Through the driving signal on the driving signal line, all the The driving unit can control the light-emitting device unit to emit light; the driving signal line includes a scanning signal line and a vertical signal line perpendicular to the scanning signal line; An electrode layer, a light-emitting layer and a second electrode layer; wherein, the vertical signal line and the first electrode layer are fabricated in the same layer. The use of the display panel can solve the problem of large RC Loading in the display panel of the prior art, resulting in serious waveform distortion of the driving signal.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a display device and a preparation method.
Background
At present, OLED products with medium size and high resolution are more and more favored by customers; however, since the OLED pixel circuit is complex and the lines overlap more, RC Loading on the Data Line and the Gate Line will be larger.
Due to the existence of the resistor and the capacitor on the signal wire, the waveform driven by the OLED display panel can be distorted, and the larger the RC is, the more serious the distortion is; generally, the larger the size of the display panel is, the higher the resolution is, the more serious the waveform distortion is, and if the driving frequency is higher, the problem that the driving signal cannot reach the expected value exists; therefore, reducing the RC value of the signal line is the most direct and effective means for solving the above problems, and reducing the RC Loading (i.e. the technical problem that the resistance-capacitance load is a medium-large size, high resolution, and high refresh frequency OLED product is needed to be solved urgently, and the technical problem that is difficult to break through in the design of the OLED product is also the technical problem.
Disclosure of Invention
The technical scheme of the invention aims to provide a display panel, a display device and a preparation method, which are used for solving the problem of serious waveform distortion of a driving signal caused by large RC Loading in the display panel in the prior art.
One embodiment of the invention provides a display panel, which comprises a substrate, and a driving unit, a light-emitting device unit and a driving signal line which are manufactured on the substrate, wherein the driving signal line is connected with the driving unit, and the driving unit can control the light-emitting device unit to emit light through a driving signal on the driving signal line;
the driving signal lines include scanning signal lines and vertical signal lines perpendicular to the scanning signal lines;
the light-emitting device unit comprises a first electrode layer, a light-emitting layer and a second electrode layer which are sequentially manufactured on the driving unit;
the vertical signal line and the first electrode layer are manufactured in the same layer.
Optionally, in the display panel, the vertical signal line and the first electrode layer are made of the same conductive material and are manufactured by the same patterning process.
Optionally, the display panel, wherein the conductive material includes a first ITO layer, a metal layer, and a second ITO layer stacked in this order.
Optionally, the display panel, wherein the vertical signal line includes at least one of a data line signal line, a VDD signal line, a VSS signal line, and a compensation signal line.
Optionally, the display panel, wherein the driving unit includes a buffer layer, an active layer, a gate insulating layer, a gate electrode layer, an interlayer insulating layer, a source/drain electrode layer, and a planarization layer, which are sequentially disposed on the substrate; wherein, the vertical signal line is made on the flat layer.
Optionally, in the display panel, the scan signal line and the gate layer are fabricated in the same layer.
Optionally, the display panel, wherein the vertical signal lines include VSS signal lines, and a cross-sectional area of the metal layer is smaller than cross-sectional areas of the first ITO layer and the second ITO layer through the VSS signal lines made of the conductive material;
the light emitting layer and the second electrode layer sequentially cover the VSS signal lines, and the second electrode layer is in contact connection with the metal layer.
An embodiment of the present invention further provides a display device, including the display panel described in any one of the above.
An embodiment of the present invention further provides a method for manufacturing a display panel, where the method includes:
providing a substrate base plate;
sequentially manufacturing a driving unit and a light emitting device unit on the substrate base plate;
when the grid layer of the driving unit is manufactured, a scanning signal line is manufactured through the same composition process with the grid layer; when the first electrode layer of the light-emitting device unit is manufactured, the vertical signal line and the first electrode layer are manufactured through the same composition process.
Optionally, the manufacturing method, wherein the vertical signal line is a VSS signal line, and in a process of manufacturing a light emitting device unit, the manufacturing of the light emitting device unit includes:
manufacturing a pixel defining layer on the substrate completing the manufacturing of the driving unit;
manufacturing a first electrode layer on the pixel limiting layer, and manufacturing the VSS signal line by the same composition process with the first electrode layer; the first electrode layer and the VSS signal line respectively comprise a first ITO layer, a metal layer and a second ITO layer which are sequentially stacked;
etching the VSS signal line to enable the VSS signal line to be located in an opening on the pixel limiting layer, wherein the cross-sectional area of the metal layer is smaller than that of the first ITO layer and that of the second ITO layer;
sequentially manufacturing a light emitting layer and a second electrode layer on the substrate for manufacturing the first electrode layer and the VSS signal line; and in the opening, the light-emitting layer is in contact connection with the first ITO, and the second electrode layer is in contact connection with the metal layer.
At least one of the above technical solutions of the specific embodiment of the present invention has the following beneficial effects:
according to the display panel, the signal lines perpendicular to the scanning signal lines and the first electrode layer on the driving unit are manufactured in the same layer, so that the spacing distance between the scanning signal lines and the signal lines perpendicular to the scanning signal lines is increased, the capacitance at the overlapped part between the scanning signal lines and the signal lines perpendicular to the scanning signal lines is reduced, the RC Loading on the scanning signal lines is reduced, and the RC on the signal lines perpendicular to the scanning signal lines is reduced, so that the problem that the driving signal waveform is seriously distorted due to the fact that the RC Loading in the display panel in the prior art is large is solved.
Drawings
FIG. 1 is a schematic diagram of a prior art display panel;
FIG. 2 is a schematic diagram of an input waveform of a driving signal;
fig. 3 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the invention;
FIG. 4 is an enlarged diagram of a VSS signal line portion of the circuit of FIG. 3;
fig. 5 is a schematic flow chart of a manufacturing method of a display panel according to an embodiment of the invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
In order to solve the problem of serious waveform distortion of a driving signal due to large RC Loading in a display panel in the prior art, the embodiment of the invention provides the display panel, wherein in the driving signal line on the display panel, a vertical signal line vertical to a scanning signal line and an electrode layer of a light-emitting device unit are manufactured in the same layer.
As shown in fig. 1, a schematic cross-sectional structure of a conventional display panel, taking a top emission display panel as an example, the display panel includes a substrate 100, and a driving unit 200 and a light emitting device unit 300 sequentially fabricated on the substrate 100.
The driving unit 200 includes a buffer layer 201, an active layer 2011, a gate insulating layer 202, a gate layer 203, an interlayer insulating layer 204, a source/drain layer 205, and a planarization layer 206 sequentially disposed on the substrate 100.
The light emitting device unit 300 includes a first electrode layer 301, a light emitting layer 302, and a second electrode layer 303 sequentially formed on the planarization layer 206, and the light emitting layer 302 is formed in a pixel defining layer 304.
In addition, the display panel is further provided with driving signal lines, which respectively include scanning signal lines (not shown) arranged along a first direction, VSS signal lines 2, VDD signal lines 3, data signal lines 4 and compensation signal lines (not shown) arranged along a second direction, wherein the first direction is perpendicular to the second direction.
Currently, in the conventional technology, the scan signal Line and the gate layer 203 of the driving unit 200 are fabricated in the same layer, and the VSS signal Line 2, the VDD signal Line 3, the data signal Line 4, and the compensation signal Line are fabricated in the same layer as the source/drain layer 205.
In the display panel, due to the existence of the resistor and the capacitor on each driving signal Line, the overlapping of the scanning signal Line and the lines among the VSS signal Line 2, the VDD signal Line 3, the data signal Line 4 and the compensation signal Line is large, and the RC Loading on the scanning signal Line and the data signal Line 4 is large, the waveform of the driving signal on each driving signal Line is distorted. Specifically, the larger the RC, the larger the distortion, as shown in fig. 2. Generally, the larger the display panel size, the higher the resolution, and the more severe the distortion. In the case where the driving frequency is high, there may be a problem that the driving signal does not reach a desired value. Referring to fig. 2, when the driving signal reaches the target value and can be kept stable for a period of time, the signal driving requirement can be satisfied, as shown in a waveform a after RC in fig. 2; when the size of the display panel is large or the resolution is high, that is, when the RC Loading is too large and the driving signal cannot reach the target value, or cannot be kept stable for a while, the driving signal is abnormal, that is, the driving fails, as shown in fig. 2 by waveforms b and c after RC; in addition, when the signal output frequency is high, i.e., the period of the driving waveform is shortened, abnormality of the driving signal may be caused, such as the waveform of fig. 2.
As described above, in any case of generating the waveform a or the waveform b, the driving of the driving signal is disabled due to the fact that the RC Loading on the driving signal line is too large, and the RC value on the driving signal line, that is, the resistance or the capacitance, is reduced, which is the most direct and effective means for solving the technical problem.
In a typical display panel, a scan signal Line and a gate layer 203 are fabricated in the same layer, a VSS signal Line 2, a VDD signal Line 3, a data signal Line 4 and a compensation signal Line are fabricated in the same layer as a source/drain layer 205, respectively, and only an interlayer insulating layer 204 is disposed between the source/drain layer 205 and the gate layer 203, and the thickness of the interlayer insulating layer is generally 300 nnm-1000 nm, i.e., the thickness of an intermediate medium between the data signal Line 4 and the scan signal Line is small, so that the capacitance between the scan signal Line and each signal Line perpendicular to each other is large.
In light of the foregoing problems, embodiments of the present invention provide a display panel, which includes a substrate, and a driving unit, a light emitting device unit, and a driving signal line that are formed on the substrate, wherein the driving signal line is connected to the driving unit, and the driving unit can control the light emitting device unit to emit light according to a driving signal on the driving signal line;
the driving signal lines include scanning signal lines and vertical signal lines perpendicular to the scanning signal lines;
the light-emitting device unit comprises a first electrode layer, a light-emitting layer and a second electrode layer which are sequentially manufactured on the driving unit;
the vertical signal line and the first electrode layer are manufactured in the same layer.
Compared with the prior art, the display panel has the advantages that the signal line perpendicular to the scanning signal line and the source/drain electrode layer of the driving unit are manufactured in the same layer, the signal line perpendicular to the scanning signal line and the first electrode layer on the driving unit are manufactured in the same layer, so that the spacing distance between the scanning signal line and the signal line perpendicular to the scanning signal line is increased, the capacitance of the overlapping part between the scanning signal line and the signal line perpendicular to the scanning signal line is reduced, the RC Loading on the scanning signal line is reduced, and the RC on the vertical line is reduced, so that the problem that the waveform distortion of the driving signal is serious due to the fact that the RC Loading in the display panel in the prior art is large is solved.
In the embodiment of the present invention, the vertical signal line perpendicular to the scanning signal line includes at least one of a data signal line, a VDD signal line, a VSS signal line, and a compensation signal line.
As shown in fig. 3, the display panel according to the embodiment of the present invention, taking a top emission display panel as an example, includes a substrate 100, and a driving unit 200 and a light emitting device unit 300 sequentially fabricated on the substrate 100.
The driving unit 200 includes a buffer layer 201, an active layer 2011, a gate insulating layer 202, a gate layer 203, an interlayer insulating layer 204, a source/drain layer 205, and a planarization layer 206 sequentially disposed on the substrate 100.
The light emitting device unit 300 includes a first electrode layer 301, a light emitting layer 302, and a second electrode layer 303 sequentially formed on the planarization layer 206, and the light emitting layer 302 is formed in a pixel defining layer 304.
Optionally, the first electrode layer 301 is an anode layer and the second electrode layer 303 is a cathode layer.
In this embodiment, taking the vertical signal lines including the VSS signal lines and the data signal lines as an example, as shown in fig. 3, in the embodiment of the invention, the VSS signal lines 2 and the data signal lines 4 are both formed on the planarization layer 206 and are formed in the same layer as the first electrode layer 301.
Further, the first electrode layer 301 is connected to the source/drain electrode layer 205 of the driving unit 200 through a via hole penetrating the planarization layer 206; the data signal line 4 is connected with the source/drain electrode layer 205 of the driving unit 200 through a via hole penetrating the planarization layer 206 to enable input of a control signal to the first electrode layer 301 and the data signal line 4 through the driving unit 200.
According to this embodiment, the VSS signal lines 2 and the data signal lines 4 are separated from the gate electrode layer 203 by the gate insulating layer 202 and the planarization layer 206 (the planarization layer has a large thickness, typically 2um or more), and the gate electrode layer 203 and the scanning signal lines are disposed on the same layer, so that the distance between the scanning signal lines and the vertical signal lines can be increased, and the capacitance at the overlapping portions between the scanning signal lines and the vertical signal lines can be reduced, as compared with the related art.
In the embodiment of the present invention, the vertical signal line perpendicular to the scanning signal line and formed on the same layer as the first electrode layer 301 and the first electrode layer 301 are made of the same conductive material and formed by the same patterning process.
Referring to fig. 3, in one embodiment, when the vertical signal lines include the VSS signal lines 2 and the data signal lines 4, the VSS signal lines 2 and the data signal lines 4 are made of the same conductive material and are formed by the same patterning process.
In the embodiment of the present invention, optionally, as shown in fig. 4, the conductive material includes a first ITO layer 401, a metal layer 402, and a second ITO layer 403, which are stacked in this order. With this embodiment, the materials of the first electrode layer 301, the VSS signal line 2 and the data signal line 4 are formed in a structure of the first ITO layer 401/the metal layer 402/the second ITO layer 403, alternatively, the first electrode layer 301 is an anode, and the metal layer 402 may be any one of an Al layer, an AlNb layer and a Cu layer, and specifically, not limited thereto, as long as the functional requirements of the first electrode layer 301 of the light emitting device unit and the functional requirements of the vertical signal line of lower resistance can be simultaneously satisfied. The conductive material having this structure can be used not only for forming the anode of the light emitting device unit but also for forming the driving signal line, for example, the VSS signal line 2 and the data signal line 4. That is, the anode made of the conductive material is matched with the impedances of the VSS signal line 2 and the data signal line 4, and can meet the anode making requirement of the light emitting device unit.
Specifically, the first electrode layer 301, the VSS signal lines 2 and the data signal lines 4 made of a conductive material including the first ITO layer 401/the metal layer 402/the second ITO layer 403 have a very small impedance due to the presence of the middle thick metal layer 402 of the conductive material, so that the impedance of the first electrode layer 301 is very small, and the requirement of a small impedance as a driving signal line is satisfied.
In the embodiment of the present invention, as shown in fig. 4, when the vertical signal line includes the VSS signal line 2, optionally, the cross-sectional area of the metal layer 402 of the VSS signal line 2 made of the conductive material is smaller than the cross-sectional areas of the first ITO layer 401 and the second ITO layer 402;
the light emitting layer 302 and the second electrode layer 303 sequentially cover the VSS signal line 2, and the second electrode layer 303 is in contact with and connected to the metal layer 402.
Specifically, as shown in fig. 4 in combination with fig. 3, the first ITO layer 401, the metal layer 402 and the second ITO layer 403 connected in sequence are formed in an "i" shape, wherein the VSS signal line 2 is fabricated on the planarization layer 206, the pixel defining layer 304 forms a spacing space at the periphery of the VSS signal line 2 when the pixel defining layer 304 is fabricated on the entire substrate 100 on which the light emitting layer 302, the VSS signal line 2 and the data signal line 4 are fabricated, wherein the light emitting layer 302 is fabricated on the entire substrate 100 on which the pixel defining layer 304 is fabricated, and is connected in contact with the first electrode layer 301 at the first electrode layer 301; at the VSS signal lines 2, extending to the lower side of the second ITO layer 402, is in contact connection with the first ITO layer 401 of the VSS signal lines 2. Further, a second electrode layer 303 is formed on the entire substrate 100 where the light emitting layer 302 is formed, and extends to the lower side of the second ITO layer 402 at the VSS signal line 2, and is in contact with the first ITO layer 401 and the metal layer 402.
With this embodiment, the VSS signal line 2 is formed of a conductive material formed in an i shape, and the light-emitting layer 302 is cut at the VSS signal line 2, and the second electrode layer 303 can be connected in contact with the metal layer 402 of the conductive material, thereby forming an auxiliary electrode using the VSS signal line 2.
In the embodiment of the present invention, optionally, the conductive material in the shape of "i" of the implementation structure may be manufactured by etching or sputtering, and will not be described in detail herein.
Further, with the above-described implementation structure, in combination with fig. 4, the thickness of the pixel defining layer 304 can be increased, so that the capacitances between the data signal line of the first electrode layer 301 (i.e., the anode layer) and the compensation signal line and the second electrode layer 303 (i.e., the cathode layer) can be further reduced.
With the display panel according to the embodiment of the present invention, as shown in fig. 3, the gate insulating layer 202 and the planarization layer 206 are separated between the data signal line and the scan signal line, compared with the prior art in which only the gate insulating layer is separated between the data signal line and the scan signal line, the planarization layer 206 is added, and the planarization layer 206 has a larger thickness, for example, usually greater than 2um, so that the separation thickness between the two lines can be greatly increased, and the capacitance between the two signal lines is reduced, thereby realizing smaller RC Loading on the data signal line and the scan signal line.
In addition, in the display panel according to the embodiment of the invention, the vertical signal lines perpendicular to the scanning signal lines are not limited to include only the VSS signal lines and the data signal lines, and may include any one of the VDD signal lines and the compensation signal lines, where the signal lines are all signal lines perpendicular to the scanning signal lines on the display panel at a longer distance.
Alternatively, with the above-described implementation structure, the material for forming the source/drain layer of the driving unit or the short-distance connection line may be different from the material for forming the vertical signal line perpendicular to the scanning signal line, and on this basis, the material for forming the source/drain layer of the driving unit does not need a low-resistance material, and therefore, the driving unit may be formed of a metal material having a high resistance but a high stability, such as a molybdenum material.
With reference to fig. 3 and 4, the manufacturing process of the display panel according to the embodiment of the present invention may include the following steps:
1) after the buffer layer 201 is manufactured on the substrate 100, the active layer 2011 and the gate insulating layer 202 are manufactured in sequence;
2) manufacturing a gate electrode layer 203 on the substrate 100 on which the active layer 2011 and the gate insulating layer 202 are manufactured, and simultaneously manufacturing a scanning signal line and a VDD signal line parallel to the scanning signal line by adopting the same composition process;
3) forming an interlayer insulating layer 204 on the substrate 100 on which the gate layer 203 is formed;
4) a source/drain layer 205 is formed on the substrate 100 on which the interlayer insulating layer 204 is formed, wherein the source/drain layer 205 includes a source and a drain for forming a thin film transistor, and a plate of a storage capacitor, i.e., a short distance wire. In the process, the part of the electrode layer which is manufactured has no higher requirement on resistance, and can be made of a material with good stability, thin thickness and large resistance, such as a molybdenum material; in addition, in the process, the manufactured source/drain layer 205 is connected to the active layer 2011 through a via;
5) fabricating a planarization layer 206 on the substrate 100 on which the source/drain layer 205 is fabricated; the thickness of the planarization layer 206 is typically 2um or more;
6) manufacturing a first electrode layer 301 on the substrate 100 on which the planarization layer 206 is manufactured, and manufacturing the VSS signal line 3 and the data signal line 4 by using the same conductive material and the same patterning process; alternatively, a VDD signal line and a compensation signal line, etc. parallel to the data signal line 4 may be simultaneously fabricated;
as shown in fig. 3, the first electrode layer 301 is connected to the source/drain layer 205 of the tft through a via hole penetrating the planarization layer 206;
in the embodiment of the invention, the conductive materials of the first electrode layer 301, the VSS signal line 3 and the data signal line 4 can be referred to the above detailed description, and are not described herein;
7) forming a pixel defining layer 304 on the substrate 100 on which the first electrode layer 301 is formed, wherein the pixel defining layer 304 forms a space corresponding to the periphery of the VSS signal line 2, and the first ITO layer 401, the metal layer 402 and the second ITO layer 403 of the VSS signal line 2 in an i-shaped structure are exposed at the space;
8) sequentially manufacturing a light-emitting layer 302 and a second electrode layer 304 on the substrate 100 on which the pixel defining layer 304 is manufactured, so that the light-emitting layer 302 is in contact connection with the first ITO layer 401 and the second electrode layer 303 is in contact connection with the first ITO layer 401 and the metal layer 402 at the VSS signal line 2;
9) a color film layer, a glass cover plate, and the like are sequentially formed on the substrate 100 on which the second electrode layer 304 is formed.
Based on the above process, the whole display panel can be manufactured.
Optionally, the display panel is formed as a WOLED display panel, that is, light emitted by the light emitting device unit is white light. Of course, the display panel is not limited to being only a WOLED display panel.
When the display panel is a WOLED display panel, as shown in fig. 3, the display panel further includes a color film layer 500 and a glass cover plate 600.
With this embodiment, in the light emitting device unit of the display panel, the first electrode layer, the light emitting layer, and the second electrode layer, which are sequentially stacked, are formed as one pixel unit; on the display panel, a plurality of pixel units are arranged in an array.
According to the display panel disclosed by the embodiment of the invention, because the Gap between the glass cover plate and the substrate base plate exists, in order to prevent the visual problem caused by light leakage, the distance between adjacent light emitting areas needs to be enlarged, and a black matrix BM is manufactured on the glass cover plate to shield the light leakage; generally, according to the Gap and light leakage requirements, the BM width is relatively wide, so the distance between adjacent PDLs is also very wide, and the distance between corresponding Anode electrodes is also relatively wide (for example, about 25 um); on the basis, the data signal line and the anode are manufactured in the same layer and are arranged between the adjacent pixel units, and the space is quite sufficient, so that the aperture opening ratio of the pixel is not influenced compared with a display panel in a traditional mode.
By adopting the display panel provided by the embodiment of the invention, the vertical signal line vertical to the scanning signal line and the electrode layer of the light-emitting device unit are manufactured in the same layer, compared with the prior art, the thickness between the scanning signal line and the vertical signal line is larger, the capacitance at the overlapped part of the scanning signal line and the vertical signal line is reduced, the RC Loading on the scanning signal line is reduced, and the RC on the vertical signal line is reduced, so that the problem that the waveform distortion of a driving signal is serious due to the larger RC Loading in the display panel in the prior art is solved.
An embodiment of the present invention further provides a display device, which includes the display panel with the above structure.
From the above detailed description, those skilled in the art should understand the specific structure of the display device using the display panel according to the embodiment of the present invention, and will not be described in detail here.
An embodiment of the present invention further provides a method for manufacturing a display panel with the above-described structure, as shown in fig. 5, the method includes:
s510, providing a substrate base plate;
s520, sequentially manufacturing a driving unit and a light-emitting device unit on the substrate;
when the grid layer of the driving unit is manufactured, a scanning signal line is manufactured through the same composition process with the grid layer; when the first electrode layer of the light-emitting device unit is manufactured, the vertical signal line and the first electrode layer are manufactured through the same composition process.
Optionally, the manufacturing method, wherein the vertical signal line is a VSS signal line, and in a process of manufacturing a light emitting device unit, the manufacturing of the light emitting device unit includes:
manufacturing a pixel defining layer on the substrate completing the manufacturing of the driving unit;
manufacturing a first electrode layer on the pixel limiting layer, and manufacturing the VSS signal line by the same composition process with the first electrode layer; the first electrode layer and the VSS signal line respectively comprise a first ITO layer, a metal layer and a second ITO layer which are sequentially stacked;
etching the VSS signal line to enable the VSS signal line to be located in an opening on the pixel limiting layer, wherein the cross-sectional area of the metal layer is smaller than that of the first ITO layer and that of the second ITO layer;
sequentially manufacturing a light emitting layer and a second electrode layer on the substrate for manufacturing the first electrode layer and the VSS signal line; and in the opening, the light-emitting layer is in contact connection with the first ITO, and the second electrode layer is in contact connection with the metal layer.
From the above detailed description, with reference to fig. 3 and fig. 4, a specific process of the method for manufacturing a display panel according to the embodiment of the present invention can be understood, and will not be described in detail herein. While the preferred embodiments of the present invention have been described, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
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| WO2023201657A1 (en) * | 2022-04-21 | 2023-10-26 | 京东方科技集团股份有限公司 | Light-emitting panel and preparation method therefor, and light-emitting device |
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| WO2023201657A1 (en) * | 2022-04-21 | 2023-10-26 | 京东方科技集团股份有限公司 | Light-emitting panel and preparation method therefor, and light-emitting device |
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