CN113140515A

CN113140515A - Method for adjusting Beta ratio of SRAM

Info

Publication number: CN113140515A
Application number: CN202110330232.3A
Authority: CN
Inventors: 景旭斌
Original assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Current assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date: 2021-03-29
Filing date: 2021-03-29
Publication date: 2021-07-20

Abstract

The present invention provides a method for adjusting the ratio of SRAM Beta, which provides a substrate on which a plurality of polysilicon structures spaced from each other are formed; A Halo implantation region is formed in the substrate; at the same time, an LDD region is formed in the substrate above the Halo implantation region; source and drain are respectively formed in the substrate on both sides of the polysilicon structure; the source and drain are farther from the polysilicon than the Halo implantation region and the LDD region. structure. The invention starts from optimizing the performance of the SRAM itself, does not pass the peripheral circuit, does not add an extra mask, utilizes the injection shadow effect, and changes the device speed sensitivity coefficient of the two SRAM devices to the polysilicon CD by introducing a large oblique angle halo implantation, using different values The sensitivity coefficient of SRAM can be adjusted in different directions of the pull-down tube and control tube device speed of the SRAM to adjust the driving current of the two devices of the pull-down tube and the control tube respectively, so as to achieve the purpose of adjusting the beta ratio and optimizing the read operation device window.

Description

Method for adjusting Beta ratio of SRAM

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method for adjusting Beta ratio of an SRAM.

Background

With the continuous development of very large scale integrated circuit technology, the device size is continuously reduced, especially the size of the SRAM device is reduced to the utmost. Two types of NMOS devices, namely a pull-down tube down and a control tube pass gate, are basically consistent in an SRAM layout with high layout density, so that the beta ratio is smaller and no effective adjusting means is provided. The small Beta ratio causes the problem of small process window of reading operation, and limits the reduction of SRAM Vccmin and the unstable yield.

In the technology of 28nm and below, the most widely applied solution at present is to introduce a read-write auxiliary circuit, raise Vdd through an external circuit, reduce word line voltage means to temporarily increase Beta ratio, and increase the window of SRAM cell read operation. The method can solve the read-write operation problem of the SRAM, but adverse effects such as increased compiler layout area, increased cost, increased circuit design complexity, limited operation speed and the like caused by the introduction of an additional circuit are simultaneously caused.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for adjusting the Beta ratio of an SRAM, which is used to solve the problem of the prior art that the Beta ratio is too small in the SRAM device.

To achieve the above and other related objects, the present invention provides a method for adjusting SRAM Beta ratio, at least comprising:

providing a substrate, and forming a plurality of polysilicon structures which are mutually spaced on the substrate;

injecting Halo into the substrate between the adjacent polycrystalline silicon structures at an oblique angle, and forming Halo injection regions in the substrates at two sides of the polycrystalline silicon structures; simultaneously forming an LDD region in the substrate above the Halo implant region;

respectively forming source and drain electrodes in the substrates at two sides of the polycrystalline silicon structure; the source and drain are far away from the polysilicon structure than the Halo implantation region and the LDD region.

Preferably, the plurality of polysilicon structures in step one are used to form gates of NMOS or PMOS.

Preferably, the CD size of the polysilicon structures in the first step is 22 nm-52 nm.

Preferably, the CD size of the plurality of polysilicon structures in the first step is 43 nm.

Preferably, in the first step, in the several polysilicon structures spaced from each other, the NMOS of two adjacent polysilicon structures respectively serve as a pull-down transistor and a control transistor of the SRAM.

Preferably, in the second step, the bevel angle is an included angle between the bevel angle and the side wall of the polysilicon structure during implantation.

Preferably, the included angle in the second step is 15 to 50 degrees.

Preferably, the included angle in the second step is 35 degrees.

As mentioned above, the method for adjusting the SRAM Beta ratio of the invention has the following beneficial effects: the invention starts from optimizing the performance of the SRAM, does not pass through a peripheral circuit, does not increase an extra photomask, utilizes the injection shadow effect, changes the device speed sensitivity coefficient of two SRAM devices to the polysilicon CD by introducing large-inclination angle halo injection, and utilizes the sensitivity coefficients with different values to realize the debugging of different directions of the speeds of the pull-down tube and the control tube of the SRAM so as to respectively adjust the drive currents of the two devices of the pull-down tube and the control tube, thereby achieving the purposes of adjusting the beta ratio and optimizing the window of a read operation device.

Drawings

FIG. 1 is a schematic diagram of a CMOS structure in an SRAM structure in the prior art;

FIG. 2 is a schematic diagram of an SRAM structure according to the present invention;

FIGS. 3-7 are graphs showing the results of a large bevel halo implant and POLY CD experiments in accordance with the present invention;

FIG. 8 is a flowchart illustrating a method for adjusting the SRAM Beta ratio according to the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

A method for adjusting SRAM Beta ratio, as shown in fig. 8, fig. 8 is a flowchart of the method for adjusting SRAM Beta ratio according to the present invention, the method at least includes the following steps:

providing a substrate, and forming a plurality of polysilicon structures which are mutually spaced on the substrate; as shown in FIG. 2, FIG. 2 is a schematic diagram of the SRAM structure of the present invention. In this step one, a plurality of spaced polysilicon structures (GATE) are formed on the substrate, only two of which are shown in fig. 2.

Further, the polysilicon structures in the first step are used for forming gates of NMOS or PMOS. In this embodiment, the polysilicon structures are all used to form the gate of the NMOS of the SRAM.

Further, the CD size of the polysilicon structures in the first step of the invention is 22 nm-52 nm. In the prior art, the CD size of the NMOS or PMOS polysilicon structure in the SRAM with different process nodes is 20 nm-50 nm, and the CD of the polysilicon structure is increased by 2nm on the basis of the prior art.

Further, the CD size of the polysilicon structures in the first step of this embodiment is 43 nm.

Furthermore, in the first step of this embodiment, in the several polysilicon structures spaced from each other, the NMOS of two adjacent polysilicon structures are respectively used as the pull-down transistor and the control transistor of the SRAM.

further, in the second step of this embodiment, the bevel is an angle between the polysilicon structure and the sidewall during the implantation. As shown in fig. 2, the angle between the ray and the sidewall of the polysilicon structure is the oblique angle of implantation.

Further, the included angle in the second step of the invention is 15-50 degrees. In the prior art, the included angle is 10-45 degrees, and the included angle is increased by 5 degrees on the basis of the prior art.

Further, the included angle in the second step of this embodiment is 35 degrees.

Step three, forming source and drain electrodes (SD) in the substrates on the two sides of the polycrystalline silicon structure respectively; the source and drain are far away from the polysilicon structure than the Halo implantation region and the LDD region.

Conventional planar CMOS processes utilize a combination of tilted halo, LDD and SD implants to form devices of different performance. As shown in fig. 1, fig. 1 is a schematic diagram of a CMOS structure in an SRAM structure in the prior art.

Normally, poly CD (polysilicon structure) has a negative value of the sensitivity coefficient a for the device speed, i.e. the larger the poly CD, the slower the device speed. The dose of the normal angle halo implant is adjusted to have a sensitivity coefficient B which is also negative with respect to the device speed, i.e., the larger the implant dose, the slower the device speed. At this time, the poly CD or halo implantation doses of the (pull-down tube) pull-down device and the (control tube) pass gate device in the SRAM are adjusted, the change directions of the two devices are consistent, namely, the two devices are simultaneously accelerated or simultaneously decelerated, and the (beta ratio) beta ratio (pull-down/pass gate) determining the reading operation of the SRAM cell is basically kept unchanged. An example formula for device speed (saturation current) is briefly described as follows: idsat is Id0+ a Δ CD + B Δ CD.

If the halo implant angle is continuously increased and blocked by poly on both sides, a phenomenon called shadow effect occurs, and part of the ion implantation is blocked from entering the effective channel region under the poly. This effect is more pronounced if the angle continues to increase until the inversion halo ions do not reach under the channel at all, and the short channel effect (short channel effect) of the device is out of control. The shadow effect of halo can also be changed by adjusting the poly and its upper hard mask layer (hard mask) thickness and poly spacing distance (space), such as increasing the thickness or decreasing the space, which can aggravate the blocking ratio. The junction leakage (junction leak) is deteriorated by the halo implantation amount increased by the severe shadow effect, and the shadow effect is avoided as much as possible by the general process. As shown in fig. 2, fig. 2 is a schematic diagram of a MOS structure used in an SRAM according to the present invention.

The present invention takes advantage of the shadow effect, but at the same time controls its adverse effects. By adding halo angle experiments, the critical angle which just can effectively change the threshold Voltage (VT) is found. Generally, the length of the implantation region is 100-250A longer than that of the full shadow. The implantation area is shown as A in FIG. 2, the line segment area is defined by the ray clinging to the bottom of the gate and the top of the gate beside the gate, when the implantation angle is increased or the gate height is increased, the length of the implantation area (line segment area) is reduced, and when the red line segment is equal to or less than zero, the full shadow condition is adopted, and the implantation cannot enter.

When the halo angle is increased to the critical angle, POLY CD (lithography or etching) is integrally adjusted, because the lengths (POLY lengths) of the original polysilicon structures of pull down and pass gate devices are different, the sensitivity of the pull down and pass gate devices to CD change is different, and meanwhile, the halo shadow effect caused by space change brought by the CD change needs to be considered, and by combining the feedback of the two different effects, the sensitivity coefficient A of the change of POLY CD to the device speed can be converted from a negative value to zero or even a positive value, and the sensitivity coefficient A values of the devices with different sizes can be different or even have a positive-negative condition. There is now an opportunity to change the beta ratio.

Increasing poly CD slows the device speed, but decreasing poly space spacing (poly space) enhances halo implant shadowing resulting in a decrease in halo effective inversion ion access to the channel, which has the opposite effect of speeding the device speed. In an experiment, 2nm poly CD is added through a photoetching process, 5 degrees are added on the basis of an original halo angle, the initial expectation that Pull down and Pass gate become slow simultaneously does not appear in an electrical property test, and instead, the result that the Pass gate speed is kept unchanged and the Pull down speed is increased by 12 percent is obtained, namely the CD sensitivity coefficient A of a Pull down device becomes a positive value and the CD sensitivity coefficient A of a Pass gate device becomes zero. Experiments have the effect of increasing 12% of beta ratio, and the Iread reading current is increased by 10%, so that the reading operation of the SRAM is facilitated, and the performance of the SRAM is improved. And repeating a plurality of groups of halo injection dosage experiments to obtain the same experiment result. The feasibility and the repeatability of the invention are verified. The experimental results are shown in fig. 3 to 7. FIGS. 3-7 are graphs showing the results of the large bevel halo implantation and POLY CD experiments of the present invention. The PO CD BL in FIGS. 3-7 refers to the CD of the polysilicon structure in the prior art process (e.g., 41nm), and PO CD + refers to the CD of the polysilicon structure in the present invention (i.e., 43nm in this embodiment).

In conclusion, the invention starts from optimizing the performance of the SRAM, does not pass through a peripheral circuit, does not increase an extra photomask, utilizes the injection shadow effect, changes the device speed sensitivity coefficients of two SRAM devices to the polysilicon CD by introducing the halo injection with a large inclination angle, and utilizes the sensitivity coefficients with different values to realize the debugging of different directions of the device speeds of the pull-down tube and the control tube of the SRAM so as to respectively adjust the drive currents of the two devices of the pull-down tube and the control tube, thereby achieving the purposes of adjusting the beta ratio and optimizing the window of a read operation device. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A method for adjusting SRAM Beta ratio, comprising:

2. The method of adjusting SRAM Beta ratio of claim 1, wherein: and the plurality of polysilicon structures in the first step are used for forming gates of NMOS or PMOS.

3. The method of adjusting SRAM Beta ratio of claim 1, wherein: the CD size of the polysilicon structures in the first step is 22 nm-52 nm.

4. The method of adjusting SRAM Beta ratio of claim 3, wherein: the CD size of the polysilicon structures in the first step is 43 nm.

5. The method of adjusting SRAM Beta ratio of claim 2, wherein: in the step one, in the plurality of mutually spaced polysilicon structures, the NMOS of two adjacent polysilicon structures are respectively used as a pull-down tube and a control tube of the SRAM.

6. The method of adjusting SRAM Beta ratio of claim 1, wherein: and in the second step, the oblique angle is an included angle between the oblique angle and the side wall of the polycrystalline silicon structure during injection.

7. The method of adjusting SRAM Beta ratio of claim 6, wherein: and the included angle in the second step is 15-50 degrees.

8. The method of adjusting SRAM Beta ratio of claim 7, wherein: and the included angle in the second step is 35 degrees.