CN113132662A

CN113132662A - Method and device for realizing HDMI2.1 interface data transmission based on FPGA and conversion box

Info

Publication number: CN113132662A
Application number: CN202110410653.7A
Authority: CN
Inventors: 张朝春
Original assignee: Shenzhen City Shixian Optoelectronics Technology Co ltd
Current assignee: Shenzhen City Shixian Optoelectronics Technology Co ltd
Priority date: 2021-04-14
Filing date: 2021-04-14
Publication date: 2021-07-16

Abstract

The invention discloses a method, a device and a conversion box for realizing HDM I2.1 interface data transmission based on an FPGA (field programmable gate array), and relates to the technical field of HDM I and high-definition video display. The method is applied to an FPGA chip, wherein the FPGA chip comprises a transceiver, and the method comprises the following steps: receiving a video data source; for the data in the data channel of each video data source, executing the following steps in parallel: if the data is in an FRL format, sequentially carrying out TMDS Tri-Byte group flow, FRL group packing, FRL partitioning block and Super block combined mapping, inserting RS (Reed-Solomon) front item error correcting codes, FRL scrambling codes and coding processing on the data; converting the bit width of the data to a bit width adapted by the transceiver, and inputting the data into the transceiver. The technical scheme of the embodiment of the invention perfectly realizes the transmission of the HDM I2.1 interface data by utilizing the advantages of a high-speed transceiver (Transce I ver) of the FPGA and the parallel data processing thereof, thereby effectively solving the problem that no HDM I2.1 interface chip can be supported in the market due to high HDM I2.1 interface speed and large logic structure complexity.

Description

Method and device for realizing HDMI2.1 interface data transmission based on FPGA and conversion box

Technical Field

The invention relates to the technical field of HDMI2.1 and high-definition video display, in particular to a method, a device and a conversion box for realizing HDMI2.1 interface data transmission based on FPGA.

Background

The high resolution/high frame rate, High Dynamic Range (HDR) has become a performance index pursued in the field of video display. The high resolution can bring more exquisite visual presentation to a large-size display panel, more smooth video playing is brought to a high frame rate, higher contrast is brought to lower delay and high dynamic range display, and the image quality effect can be obviously improved in the same scene.

In 2017, in 11 months, the HDMI alliance issues a new HDMI2.1 standard, and the bandwidth is increased to 48Gbps (the highest support for 10K × 5K @60Hz video image transmission), dynamic HDR, dynamic refresh rate, enarc and other new characteristics. The HDMI2.1 bandwidth with the highest 48Gbps provides a new height for the design of the transmission line, the speed of a single differential pair is 12Gbps which is twice that of the HDMI2.0, and in order to ensure the stability of transmission signals, different types of HDMI2.1 optical fiber transmission lines appear on the market, and the transmission distance can reach dozens of meters to hundreds of meters. In the coming years of 5G to popularization, various 8K products gradually enter the eye of the ordinary public, and the HDMI2.1 standard is pushed out to have a vital significance for pushing the 8K industry chain.

2017. 2018, a series of 4-channel HDMI2.0 splicing input 8K television schemes are successively provided by the sharp on the market, 4 HDMI connecting lines are needed in practical application, 8K video picture point-to-point display can be realized through the splicing channels, and the common household set top box can not meet the use scene because the splicing channels are matched with special 8K source output equipment. In these two years, as the providers of television solutions support the sequential release of the SOC chip of the HDMI2.1 standard to the market, TV complete plants begin to adopt the scheme of competing for the high-end 8K televisions, and domestic haisi semiconductors also propose the scheme of HDMI2.1 TV-BOX chip, so that the problems that the source device supporting the HDMI2.1 output cannot be perfectly connected to the 8K television of the sharp splicing scheme and the 8K broadcast source device of the splicing scheme cannot be perfectly connected to the 8K television of the HDMI2.1 interface occur.

Disclosure of Invention

The embodiment of the invention provides a method, a device and a conversion box for realizing HDMI2.1 interface data transmission based on an FPGA (field programmable gate array), and aims to solve the problem that no 8K conversion equipment capable of being matched with an HDMI2.1 interface exists in the market due to high HDMI2.1 rate at present.

In a first aspect, an embodiment of the present invention provides a method for implementing HDMI2.1 interface data transmission based on an FPGA, where the method is applied to an FPGA chip, the FPGA chip includes a transceiver, and the method includes:

receiving a video data source, the video data source comprising a plurality of data channels;

for the data in each data channel, executing the following steps in parallel: if the data is in an FRL format, sequentially carrying out TMDS Tri-Byte group flow, FRL group packing, FRL block and Super block combined mapping, inserting RS (Reed-Solomon) front item error correcting codes, FRL scrambling codes and coding treatment on the data; converting the bit width of the data to a bit width adapted by the transceiver, and inputting the data into the transceiver.

The further technical scheme is that the method also comprises the following steps:

if the format of the data is TMDS format, carrying out TMDS Tri-Byte group flow processing on the data;

converting a bit width of the data to a bit width adapted for the transceiver;

performing TMDS scrambling and coding processing on the data;

inputting the data into the transceiver.

The method further comprises the following steps that before TMDS Tri-Byte group flow processing is carried out on the data:

the data is encoded by a VESA DSC encoder.

The further technical scheme is that after TMDS Tri-Byte group flow processing is carried out on the data, the method further comprises the following steps:

and carrying out HDCP2.x encryption processing on the data.

and if the format of the data is an FRL format, executing a data training process on the data.

In a second aspect, an embodiment of the present invention further provides an apparatus for implementing HDMI2.1 interface data transmission based on an FPGA, which includes a unit for executing the foregoing method.

In a third aspect, an embodiment of the present invention further provides a computer device, which includes a memory and a processor, where the memory stores a computer program, and the processor implements the above method when executing the computer program.

In a fourth aspect, the present invention also provides a computer-readable storage medium, which stores a computer program, and the computer program can implement the above method when being executed by a processor.

The invention can achieve the following technical effects:

according to the technical scheme of the embodiment of the invention, the transmission of the HDMI2.1 interface data can be realized by utilizing the advantages of a high-speed Transceiver (Transceiver) of the FPGA and the parallel data processing of the FPGA, so that the problem that no 8K conversion box can support the HDMI2.1 interface in the market due to high HDMI2.1 interface speed and high logic structure complexity is effectively solved. Furthermore, the technical scheme of the invention can simultaneously support an FRL format and a TMDS format, thereby solving the problem of mutual conversion of signals of HDMI2.1 and HDMI2.0 devices.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic flowchart of a method for implementing HDMI2.1 interface data transmission based on an FPGA according to an embodiment of the present invention;

fig. 2 is a schematic block diagram of a method for implementing HDMI2.1 interface data transmission based on an FPGA according to an embodiment of the present invention;

FIG. 3 is a functional block diagram of process 9 of FIG. 2;

FIG. 4 is a schematic diagram of bit width conversion process in process 9 according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the FRL encoding process of FIG. 3;

FIG. 6 is a schematic block diagram of a converter box provided by an embodiment of the present invention;

FIG. 7 is a diagram of an application scenario of a transition box according to the present invention;

FIG. 8 is a diagram of an application scenario of a transition box according to the present invention;

FIG. 9 is a diagram of an application scenario of a transition box according to the present invention;

FIG. 10 is a diagram of an application scenario of a transition box according to the present invention;

FIG. 11 is a diagram of an application scenario of a transition box according to the present invention;

fig. 12 is a schematic block diagram of an apparatus for implementing HDMI2.1 interface data transmission based on FPGA according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Referring to fig. 1-2, fig. 1 is a schematic flow chart illustrating a method for implementing HDMI2.1 interface data transmission based on an FPGA according to an embodiment of the present invention. Fig. 2 is a schematic block diagram of a method for implementing HDMI2.1 interface data transmission based on an FPGA according to an embodiment of the present invention. The method is applied to an FPGA chip and is realized at a transmitting end of HDMI2.1, and the FPGA chip comprises a transceiver. As shown, the method includes the following steps S1-S2.

S1, receiving a video data source, wherein the video data source comprises a plurality of data channels (Lane).

In a specific implementation, a video data source is received, and the format of the video data source includes an FRL format and a TMDS format. The video data source includes a plurality of data channels (Lane).

For example, the FRL format is an HDMI2.1 add-on transmission format, supporting multi-line multi-rate (4Lane includes four rates of 12Gbps, 10Gbps, 8Gbps, 6Gbps, and 3Lane includes two rates of 6Gbps, 3 Gbps).

TMDS is a data transmission format supported by HDMI2.0 and previous versions.

S2, for the data in each data channel, executing the following steps in parallel: if the data is in an FRL format, sequentially carrying out TMDS Tri-Byte group flow, FRL group packing, FRL block and Super block combined mapping, inserting RS (Reed-Solomon) front item error correcting codes, FRL scrambling codes and coding treatment on the data; converting the bit width of the data to a bit width adapted by the transceiver, and inputting the data into the transceiver.

Further, in an embodiment, step S2 further includes: if the format of the data is TMDS format, carrying out TMDS Tri-Byte group flow processing on the data; converting a bit width of the data to a bit width adapted for the transceiver; performing TMDS scrambling and coding processing on the data; inputting the data into the transceiver.

In a specific implementation, the process of implementing parallel processing at the HDMI2.1 transmitting end in the above steps is shown in fig. 2 (the data flow at the receiving end is the reverse process of the transmitting end). The concrete description is as follows:

if the transmission adopts an FRL data format, the following steps are executed in parallel on the data in each channel of the video data source: TMDS Tri-Byte packet stream (process 1), hdcp2.x encryption (process 2), FRL packet (process 5), FRL partition and Super block combination mapping (process 6), inserting RS-antecedent error correction code (process 7), FRL scrambling and coding (process 8) and transformation B (process 9); after the above-described process is performed, the data is input to a Transceiver (Transceiver). Among them, hdcp2.x encryption is an optional processing method. For FRL format data, the interference resistance in the data transmission process is greatly improved by adding an RS forward error correction code processing process.

The transformation B is specifically to transform the bit width of the data into a bit width adapted to the Transceiver so that the data can be adapted to the Transceiver (Transceiver).

Further, if the format of the data of the video data source is FRL format, a data Training (Training) process needs to be performed on the data, so as to ensure that the data transmitted at high rate is reliably received by the receiving end.

If the transmission adopts TMDS data format, the following steps are executed in parallel to the data in each channel of the video data source: TMDS Tri-Byte group stream (process 1), hdcp2.x encryption (process 2), transform a (process 3), and TMDS scrambling and encoding (process 4); after the above-described process is performed, the data is input to a Transceiver (Transceiver). Among them, hdcp2.x encryption is an optional processing method.

Specifically, the transformation a is to transform the bit width of the data into a bit width adapted to the Transceiver so that the data can be adapted to the Transceiver (Transceiver).

Further, with continued reference to fig. 2, in some embodiments, before TMDS Tri-Byte group stream processing the data, the method further comprises: the data is encoded by a VESA DSC encoder, which is an optional process.

According to the technical scheme of the embodiment of the invention, the transmission of the HDMI2.1 interface data can be realized by utilizing the advantages of a high-speed Transceiver (Transceiver) of the FPGA and the parallel data processing, so that the problem that no 8K conversion box can support the HDMI2.1 interface in the market due to high HDMI2.1 interface rate and high logic structure complexity is effectively solved. Furthermore, the technical scheme of the invention can simultaneously support an FRL format and a TMDS format, thereby solving the problem of mutual conversion of signals of HDMI2.1 and HDMI2.0 devices.

In order to better illustrate the technical solution of the present invention, the above parallel processing process is described in detail as follows:

in fig. 2, the data is output as a final high-speed serial signal by a Transceiver (Transceiver) of the FPGA. Each data channel of the parallel data after TMDS format data coding takes 10-bit integral multiple as an output unit, and can select 10bit, 20bit, 40bit and the like for parallel processing bit width. And the data in single FRL format is 16 bits, each channel of the encoded data takes 18-bit integer multiple as an output unit, and the bit width can be selected to be processed in parallel by 18 bits, 36 bits, 72 bits and the like. In order to ensure that the bit widths of two different output data can be adapted to the optional parallel bit width of the transceiver, the self performance of the FPGA and the logic occupation amount are considered, and 40bit width is selected as the bit width of the parallel input of the transceiver. Thus the parallel data clock is 150MHz for TMDS signals up to 6 Gbps. The clock of the parallel data of the FRL signal with the highest 12Gbps is 300MHz, and the bit width of the parallel data coded by the FRL data is selected to be 72 bits (a single clock processes 4 FRL data of a single data line in parallel, an equivalent single clock cycle processes 16 FRL data in a 4Lane mode, and an equivalent single clock cycle processes 12 FRL data in a 3Lane mode). Therefore, 72-bit-width continuous parallel data needs to be converted into 40-bit-width continuous data to be output to the transceiver, and a conversion logic (namely, a process 9 and a conversion B) between an FRL link layer and a physical layer needs to be inserted, so that the designed parameter indexes conform to the performance range of an FPGA chip, and the problem that an FRL data format and a TMDS data format can be simultaneously switched and output to the transceiver to be converted into high-speed serial data is solved.

Further, since the process 1 and the process 2 simultaneously include two data output formats, the number of parallel processes is determined as follows:

since FRL data is reassembled from TMDS Tri-Byte streams, if the transmission using this mode is based on the fact that FRL provides a bandwidth theoretically higher than the data bandwidth of Tri-Byte streams, the maximum clock frequency of Tri-Byte streams can be roughly calculated according to the following formula:

F_{tb_clk_max}＝N_Lane×R_Transfer×E_Encode×R_Video÷B_TriByte

F_{tb_clk_max}the highest clock frequency allowed by the Tri-Byte group flow in the highest FRL mode.

N_LaneThe number of data lines is transmitted in FRL mode (4 or 3).

R_TransferThe highest transmission rate in FRL mode (12Gbps, 10Gbps, 8Gbps, 6Gbps, 3 Gbps).

EEncode is the transmission coding efficiency in FRL mode (fixed at 16: 18).

R_VideoThe ratio of active video to total line time is output for the video (taking 0.9 here to account for allowing the video to be transmitted with the blanking time borrowed).

B_TriByteIs the data bit width (fixed at 24 bits) of the Tri-Byte stream.

The highest clock frequency allowed by the highest Tri-Byte group flow according to the above formula is

For the master frequency which greatly exceeds the internal logic of the FPGA (usually, the frequency of a large-area logic clock is designed by taking 300M as an upper limit), the master frequency and the resource usage are considered, so that the master frequency of the clock is treated in parallel by taking 8 Tri-Bytes as a clock unit, and is shifted to 200MHz, thereby equivalently realizing the maximum performance to meet the design requirement.

Further, in the process 4, since the transceiver is directly connected to the FPGA through the selector, the input Bit width of the transceiver is 40 bits, and if 4 Tri-Bytes are selected for parallel processing, the Bit width of the encoded data on each transmission data channel is just 40 bits. In order to meet the maximum performance of FRL, the

processes

1 and 2 select 8 times of Tri-Bytes as a single clock cycle processing unit, and the interfaces of the process 4 cannot be directly connected with each other, so that the process 3 is inserted between the

processes

2 and 4 to realize the conversion from 8 times of Tri-Bytes to 4 times of Tri-Bytes in bit width, and the process 4 clock frequency is converted into twice of the

processes

1 and 2, thereby realizing the equal rate of two sides.

Process 3 is similar to process 9 in that process 9 is used as an example to illustrate the manner/method.

Specifically, the specific implementation of the process 9 is as follows:

the encoder of the transceiver of the FPGA is 8B10B hardware codec of IBM, while HDMI2.1 uses 16B18B encoding in FRL mode, and the internal hardware encoding of the transceiver itself needs to be disabled and external software encoding is used. The transceiver User parallel data logic Clock is referred to herein as User Clock and the synchronous Clock at the FRL processing side is referred to as FRL Clock (for processing processes 5, 6, 7, 8).

The implementation process 9 of the transmitting end is shown in fig. 3 (the receiving end is the inverse process of the next figure), in the figure, the corresponding conversion relation of a single data line is shown, and the clock of the input and output of the bit width-frequency transmission (gearshifting) is controlled without deviation through a phase-locked loop.

Taking the 12Gbp rate as an example, the specific implementation process is as follows, the input clock is 300.000MHz, and the input data bit is 72 bits wide. The output clock is 166.667MHz, and the output data is 40 bits wide.

The first step is as follows: the least common multiple of

calculations

72 and 40 is 360 and the logic implementation defines a data cache space data _ Bufer of 360 bits size, where we use a Register (Register) to implement the cache.

The second step is that: the input data position change period is 360 divided by 72 and equals 5, the output data position change period is 360 divided by 40 and equals 9, and logic implementation defines an input position in _ addr (which changes from 0, 1, 2, 3 and 4) and an output position out _ addr (which changes from 0, 1, …, 7 and 8), wherein in _ addr is driven by the input clock and out _ addr is driven by the output clock. The in _ addr is 0 to update the 0 th bit to the 71 th bit of the data _ buffer, the in _ addr is 1 to update the 72 th bit to the 143 th bit of the data _ buffer, and so on; the out _ addr outputs the 0 th bit to the 39 th bit of the data _ buffer for 0, the out _ addr outputs the 40 th bit to the 79 th bit of the data _ buffer for 1, and so on, as shown in FIG. 4.

The third step: defining a flip signal tog, in _ addr flips once (0 to 1 or 1 to 0) per cycle of change, e.g. each time the position flips at position 3, the position of the flip can be arbitrarily chosen. The inverted signal tog is synchronously sampled in an output clock domain, the synchronized signal is defined as tog _ sync, the position of the out _ addr is reset at the time when the tog _ sync is inverted, and if the position is abnormal (the reset position value is inconsistent with the originally normally changed expected value), dynamic adjustment can be realized, so that the conflict of reading and writing without cache is ensured, the robustness of a logic function is greatly enhanced, and the function of bit width frequency change is realized.

Further, the implementation manner/method (example of parallel processing manner) of the FRL-encoded FPGA in fig. 3 is as follows:

the HDMI2.1 FRL data transmission adopts 16B18B encoding, the encoding mode comprises two special 18bit characters SSB/SR which are used for FRL block synchronization and receiving end character alignment, the encoding is to balance the number of 0 and 1 in the transmission link, and simultaneously, the encoding efficiency of TMDS 8B10B is improved. The number of serial data streams 1 minus 0 in the transmission link is called Running Disparity (RD), the encoding method divides 16bit input data into low 9bit and high 7bit, which correspond to 9B10B lookup table and 7B8B lookup table respectively, the encoding process firstly passes through 9B10B encoding table and then passes through 7B8B encoding table to output the whole 18bit result, RD before 9B10B lookup table input is called Running Front Disparity (RFD), RD after 9B10B lookup table output (7B8B lookup table input data) is called Running Mid-Disparity (rmd), 7B8B lookup table output data RD is called Running End Disparity (RED), the initial value of RD is set to +3, +1, -3, and the RD value in the whole encoding process varies among several values.

The actual FPGA adopts 4 characters symbol to be synchronously coded together in parallel, the coding structure is realized as shown in FIG. 5, wherein DFF is a D trigger, X3, X2, X1 and X0 are four 16-bit FRL high-order characters to low-order characters, RY3, RY2, RY1 and RY0 are coded and then output by latching the high-order characters to the low-order characters through the D trigger, the results of unbalanced quantities of '0' and '1' RED3 of a single clock after being coded by 4-level processing are input as RFD0 calculated in the next clock period after being latched by the D trigger, and a dashed box represents a single 16B18B coding table function module.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a switch box 100 according to an embodiment of the present invention. As can be seen, the converter box 100 includes an FPGA chip 30. The FPGA chip 30 includes a transceiver, and the FPGA chip 30 is configured to execute the method for implementing the HDMI2.1 interface data transmission based on the FPGA according to the above embodiment.

Further, the converter box 100 also includes a plurality of HDMI2.1 input interfaces 10 (e.g., 4), a plurality of HDMI2.1 output interfaces 20 (e.g., 4), and a configuration interface 40.

In a specific embodiment, the board card of the converter box 100 uses the FPGA chip 30 with the model number KU060(-2I) of Xilinx corporation as a core, the FPGA chip 30 provides 726K basic logic units, a 38Mbit block RAM, and 32 highest 16.375Gbps transceivers (transceivers, which implement conversion between parallel data and high-speed serial data), and the auxiliary circuit includes 4 HDMI input interfaces 10, 4 HDMI output interfaces 20, and a control configuration interface 40. Each of the HDMI input interface 10 and the HDMI output interface 20 supports the HDMI2.1 (maximum 48Gbps) specification, and the HDMI input/output main link high-speed differential signal is implemented by a high-speed Transceiver (Transceiver) of an FPGA. The configuration interface 40 is used for setting an application scene, and includes a universal gigabit network port and an RS232 serial port, the gigabit network port realizes setting and web page control of the board card, and the RS232 serial port completes printing and debugging of information.

Example of applicable scenarios for 8K transition Box

1. One input source broadcast mode is output to a plurality of output ports, and the application scene is shown in fig. 7.

The setting method comprises the following steps:

and (I) the playing source is connected to any input port of the conversion box.

And (II) the output port of the conversion box is connected with the input port of a television or other conversion boxes (the output port of the conversion port is connected with other conversion boxes to realize the expansion of the output port).

And (III) setting the content of the target input port to be broadcast to all output ports by the configuration interface, and if the four ports are connected with input sources, selecting any one of 4 ports by software configuration.

2. Conversion between HDMI interfaces of products with different 8K forms (including A conversion scene and B conversion scene)

A transitions the scene as shown in fig. 8.

A transition scene setting method:

the HDMI2.0 output sources of the first path and the 4 paths are respectively connected with 4 input ports of the conversion box.

And (II) selecting one path of output port of the conversion box to be connected with an 8K television HDMI2.1 input port.

And (III) setting the conversion box into a field-shaped splicing mode by the configuration interface, wherein each HDMI2.0 input port frame accounts for one part of the output field-shaped frame, the conversion box can automatically realize the synchronization of 4 paths of input signal sources, and the audio is selected according to the priority sequence of the input

physical port numbers

1, 2, 3 and 4.

B transition the scene as shown in fig. 9.

The B conversion scene setting method comprises the following steps:

and the output source of the HDMI2.1 is connected with one of the input ports of the conversion box.

And 4 output ports of the conversion box are respectively connected with 4 paths of 8K televisions in the HDMI2.0 splicing mode.

And (III) setting the conversion box into a field-shaped division mode by the configuration interface, wherein each output port frame occupies one part of the input field-shaped division mode, the conversion box can automatically realize the synchronization of 4 paths of output signal sources, and audio is synchronously broadcast at all output ports.

3. Tiled screen application, as shown in fig. 10.

The setting method comprises the following steps:

the

transpose boxes

2, 3, 4, 5 in the first figure can be used as appropriate or not at all for output port expansion.

And (II) the output source of the HDMI2.1 is connected with one of the input ports of the conversion box 1. If a plurality of input sources are provided, the input sources can also be connected with other input ports of the conversion box 1, so that multi-picture display on the spliced screen is realized.

And (III) 4 output ports on the conversion box 1 are respectively connected with the conversion box or directly connected with the spliced screen.

And (IV) respectively setting respective division modes of the

conversion boxes

1, 2, 3, 4 and 5 by the configuration interface, synchronizing output frame pictures of each conversion box, and determining a combination scheme of the conversion boxes according to the number of spliced screens, wherein 16 paths of spliced output display are realized maximally in the implementation scheme, and splicing modes such as 3 × 4, 3 × 3, 2 × 5 and 2 × 6 can be realized.

4. And monitoring in multiple pictures, as shown in FIG. 11.

The setting method comprises the following steps:

the

transpose boxes

2, 3, 4, and 5 in the above figures may be used as appropriate or may not be used at all, and are used for input port expansion.

And (II) the conversion box 1 is set to be in a 4-picture input 1-picture output mode, and the four-input picture can be a standard 'tian' -shaped picture or can be set to be in a pull-up/pull-down mode to be other non-equal pictures.

And (III) respectively setting the combination mode and the picture size/display position of the conversion box through a configuration interface according to the monitoring path number, realizing 16-path picture output display at maximum in the scheme realized by way of example, and supporting one-key full screen or restoration of a certain picture.

And (IV) each conversion box can independently set output display time sequence.

Referring to fig. 12, fig. 12 is a schematic block diagram of an apparatus 70 for implementing HDMI2.1 interface data transmission based on FPGA according to an embodiment of the present invention. Corresponding to the method for realizing the HDMI2.1 interface data transmission based on the FPGA, the invention also provides a device 70 for realizing the HDMI2.1 interface data transmission based on the FPGA. The HDMI2.1 interface data transmission device 70 based on FPGA comprises means for executing the above method for implementing HDMI2.1 interface data transmission based on FPGA, and the HDMI2.1 interface data transmission device 70 based on FPGA can be configured in an FPGA chip. Specifically, the HDMI2.1 interface data transmission device 70 implemented based on FPGA includes a receiving unit 71 and a parallel processing unit 72.

A receiving unit 71, configured to receive a video data source, where the video data source includes a plurality of data channels;

a parallel processing unit 72, configured to perform the following steps in parallel for the data in each data channel:

if the data is in an FRL format, sequentially carrying out TMDS Tri-Byte group flow, FRL group packing, FRL block and Super block combined mapping, inserting RS (Reed-Solomon) front item error correcting codes, FRL scrambling codes and coding treatment on the data; converting the bit width of the data to a bit width adapted by the transceiver, and inputting the data into the transceiver.

In one embodiment, the parallel processing unit 72 is further configured to perform the following steps in parallel:

converting a bit width of the data to a bit width adapted for the transceiver;

performing TMDS scrambling and coding processing on the data;

inputting the data into the transceiver.

In one embodiment, the parallel processing unit 72 is further configured to perform the following steps in parallel: the data is encoded by a VESA DSC encoder.

In one embodiment, the parallel processing unit 72 is further configured to perform the following steps in parallel: and carrying out HDCP2.x encryption processing on the data.

In one embodiment, the parallel processing unit 72 is further configured to perform the following steps in parallel: and if the format of the data is an FRL format, executing a data training process on the data.

It should be clearly understood by those skilled in the art that, for the specific implementation process of the HDMI2.1 interface data transmission apparatus 70 and each unit based on the FPGA, reference may be made to the corresponding description in the foregoing method embodiment, and for convenience and brevity of description, no further description is provided herein.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be merged, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, while the invention has been described with respect to the above-described embodiments, it will be understood that the invention is not limited thereto but may be embodied with various modifications and changes.

While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for realizing HDMI2.1 interface data transmission based on FPGA is characterized in that the method is applied to an FPGA chip, the FPGA chip comprises a transceiver, and the method comprises the following steps:

for the data in each data channel, executing the following steps in parallel:

if the data is in an FRL format, sequentially carrying out TMDS Tri-Byte group flow, FRL group packing, FRL block and Super block combined mapping, inserting RS (Reed-Solomon) front item error correcting codes, FRL scrambling codes and coding treatment on the data;

converting the bit width of the data to a bit width adapted by the transceiver, and inputting the data into the transceiver.

2. The method for realizing HDMI2.1 interface data transmission based on FPGA according to claim 1, further comprising:

converting a bit width of the data to a bit width adapted for the transceiver;

performing TMDS scrambling and coding processing on the data;

inputting the data into the transceiver.

3. The method of claim 2, wherein before performing TMDS Tri-Byte stream processing on the data, the method further comprises:

the data is encoded by a VESA DSC encoder.

4. The method of claim 2, wherein after performing TMDS Tri-Byte stream processing on the data, the method further comprises:

and carrying out HDCP2.x encryption processing on the data.

5. The method for realizing HDMI2.1 interface data transmission based on FPGA according to claim 1, further comprising:

6. The utility model provides a realize HDMI2.1 interface data transmission device based on FPGA, its characterized in that, realize in HDMI2.1 interface data transmission device is applied to the FPGA chip based on FPGA, the FPGA chip includes the transceiver, realize HDMI2.1 interface data transmission device based on FPGA and include:

a receiving unit for receiving a video data source, the video data source comprising a plurality of data channels;

the parallel processing unit is used for executing the following steps in parallel on the data in each data channel:

7. The device according to claim 6, wherein the parallel processing unit is further configured to execute the following steps in parallel:

converting a bit width of the data to a bit width adapted for the transceiver;

performing TMDS scrambling and coding processing on the data;

inputting the data into the transceiver.

8. A conversion box, characterized in that it comprises an FPGA chip comprising a transceiver, the FPGA chip being configured to perform the method of any one of claims 1-5.

9. The converter box of claim 8, wherein said converter box further comprises a plurality of HDMI2.1 input interfaces and a plurality of HDMI2.1 output interfaces.

10. The conversion cartridge of claim 8, wherein said conversion cartridge further comprises a configuration interface.