CN113132651A - Image processing method and device and display control system - Google Patents
Image processing method and device and display control system Download PDFInfo
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- CN113132651A CN113132651A CN202010055992.3A CN202010055992A CN113132651A CN 113132651 A CN113132651 A CN 113132651A CN 202010055992 A CN202010055992 A CN 202010055992A CN 113132651 A CN113132651 A CN 113132651A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2628—Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
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Abstract
The embodiment of the invention discloses an image processing method and device and a display control system. The image processing method comprises the following steps: receiving a first image signal transmitted from the first link, and processing an image data frame of the first image signal for output according to a field synchronization signal of the first image signal; when the first link is detected to be abnormal, switching to receiving a second image signal transmitted from the second link and freezing an image data frame cached inside before acquiring a field synchronization signal of a specified number of the second image signals; and when the field synchronizing signals of the second image signals of the designated number are acquired, processing the image data frames of the second image signals according to the field synchronizing signals of the second image signals for output. The embodiment of the invention effectively solves the problems of screen flashing, screen splash or screen blacking caused by switching the received image signals of the display screen control card.
Description
Technical Field
The present invention relates to the field of image processing technologies, and in particular, to an image processing method, an image processing apparatus, and a display control system.
Background
LED displays have been widely used in many settings for indoor meetings, outdoor advertising, and other large events. Many important scenes require that the LED display screen cannot have the problems of screen blackness, screen flickering or screen splash and the like, so that signal transmission between a plurality of display screen control cards for driving and controlling the LED display screen and a display controller must be stable.
At present, it is generally adopted that a display controller cascades a plurality of display screen control cards through a first link (also called a main loop) and a second link (also called a backup loop), and the display controller and the cascaded display screen control cards form a loop through the first link and the second link; the plurality of display screen control cards receive first image signals transmitted by the first link, and when a part of the plurality of display screen control cards cannot receive the first image signals due to the abnormality of the first link, the part of the plurality of display screen control cards are switched to receive second image signals transmitted by the second link. However, during the switching process, the problems of black screen, splash screen or splash screen still occur.
Disclosure of Invention
To overcome the defects and shortcomings in the prior art, embodiments of the present invention provide an image processing method, an image processing apparatus, and a display control system.
In one aspect, an embodiment of the present invention provides an image processing method, which operates in a first state to receive a first image signal transmitted from a first link; writing frames of image data included in the first image signal into different storage areas in a frame-alternating manner according to a field sync signal included in the first image signal; reading frames of image data from the different storage areas in a frame-alternating manner for processing for output under control of a field sync signal included in the first image signal; in response to detecting the first link is abnormal, switching the first state to a second state to receive a second image signal transmitted from a second link different from the first link, and controlling to write a frame of image data included in the second image signal into a designated storage area before a designated number of field synchronization signals included in the second image signal are acquired, the designated storage area being one of the different storage areas; and in response to acquisition of a specified number of the field sync signals included in the second image signal, processing to write frames of image data included in the second image signal in the different storage area in a frame-alternate manner in accordance with the field sync signals included in the second image signal, and to read frames of image data from the different storage area in the alternate manner for output under control of the field sync signals included in the second image signal.
In this embodiment, when the first link is detected to be abnormal, the switching is performed to receive the second image signal transmitted by the second link, and the writing operation of the image data frame in a frame alternating manner is stopped, and the image data frame is written into the designated storage area in the different storage areas, so that the complete image data frame can be always received in the switching process for processing and outputting, and thus the problem of screen flashing, black screen or screen splash caused by the incompleteness of the image data frame in the switching process of the display screen control card is solved.
In a specific embodiment of the present invention, the image processing method further includes: counting the length of the image data frame contained in the first image signal written in the different storage areas in a frame-alternating manner to obtain a count value; and in response to the detection that the first link is abnormal and the count value exceeds a preset time length relative to a field frequency single frame period corresponding to a field synchronization signal contained in the first image signal, generating the field synchronization signal, and reading the image data frames from the different storage areas in a frame alternating mode under the control of the generated field synchronization signal and processing the image data frames for output.
In a specific embodiment of the present invention, the field sync signal is generated before receiving the second image signal.
In a specific embodiment of the present invention, the different storage areas include a first storage area and a second storage area, and writing frames of image data included in the first image signal into the different storage areas in an alternating manner according to a field sync signal included in the first image signal includes: switching a value of a storage flag bit to a first value according to the field sync signal included in the first image signal, and writing the image data frame included in the first image signal into the first storage area; switching the value of the storage flag bit to a second value according to the field synchronization signal included in the first image signal, and writing the image data frame included in the first image signal into the second storage area; the controlling of writing the frame of image data included in the second image signal into a designated storage area before acquiring a designated number of field sync signals included in the second image signal includes: stopping switching the value of the storage flag bit before acquiring a specified number of field synchronization signals contained in the second image signal; and controlling writing of the frame of image data included in the second image signal into the designated storage area corresponding to the storage flag bit, the designated storage area being one of the first storage area and the second storage area.
On the other hand, an image scaling processing apparatus provided by an embodiment of the present invention includes: the device comprises a receiving module, an image processing module and a writing control module; the receiving module is used for working in a first state to receive a first image signal transmitted from a first link; the writing control module is used for writing the image data frames contained in the first image signal into different storage areas in a frame alternating mode according to the field synchronization signal contained in the first image signal; the image processing module is used for processing the image data frames read from the different storage areas in a frame alternating mode under the control of a field synchronization signal contained in the first image signal for outputting; the receiving module is further configured to switch the first state to a second state to receive a second image signal transmitted from a second link different from the first link in response to detecting that the first link is abnormal; the writing control module is further configured to control writing of the image signals included in the first image signal into a designated storage area before a designated number of field synchronization signals included in the second image signal are acquired, where the designated storage area is one of the different storage areas; the write control module is further configured to, in response to acquiring a specified number of the field synchronization signals included in the second image signal, write frames of image data included in the second image signal into the different storage areas in a frame-alternating manner according to the field synchronization signals included in the second image signal; the image processing module is further used for processing the image data frames read from the different storage areas in an alternating mode for output under the control of a field synchronization signal contained in the second image signal.
In this embodiment, when the receiving module switches to receive the second image signal through the second link, the writing operation of the image data frame in an alternating manner is suspended, and the image data frame is written into the designated storage area, so that a complete image data frame can be received all the time in the switching process for processing and outputting, thereby solving the problem of screen flashing, screen blacking or screen splash caused by the incomplete image data frame in the switching process of the display screen control card.
In a specific embodiment of the present invention, the image processing apparatus further includes: a counting module for counting the length of the image data frame contained in the first image signal written in the different storage areas in a frame-alternating manner to obtain a count value; the receiving module is further configured to locally generate a field synchronization signal in response to that the first link is detected to be abnormal and the count value exceeds a preset time duration relative to a field frequency single frame period corresponding to a field synchronization signal included in the first image signal; the image processing module is further configured to read the image data frames from the different storage areas in a frame-alternating manner under control of the locally generated field sync signal and process the image data frames for output.
In a specific embodiment of the present invention, the receiving module generates the field sync signal before receiving the second image signal.
In a specific embodiment of the present invention, the different storage areas include a first storage area and a second storage area; the write control module is specifically configured to: switching a value of a storage flag bit to a first value according to the field sync signal included in the first image signal to write the image data frame included in the first image signal into the first storage area; switching the value of the storage flag bit to a second value according to the field sync signal included in the first image signal, so as to write the image data frame included in the first image signal into the second storage area; the write control module is specifically configured to stop switching the value of the storage flag before acquiring a specified number of field synchronization signals included in the second image signal; controlling writing of a frame of image data included in the second image signal into the designated storage area corresponding to the storage flag bit, the designated storage area being one of the first storage area and the second storage area.
In another aspect, an embodiment of the present invention provides a display control system, including: a display controller having a master control interface and a backup interface; the display screen control cards are electrically connected between the main control interface and the backup interface in a cascading mode, and each display screen control card is provided with a first image signal interface and a second image signal interface; wherein any one of the plurality of display screen control cards is configured to execute the image processing method according to any one of the above embodiments, and the first image signal interface of the display screen control card is electrically connected to the main control interface to form the first link, and the second image signal interface of the display screen control card is electrically connected to the backup interface to form the second link.
In a specific embodiment of the present invention, the display screen control card includes a programmable logic device electrically connected to the first image signal interface and the second image signal interface, and the programmable logic device is configured to execute the image processing method; and the first image signal interface and the second image signal interface are respectively Ethernet interfaces.
In summary, the above embodiments of the present invention may have the following advantages or beneficial effects: when the first link is detected to be abnormal, the writing operation of the image data frame in a frame alternation mode is paused, and the image data frame is written into the designated storage area, so that the complete image data frame can be rewritten in the designated storage area in which the incomplete image data frame is written, the complete image data frame is processed and output, and the problem of screen flashing, screen splash or screen blacking of the display screen control card is solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flowchart illustrating an image processing method according to a first embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a display control system according to an embodiment of the present invention.
Fig. 3 is a schematic block diagram of the display control card in fig. 2.
Fig. 4 is a schematic diagram of image signal transmission when a master image signal transmission failure occurs in the display control system shown in fig. 2.
Fig. 5 is a schematic diagram illustrating the structures of the image data frame and the field sync signal of the main control image signal in fig. 2.
FIG. 6 is a diagram illustrating a situation where a master video signal fails when receiving a video data frame of the master video signal according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating a failure of a master video signal when receiving a field sync signal of the master video signal according to an embodiment of the present invention.
Fig. 8 is a schematic structural diagram of an image processing system according to a second embodiment of the present invention.
Fig. 9 is a schematic structural diagram of a computer storage medium according to a third embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
[ first embodiment ] A method for manufacturing a semiconductor device
Referring to fig. 1, it is a schematic flow chart of an image processing method according to a first embodiment of the present invention, where the image processing method includes:
step S10, operating in a first state to receive the first image signal transmitted from the first link;
a step S30 of writing frames of image data included in the first image signal into different storage areas in a frame-alternating manner in accordance with a field sync signal included in the first image signal;
a step S50 of reading frames of image data from the different storage areas in a frame-alternating manner under control of a field sync signal included in the first image signal for processing for output;
a step S70, in response to detecting the first link is abnormal, of switching the first state to a second state to receive a second image signal transmitted from a second link different from the first link, and controlling to write a frame of image data included in the second image signal into a designated storage area before acquiring a designated number of field synchronization signals included in the second image signal, the designated storage area being one of the different storage areas; and
step S90, in response to acquiring a specified number of the field sync signals included in the second image signal, writing frames of image data included in the second image signal into the different storage areas in a frame-alternate manner in accordance with the field sync signals included in the second image signal, and processing frames of image data read from the different storage areas in an alternate manner for output under control of the field sync signals included in the second image signal. Further, the different storage areas include, for example, a first storage area and a second storage area, and the step S10 includes, for example: switching a value of a storage flag bit to a first value according to the field sync signal included in the first image signal, and writing the image data frame included in the first image signal into the first storage area; and switching the value of the storage flag bit to a second value according to the field synchronization signal contained in the first image signal, and writing the image data frame contained in the first image signal into the second storage area.
Further, the controlling, before the acquiring of the field synchronization signals included in the second image signal in the specified number, the writing of the image data frame included in the second image signal into the specified storage area in step 70 specifically includes: stopping switching the value of the storage flag bit before acquiring a specified number of field synchronization signals contained in the second image signal; and controlling writing of the frame of image data included in the second image signal into the designated storage area corresponding to the storage flag bit, the designated storage area being one of the first storage area and the second storage area. For example, when the first link is detected to be abnormal, if the value of the storage flag bit is the first value, it indicates that the image data frame included in the first image signal is currently written into the first storage area, at this time, switching of the value of the storage flag bit is stopped, so that the storage flag bit is always the first value, and the image data frame included in the second image signal is written into the first storage area.
In this embodiment, in practical implementation, the specified storage area refers to a storage area in which the image data frame is being stored when the first link is abnormal. For example, the image data frame is stored in a first storage area (which is the designated storage area) under control of a field sync signal included in a first image signal, and in response to detection of the first link abnormality, switching is made to receive a second image signal transmitted by a second link, and the image data frame included in the second image signal is controlled to be written in the first storage area before a designated number of field sync signals included in the second image signal are acquired.
Further, the image processing method, for example, further includes: counting the length of the image data frame contained in the first image signal written in the different storage areas in a frame-alternating manner to obtain a count value; and in response to the detection that the first link is abnormal and the count value exceeds a preset time length relative to a field frequency single frame period corresponding to a field synchronization signal contained in the first image signal, generating the field synchronization signal, and reading the image data frames from the different storage areas in a frame alternating mode under the control of the generated field synchronization signal and processing the image data frames for output. Wherein the field sync signal is generated, for example, before receiving the second image signal.
For the sake of better understanding of the present embodiment, the following describes the process of the image processing method in detail with reference to fig. 2 to 5.
Referring to fig. 2, which is a schematic structural diagram of a display control system according to an embodiment of the present invention, the display control system 100 includes: a display controller 110 and a plurality of display screen control cards 120.
The display controller 110 includes, for example, a master interface 111 and a backup interface 112, and the master interface 111 and the backup interface 112 are data transmission interfaces, for example, ethernet interfaces.
Each display control card 120 includes, for example, a first image signal interface 121, a second image signal interface 122, and a Programmable logic device (not shown in the figure) electrically connected between the first image signal interface 121 and the second image signal interface 122, where the first image signal interface 121 and the second image signal interface 122 are data transmission interfaces, for example, ethernet interfaces, the Programmable logic device is, for example, an FPGA (Field Programmable Gate Array) device, and the display control card 120 further includes, for example, at least one memory electrically connected to the Programmable logic device; the plurality of display screen control cards 120 are cascaded between the main control interface 111 and the backup interface 112 of the display controller 110.
Specifically, the first image signal interface 121 of each display control card 120 is electrically connected to the main control interface 111 of the display controller 110, and each display control card 120 receives a main control image signal (also called a first image signal) transmitted by the main control interface 111 through the display controller 110 through the first image signal interface 121, which is a first link; the second image signal interface 122 of each display control card 120 is electrically connected to the backup interface 112 of the display controller 110, and each display control card 120 receives a backup image signal (also called a second image signal) transmitted by the display controller 110 through the backup interface 112 through the second image signal interface 122, which is a second link; and the first link and the second link form a loop, which is not described herein again.
In a specific embodiment, a computer sends a video image to a display controller 110 through a DVI video source, and interacts a command with the display controller 110 through a serial port or a USB interface, the display controller 110 sends a main control image signal to a first display screen control card 120 through a main control interface 111, the first display screen control card 120 forwards a received image signal to a next display screen control card 120 until a last display screen control card 120, which transmits the main control image signal (also referred to as a first image signal) for the first link; meanwhile, the display controller 110 inputs the backup image signal to the last display control card 120 until the first display control card 120, which is the second link for transmitting the backup image signal (also called as the second image signal).
Referring to fig. 3, which is a block diagram of the image processing apparatus 120, the image processing apparatus 120 includes, for example, a receiving module 123, a writing control module 124, and an image processing module 125; wherein the receiving module 123, the writing control module 124 and the image processing module 125 are, for example, software modules integrated in the programmable logic device; the receiving module 123, the writing control module 124 and the image processing module 125 are configured to perform steps S10, S30, S50, S70 and S90 of the image processing method, which is not described herein again.
In one embodiment, the image processing apparatus 120 further includes a driving control module 126, for example, wherein the image processing module 125 is further configured to buffer the processed image data frames into a third storage area and a fourth storage area in a frame-alternating manner according to a field synchronization signal included in the master image signal (or the backup image signal), and the driving control module 126 is configured to drive and output the processed image data frames buffered in the third storage area and the fourth storage area in a frame-alternating manner according to a field synchronization signal included in the master image signal (or the backup image signal); the driving control module 126 is, for example, a software module integrated in the programmable logic device, and is not described herein again.
The display controller 110 sends a main control image signal through the main control interface 111 and sends a backup image signal through the backup interface 112 to each display screen control card 120 respectively; the plurality of display screen control cards 120 respectively execute the image processing method described above to realize that the plurality of display screen control cards 120 respectively receive the main control image signal through the respective first image signal interfaces 121 and respectively output the drive control signal according to the main control image signal to perform image display, for example, each display screen control card 120 is connected with one display box, and the display boxes respectively connected to the plurality of display screen control cards 120 are built into a tiled display screen, so that the plurality of display screen control cards 120 respectively output the drive control signal to carry the display boxes respectively connected to each display screen to perform image display, and finally the tiled display screen performs image display; when the master image signal transmitted by the first link fails (see fig. 4), the display control card 120 that fails to receive the master image signal through the first image signal interface 121 is switched to receive the backup image signal through the second image signal interface 122, so that the display control card 120 before the failure location receives the master image signal and the display control card 120 after the failure location receives the backup image signal; when the failure of the first transmission link is recovered, the display screen control cards 120 after the failure location are switched to receive the master image signal through the first image signal interfaces 121, so that the plurality of display screen control cards 120 respectively receive the master image signal through the respective first image signal interfaces 121.
Specifically, the receiving module 123 of the display screen control card 120 receives a main control image signal (see fig. 5) through the first image signal interface 121, the write control module 124 switches the value of the storage flag bit to 0 (the first value) according to the first field synchronization signal, and the receiving module 123 writes the received first image data frame into the first storage area; the write control module 124 switches the value of the storage flag bit to 1 (the second value) according to a second field synchronization signal, the receiving module 123 writes the received second image data frame into the second storage region, the image processing module 125 reads and processes the first image data frame cached in the first storage region, and then writes the processed first image data frame into the third storage region; the write control module 124 switches the value of the storage flag bit to 0 according to a third field synchronization signal, the receiving module 123 writes the received third image data frame into the first storage region, the image processing module 125 reads and processes the second image data frame cached in the second storage region, and then writes the processed second image data frame into the fourth storage region, and the drive control module 126 reads the processed first image data frame cached in the third storage region and drives and controls the LED display module in the tiled display screen correspondingly connected to the display screen control card 120 to display the processed first image data frame; it should be noted that the embodiments of the present invention are not limited thereto.
In response to detecting the abnormality of the first image signal interface 121, that is, the abnormality of the first link, the following two situations are included in the case that the receiving module 123 of the display screen control card 120 cannot receive the master image signal through the first image signal interface 121.
In case one, referring to fig. 6, the receiving module 123 writes the received third image data frame into the first storage area, the write control module 124 switches the storage flag bit to 1 according to the fourth field synchronization signal, the receiving module 123 writes the received fourth image data frame into the second storage area, in response to detecting the failure of the first image signal interface, at this time, a part of image data of the fourth image data frame has been written into the second storage area, the receiving module 123 switches to receive the backup image signal transmitted from the second image signal interface 122 (part of image data is lost during this switching process), continues to write the image data of the backup image signal received by the receiving module 123 into the second storage area, and when the first field synchronization signal of the backup image signal is acquired, the write control module 124 does not switch the value of the storage flag bit, making the value of the storage flag bit continue to be 1, the receiving module 123 completely writes the image data frame after the first field synchronization signal in the received backup image signal into the second storage area, waits for a field synchronization signal (may also wait for a plurality of field synchronization signals), and then the write control module 124 switches the value of the storage flag bit to 0 when obtaining the next field synchronization signal of the backup image signal, and the rest of the processes are the same as the processes of the write control module 124 switching the value of the storage flag bit according to the field synchronization signal of the main control image signal, and are not described herein again; it should be noted that the embodiments of the present invention are not limited thereto.
In case two, referring to fig. 7, after the receiving module 123 writes the received third image data frame into the first storage area, a counting module (not shown in the figure, which may also be a software module of the programmable logic device) of the display screen control card 120 counts the length of the third image data frame written in the first storage area to obtain a length value of the third image data frame buffered in the first storage area, obtaining the field frequency single frame period of the field synchronizing signal of the corresponding main control image signal according to the length value, and when the field frequency single frame period is longer than a preset duration (for example, the current field frequency single frame period), that is, after the display screen control card 120 completely writes the third image data frame into the first storage area, the display screen control card 120 detects an interface fault of the first image signal when receiving the fourth field synchronization signal of the first image signal; in response to detecting the failure of the first image signal interface, at this time, the receiving module 123 locally generates a field sync signal, and then switches to receive the backup image signal transmitted from the second image signal interface 122 (the field sync signal is lost in the switching process), so that the image processing module 125 reads the third image data frame from the first storage area, the write control module 124 switches the value of the storage flag according to the field sync signal, and the remaining processes are the same as the processes of the write control module 124 switching the value of the storage flag according to the field sync signal of the main control image signal, and are not described herein again; it should be noted that the embodiments of the present invention are not limited thereto.
In response to detecting that the first image signal interface transmits the main control image signal, that is, the first image signal interface is restored, the display screen control card 120 switches the receiving module 123 to receive the main control image signal transmitted by the first image signal interface, which is similar to the process of switching the receiving module 123 to receive the backup image signal transmitted by the second image signal interface in the above two situations, and details are not repeated here.
[ second embodiment ]
Referring to fig. 8, which is a schematic structural diagram of an image processing system according to a third embodiment of the present invention, the image processing system 400 includes, for example, a processor 430 and a memory 410 electrically connected to the processor 430, the memory 410 stores a computer program 411, and the processor 430 loads the computer program 411 to implement the image processing method according to the first embodiment.
[ third embodiment ]
Referring to fig. 9, which is a schematic structural diagram of a computer-readable storage medium according to a third embodiment of the present invention, the computer-readable storage medium 500 is, for example, a non-volatile memory, and is, for example: magnetic media (e.g., hard disks, floppy disks, and magnetic tape), optical media (e.g., CDROM disks and DVDs), magneto-optical media (e.g., optical disks), and hardware devices specially constructed for storing and executing computer-executable instructions (e.g., Read Only Memories (ROMs), Random Access Memories (RAMs), flash memories, etc.). The computer-readable storage medium 500 has stored thereon computer-executable instructions 510. The computer-readable storage medium 500 may execute the computer-executable instructions 510 by one or more processors or processing devices to implement the image processing method as described in the first embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of one logic function, and an actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may also be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An image processing method, comprising:
the first link is operated in a first state to receive a first image signal transmitted from the first link;
writing frames of image data included in the first image signal into different storage areas in a frame-alternating manner according to a field sync signal included in the first image signal;
reading frames of image data from the different storage areas in a frame-alternating manner for processing for output under control of a field sync signal included in the first image signal;
in response to detecting the first link is abnormal, switching the first state to a second state to receive a second image signal transmitted from a second link different from the first link, and controlling to write a frame of image data included in the second image signal into a designated storage area before a designated number of field synchronization signals included in the second image signal are acquired, the designated storage area being one of the different storage areas; and
in response to acquisition of a specified number of the field sync signals included in the second image signal, writing frames of image data included in the second image signal into the different storage areas in a frame-alternate manner in accordance with the field sync signals included in the second image signal, and processing reading frames of image data from the different storage areas in an alternate manner for output under control of the field sync signals included in the second image signal.
2. The image processing method according to claim 1, further comprising:
counting the length of the image data frame contained in the first image signal written in the different storage areas in a frame-alternating manner to obtain a count value;
and in response to the detection that the first link is abnormal and the count value exceeds a preset time length relative to a field frequency single frame period corresponding to a field synchronization signal contained in the first image signal, generating the field synchronization signal, and reading the image data frames from the different storage areas in a frame alternating mode under the control of the generated field synchronization signal and processing the image data frames for output.
3. The image processing method according to claim 2, wherein the field sync signal is generated before the second image signal is received.
4. The image processing method according to claim 1, wherein the different storage areas include a first storage area and a second storage area,
writing frames of image data included in the first image signal into different storage areas in an alternating manner according to a field sync signal included in the first image signal, including:
switching a value of a storage flag bit to a first value according to the field sync signal included in the first image signal, and writing the image data frame included in the first image signal into the first storage area;
switching the value of the storage flag bit to a second value according to the field synchronization signal included in the first image signal, and writing the image data frame included in the first image signal into the second storage area;
the controlling of writing the frame of image data included in the second image signal into a designated storage area before acquiring a designated number of field sync signals included in the second image signal includes:
stopping switching the value of the storage flag bit before acquiring a specified number of field synchronization signals contained in the second image signal;
and controlling writing of the frame of image data included in the second image signal into the designated storage area corresponding to the storage flag bit, the designated storage area being one of the first storage area and the second storage area.
5. An image processing apparatus characterized by comprising: the device comprises a receiving module, an image processing module and a writing control module;
the receiving module is used for working in a first state to receive a first image signal transmitted from a first link;
the writing control module is used for writing the image data frames contained in the first image signal into different storage areas in a frame alternating mode according to the field synchronization signal contained in the first image signal;
the image processing module is used for processing the image data frames read from the different storage areas in a frame alternating mode under the control of a field synchronization signal contained in the first image signal for outputting;
the receiving module is further configured to switch the first state to a second state to receive a second image signal transmitted from a second link different from the first link in response to detecting that the first link is abnormal;
the writing control module is further configured to control writing of the image signals included in the first image signal into a designated storage area before a designated number of field synchronization signals included in the second image signal are acquired, where the designated storage area is one of the different storage areas;
the write control module is further configured to, in response to acquiring a specified number of the field synchronization signals included in the second image signal, write frames of image data included in the second image signal into the different storage areas in a frame-alternating manner according to the field synchronization signals included in the second image signal;
the image processing module is further used for processing the image data frames read from the different storage areas in an alternating mode for output under the control of a field synchronization signal contained in the second image signal.
6. The image processing apparatus according to claim 5, further comprising: a counting module for counting the length of the image data frame contained in the first image signal written in the different storage areas in a frame-alternating manner to obtain a count value;
the receiving module is further configured to locally generate a field synchronization signal in response to that the first link is detected to be abnormal and the count value exceeds a preset time duration relative to a field frequency single frame period corresponding to a field synchronization signal included in the first image signal;
the image processing module is further configured to read the image data frames from the different storage areas in a frame-alternating manner under control of the locally generated field sync signal and process the image data frames for output.
7. The image processing apparatus according to claim 6, wherein said receiving module generates the field sync signal before receiving the second image signal.
8. The apparatus according to claim 5, wherein the different storage areas include a first storage area and a second storage area;
the write control module is specifically configured to:
switching a value of a storage flag bit to a first value according to the field sync signal included in the first image signal to write the image data frame included in the first image signal into the first storage area;
switching the value of the storage flag bit to a second value according to the field sync signal included in the first image signal, so as to write the image data frame included in the first image signal into the second storage area;
the write control module is specifically configured to stop switching the value of the storage flag before acquiring a specified number of field synchronization signals included in the second image signal; controlling writing of a frame of image data included in the second image signal into the designated storage area corresponding to the storage flag bit, the designated storage area being one of the first storage area and the second storage area.
9. A display control system, comprising:
a display controller having a master control interface and a backup interface;
the display screen control cards are electrically connected between the main control interface and the backup interface in a cascading mode, and each display screen control card is provided with a first image signal interface and a second image signal interface;
wherein any one of the plurality of display screen control cards is used to execute the image processing method according to any one of claims 1 to 4, and the first image signal interface of the display screen control card is electrically connected to the main control interface to form the first link and the second image signal interface of the display screen control card is electrically connected to the backup interface to form the second link.
10. The display control system of claim 9, wherein the display screen control card comprises a programmable logic device electrically connecting the first image signal interface and the second image signal interface, and the programmable logic device is configured to perform the image processing method; and the first image signal interface and the second image signal interface are respectively Ethernet interfaces.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114390155A (en) * | 2021-12-28 | 2022-04-22 | 北京德为智慧科技有限公司 | Signal backup display method and device, electronic equipment and storage medium |
| CN114443373A (en) * | 2021-08-20 | 2022-05-06 | 荣耀终端有限公司 | an electronic device |
| CN115550642A (en) * | 2022-11-30 | 2022-12-30 | 湖北芯擎科技有限公司 | Multimedia link debugging method, system, equipment and medium of simulation platform |
| CN116246572A (en) * | 2023-03-07 | 2023-06-09 | 浙江方泰显示技术有限公司 | Multi-signal redundancy multifunctional display screen control system |
| CN118113247A (en) * | 2024-04-29 | 2024-05-31 | 北京芯驰半导体科技股份有限公司 | Display control method, multi-core heterogeneous system, chip and vehicle |
| WO2024198550A1 (en) * | 2023-03-24 | 2024-10-03 | 海信视像科技股份有限公司 | Image display method and display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6335728B1 (en) * | 1998-03-31 | 2002-01-01 | Pioneer Corporation | Display panel driving apparatus |
| US20020033899A1 (en) * | 1997-07-09 | 2002-03-21 | Tadashi Oguma | Multi-screen display appartus and video switching processing apparatus |
| US6469746B1 (en) * | 1992-12-28 | 2002-10-22 | Sanyo Electric Co., Ltd. | Multi-vision screen adapter |
| CN1747529A (en) * | 2004-09-10 | 2006-03-15 | 佳能株式会社 | Data processing device and control method thereof |
| CN101777036A (en) * | 2009-01-09 | 2010-07-14 | 比亚迪股份有限公司 | Device, USB equipment and method for realizing drive-free image data transmission |
| CN102768819A (en) * | 2012-07-17 | 2012-11-07 | 中国兵器工业集团第二一四研究所苏州研发中心 | OLED (organic light emitting diode) real-time display driving control system and control method thereof |
| CN110460784A (en) * | 2019-08-19 | 2019-11-15 | 京东方科技集团股份有限公司 | The switching method and module of display channel, display drive apparatus, display equipment |
-
2020
- 2020-01-15 CN CN202010055992.3A patent/CN113132651B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6469746B1 (en) * | 1992-12-28 | 2002-10-22 | Sanyo Electric Co., Ltd. | Multi-vision screen adapter |
| US20020033899A1 (en) * | 1997-07-09 | 2002-03-21 | Tadashi Oguma | Multi-screen display appartus and video switching processing apparatus |
| US6335728B1 (en) * | 1998-03-31 | 2002-01-01 | Pioneer Corporation | Display panel driving apparatus |
| CN1747529A (en) * | 2004-09-10 | 2006-03-15 | 佳能株式会社 | Data processing device and control method thereof |
| CN101777036A (en) * | 2009-01-09 | 2010-07-14 | 比亚迪股份有限公司 | Device, USB equipment and method for realizing drive-free image data transmission |
| CN102768819A (en) * | 2012-07-17 | 2012-11-07 | 中国兵器工业集团第二一四研究所苏州研发中心 | OLED (organic light emitting diode) real-time display driving control system and control method thereof |
| CN110460784A (en) * | 2019-08-19 | 2019-11-15 | 京东方科技集团股份有限公司 | The switching method and module of display channel, display drive apparatus, display equipment |
Non-Patent Citations (2)
| Title |
|---|
| NAVEED AHMED; ASHFAQ AMJAD KHAN: "《An efficient image buffering and tiling algorithm for multiple channel image acquisition for space missions》", 《2013 INTERNATIONAL CONFERENCE ON AEROSPACE SCIENCE & ENGINEERING (ICASE)》 * |
| 王水鱼等: "基于FPGA的ITU-656标准视频解码及存储系统设计", 《微型机与应用》 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114443373A (en) * | 2021-08-20 | 2022-05-06 | 荣耀终端有限公司 | an electronic device |
| CN114443373B (en) * | 2021-08-20 | 2023-02-03 | 荣耀终端有限公司 | an electronic device |
| CN114390155A (en) * | 2021-12-28 | 2022-04-22 | 北京德为智慧科技有限公司 | Signal backup display method and device, electronic equipment and storage medium |
| CN114390155B (en) * | 2021-12-28 | 2023-08-29 | 北京德为智慧科技有限公司 | Method, device, electronic equipment and storage medium for signal backup display |
| CN115550642A (en) * | 2022-11-30 | 2022-12-30 | 湖北芯擎科技有限公司 | Multimedia link debugging method, system, equipment and medium of simulation platform |
| CN116246572A (en) * | 2023-03-07 | 2023-06-09 | 浙江方泰显示技术有限公司 | Multi-signal redundancy multifunctional display screen control system |
| CN116246572B (en) * | 2023-03-07 | 2023-09-26 | 浙江方泰显示技术有限公司 | Multi-signal redundancy multifunctional display screen control system |
| WO2024198550A1 (en) * | 2023-03-24 | 2024-10-03 | 海信视像科技股份有限公司 | Image display method and display device |
| CN118113247A (en) * | 2024-04-29 | 2024-05-31 | 北京芯驰半导体科技股份有限公司 | Display control method, multi-core heterogeneous system, chip and vehicle |
| CN118113247B (en) * | 2024-04-29 | 2024-08-02 | 北京芯驰半导体科技股份有限公司 | Display control method, multi-core heterogeneous system, chip and vehicle |
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