CN113131933B - Continuous approximate register analog-to-digital converter with correction function and correction method - Google Patents

Abstract

A continuous approximation register analog-to-digital converter with correction function and a correction method thereof are provided. The continuous approximation register analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller. The at least one capacitive digital-to-analog converter includes Nd capacitors corresponding to Nd bits, where Nd is a positive integer. The correction method comprises the following steps: coupling the capacitors from the i-th bit to the (Nd-1) -th bit to a first reference voltage, and generating a first digital code according to the operation of the capacitors from the (i-1) -th bit to the 0-th bit, wherein i is an integer smaller than Nd; coupling the (i+1) th to (Nd-1) th capacitors to the first reference voltage, coupling the i th capacitor to the second reference voltage, and generating a second digital code according to the operation of the (i-1) th to 0 th capacitors; generating a capacitance weight of a capacitor of the ith bit according to the first digital code and the second digital code; and correcting the successive approximation register analog-to-digital converter according to the capacitance weight of the capacitor of the ith bit.

Description

Continuous approximate register analog-to-digital converter with correction function and correction method

Technical Field

The present disclosure relates to a calibration method for an analog-to-digital converter, and more particularly to a calibration method for a successive approximation register analog-to-digital converter and a circuit thereof.

Background Art

The performance of the analog-to-digital converter may affect the accuracy of the instrument measurement, so the linearity of the analog-to-digital converter will be required in this application. The wafer foundry provides the mismatch parameters of all devices under each process. In the Successive Approximation Register Analog-to-Digital Converter (SAR ADC), the Capacitor Digital to Analog Converter (CDAC) affects the overall linearity. How to achieve a certain linearity without over-amplifying the unit capacitance of the capacitor digital to analog converter is one of the issues that this technical field wants to solve.

Summary of the invention

According to an embodiment of the present disclosure, a calibration method for a continuous approximate register analog-to-digital converter is provided. The continuous approximate register analog-to-digital converter includes at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter includes Nd capacitors corresponding to Nd bits, where Nd is a positive integer. The capacitance correction method of the continuous approximate register analog-to-digital converter includes: coupling the capacitors from the zth to (Nd-1)th bits to a first reference voltage, generating a first digital code according to the operation of the capacitors from the (z-1)th to the 0th bits, wherein z is an integer less than Nd; coupling the capacitors from the (i+1)th to the (Nd-1)th bits to the first reference voltage, coupling the capacitors from the ith bit to a second reference voltage, generating a second digital code according to the operation of the capacitors from the (i-1)th to the 0th bits, wherein i is an integer less than Nd, and z is less than i; generating a capacitance weight of the capacitor at the ith bit according to the first digital code and the second digital code; and calibrating the continuous approximate register analog-to-digital converter according to the capacitance weight of the capacitor at the ith bit.

According to one embodiment, the present disclosure provides a calibration method for a continuous approximate register analog-to-digital converter, wherein the continuous approximate register analog-to-digital converter includes at least one capacitive digital-to-analog converter and a controller. The at least one capacitive digital-to-analog converter includes Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer. The capacitance calibration method for the continuous approximate register analog-to-digital converter includes: coupling the capacitors from the i-th to (Nd-1)-th bits to a first reference voltage, generating a first digital code according to the operation of the capacitors from the (i-1)-th to the 0-th bits, wherein i is an integer less than Nd; coupling the capacitors from the (i+1)-th to (Nd-1)-th bits to the first reference voltage, coupling the capacitors from the i-th bit to a second reference voltage, generating a second digital code according to the operation of the capacitors from the (i-1)-th to the 0-th bits; generating a capacitance weight of the capacitor from the i-th bit according to the first digital code and the second digital code; and calibrating the continuous approximate register analog-to-digital converter according to the capacitance weight of the capacitor from the i-th bit.

According to another embodiment, the present disclosure provides a continuous approximate register analog-to-digital converter with a calibration function, which includes: at least one capacitive digital-to-analog converter, which is controlled by a plurality of control signals to respectively control the switching operation of Nd switching capacitors of the at least one capacitive digital-to-analog converter, wherein Nd is a positive integer; a comparator, coupled to the at least one capacitive digital-to-analog converter, for comparing the output of the at least one capacitive digital-to-analog converter with a comparison voltage; and a controller, coupled to the comparator and the at least one capacitive digital-to-analog converter, for generating a control signal and a digital output signal according to the output of the comparator. When the controller is in a calibration mode, the capacitance weight of the i-th bit of the at least one capacitive digital-to-analog converter is obtained by the result of the (Nd+1)th operation of the comparator, wherein i is an integer less than Nd.

According to another embodiment of the present disclosure, a continuous approximate buffer analog-to-digital converter with a correction function is provided, comprising: at least one Nd-bit capacitive digital-to-analog converter having Nd-bit capacitance, where Nd is a positive integer; and a controller coupled to the at least one capacitive digital-to-analog converter. The controller is used to perform the following capacitor correction procedure: coupling the capacitors from the zth to (Nd-1)th bits to a first reference voltage, generating a first digital code based on the operation of the capacitors from the (z-1)th to the 0th bits, wherein z is an integer less than Nd; coupling the capacitors from the (i+1)th to the (Nd-1)th bits to the first reference voltage, coupling the capacitors from the i-th bit to a second reference voltage, generating a second digital code based on the operation of the capacitors from the (i-1)th to the 0th bits, wherein i is an integer less than Nd, and z is less than i; generating a capacitance weight of the capacitor at the i-th bit based on the first digital code and the second digital code; and calibrating the continuous approximate register analog-to-digital converter based on the capacitance weight of the capacitor at the i-th bit.

According to another embodiment, the present invention discloses a continuous approximate register analog-to-digital converter with a correction function, comprising: at least one Nd-bit capacitive digital-to-analog converter having Nd-bit capacitors; a controller coupled to the output of the comparator and at least one capacitive digital-to-analog converter. The controller performs the following capacitor correction procedure: coupling the capacitors from the i-th to (Nd-1)-th bits to a first reference voltage, generating a first digital code according to the operation of the capacitors from the (i-1)-th to the 0-th bits, wherein i is an integer less than Nd; coupling the capacitors from the (i+1)-th to the (Nd-1)-th bits to the first reference voltage, coupling the capacitor from the i-th bit to a second reference voltage, generating a second digital code according to the operation of the capacitors from the (i-1)-th to the 0-th bits; generating a capacitance weight of the capacitor from the i-th bit according to the first digital code and the second digital code; and calibrating the continuous approximate register analog-to-digital converter according to the capacitance weight of the capacitor from the i-th bit.

Based on the above, the present disclosure combines the advantages of window switching without adding other circuits to the signal path to affect the information of the corrected comparator offset and flicker noise. In addition, the present disclosure can also improve the capacitance weight deviation accumulated due to the correction to further improve the integral nonlinearity of the capacitive digital-to-analog converter.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

FIG. 1 is a circuit block diagram of a successive approximation register analog-to-digital converter according to an embodiment of the disclosure.

FIG. 2 is a schematic diagram of a switching mechanism of a single-ended input successive approximation register analog-to-digital converter according to an embodiment of the disclosure.

FIG. 3 is a circuit block diagram of a successive approximation register analog-to-digital converter according to another embodiment of the disclosure.

FIG. 4 is a schematic diagram showing a switching mechanism of a differential input SAR analog-to-digital converter according to another embodiment of the disclosure.

FIG. 5 is a timing diagram of calibration according to an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of correction of flicker noise and offset of a comparator according to an embodiment of the present disclosure.

FIG. 7 is a schematic diagram of capacitance calibration according to an embodiment of the present disclosure.

FIG. 8 is a schematic diagram of capacitance calibration according to an embodiment of the present disclosure.

FIG. 9A is a schematic diagram illustrating a variation of a circuit block according to an embodiment of the present disclosure.

FIG. 9B is a schematic diagram illustrating a variation of a circuit block according to an embodiment of the present disclosure.

10A and 10B are schematic diagrams showing clock signal reduction according to an embodiment of the present disclosure.

FIG. 11 is a flow chart showing a calibration method for a SAR ADC according to the present disclosure.

FIG. 12 is a flowchart of a calibration method for a SAR ADC according to an embodiment of the present invention.

FIG. 13 is a flowchart of a calibration method for a SAR ADC according to an embodiment of the present invention.

Description of Figure Numbers

100, 200: Successive Approximate Register Analog to Digital Converter

120, 220: First capacitive digital to analog converter

121, 281: Sampling switch

140, 240: Comparator

160, 260: Controller

280: Second Capacitive Digital to Analog Converter

300: Successive Approximate Register Analog to Digital Converter

310: First capacitive digital-to-analog converter

320: Second capacitive digital to analog converter

340: Comparator

345: Clock reduction circuit

360: Controller

380: Encoder

400: Correction Processor

CP1～CP11, CN1～CN11: capacitor

WP1～WP11、WN1～WN11、SW _TOP1 、SW _TOP2 ：Switch

Vcm: First reference voltage (common mode voltage)

Vref: Second reference voltage

GND: The third reference voltage

CQ: comparison result input

CQ1: First comparison result

CQ2_1~CQ2_10, CQ2_k: Second comparison result

D: Input terminal

GND: Ground voltage

RDY: Ready signal

RST: reset signal

SCP1~SCP10, SCN1~SCN10: Switching capacitor bank

SDO: digital output signal

SP1～SP10: first control signal

SN1～SN10: Second control signal

VDD: power supply voltage

VIP: First analog input signal

VIN: Second analog input signal

VP0: First voltage

VP1～VPk: Second voltage

VN0: third voltage

VN1～VNk: fourth voltage

Vr: comparison reference voltage

Vref: reference voltage

WIN1～WINk: Window area

CLKS: sampling clock signal

CLKC: comparison clock signal

RCLKC: Reduced Compare Clock

DETAILED DESCRIPTION

An embodiment of the present invention proposes a correction technology based on a window switching architecture continuous approximation analog-to-digital converter (SARADC for short), which can effectively reduce the device size of a digital-to-analog converter (DAC) that must achieve higher linearity performance due to process limitations, and can further achieve the dynamic power consumed by switching the analog-to-digital converter. This technology combines the advantages of window switching, and does not need to add other circuits to the signal path to obtain information about the comparator offset and flicker noise that will affect the correction. It can also improve the weight deviation accumulated due to the correction to further improve the integral nonlinearity (INL) of the analog-to-digital converter.

Analog to digital conversion operation

FIG1 is a circuit block diagram of a successive approximation register analog-to-digital converter 100 according to an embodiment of the present disclosure. The successive approximation register analog-to-digital converter (SAR ADC) 100 is used to convert a first analog input signal VIP into a digital output signal SDO, wherein the digital output signal SDO has N bits calculated from the most significant bit (MSB) to the least significant bit (LSB), wherein N is a positive integer, and N=10 is used for illustration below.

The SAR ADC 100 may include a first capacitor digital to analog converter (CDAC) 120, a comparator 140, and a controller 160. The first capacitor digital to analog converter 120 may include a sampling switch 121 and a switching capacitor group SCP1-SCP10, which are respectively controlled by first control signals SP1-SP10. The first capacitor digital to analog converter 120 may receive and sample a first analog input signal VIP through the sampling switch 121 at a time point to generate a first voltage VP0. The sampling switch 121 may be, for example, a bootstrapped switch controlled by a sampling clock signal CLKS. The first capacitor digital to analog converter 120 is controlled by a plurality of first control signals SP1-SP10 to respectively control the switching operation of the switching capacitor groups SCP1-SCP10. Specifically, the switching capacitor group SCPi may include a capacitor CPi and a switch WPi, where i is an integer from 1 to L (in this example, L=10). The first ends of the capacitors CP1 to CP10 are coupled to the non-inverting input end of the comparator 140, and the second ends of the capacitors CP1 to CP10 are switched between the reference voltage Vref and the ground voltage GND through the corresponding switches WP1 to WP10. The switches WP1 to WP10 are controlled by the first control signals SP1 to SP10, respectively. The capacitance values of the capacitors CP1 to CP8 are respectively twice the capacitance values of the capacitors CP2 to CP9, and the capacitance value of the capacitor CP9 is equal to the capacitance value of the capacitor CP10. In an embodiment, the coupling can be a direct connection or an indirect connection. The indirect connection is, for example, connected through another device. For example, if device A is coupled to device B, it can be that device A is directly connected to device B, or that device A and device B are connected through device C. For example, after device A is directly connected to device C, device C is directly connected to device B.

The comparator 140 receives the first voltage VP0 from the first capacitive digital-to-analog converter 120 and is controlled by the comparison clock signal CLKC to compare the first voltage VP0 with a comparison reference voltage Vr to generate a first comparison result CQ1, wherein the comparison reference voltage Vr may be, for example, a reference voltage Vref. The controller 160 is coupled to the comparator 140 and the first capacitive digital-to-analog converter 120. In particular, the controller 160 may generate first control signals SP1-SP10 according to the first comparison result CQ1 to control the switching operations of the switched capacitor groups SCP1-SCP10 respectively.

Furthermore, the controller 160 has a binary window function. The controller 160 can determine the switching operation of at least one of the switched capacitor groups SCP1-SCP10 according to the output of the comparator 140 (i.e., the first comparison result VP0) to make the output of the first capacitive digital-to-analog converter 120 approach the above-mentioned binary window, wherein the above-mentioned binary window is an M-bit window, and M is a positive integer less than or equal to N. In detail, in the k-th iteration operation of the M-iteration operation of the continuous approximate register analog-to-digital converter 100 (k is less than or equal to M), the controller 160 can switch the k-th switched capacitor group SCPk among the switched capacitor groups SCP1-SCP10 (e.g., from the first state to the second state), so that the first capacitive digital-to-analog converter 120 generates a corresponding second voltage VPk. Then, the comparator 140 can compare the second voltage VPk of the k-th iteration operation with the comparison reference voltage Vr to generate a corresponding second comparison result CQ2_k. The controller 160 may define (or determine) the window area WINk according to the first comparison result CQ1 and the second comparison result CQ2_k, and may determine whether to switch the kth switching capacitor group SCPk back to the first state or maintain it in the second state according to the first comparison result CQ1 and the second comparison result CQ2_k.

In the k-th iteration operation, if the first comparison result CQ1 indicates that the first voltage VP0 is greater than the comparison reference voltage Vr, and the second comparison result CQ2_k indicates that the second voltage VPk is also greater than the comparison reference voltage Vr, the controller 160 maintains the k-th switching capacitor group in the second state (i.e., the switched state). Alternatively, in the k-th iteration operation, if the first comparison result CQ1 indicates that the first voltage VP0 is less than the comparison reference voltage Vr, and the second comparison result CQ2_k indicates that the second voltage VPk is also less than the comparison reference voltage Vr, the controller 160 maintains the k-th switching capacitor group in the second state (i.e., the switched state).

Correspondingly, in the kth iterative operation, if the first comparison result CQ1 and the second comparison result CQ2_k indicate that one of the first voltage VP0 and the second voltage VPk is greater than the comparison reference voltage Vr, and the other of the first voltage VP0 and the second voltage VPk is less than the comparison reference voltage Vr, the controller 160 switches the kth switching capacitor group back to the first state (i.e., the state before switching).

FIG2 is a schematic diagram of a switching mechanism of a single-ended input continuous approximation register analog-to-digital converter when performing a binary window function according to an embodiment of the present disclosure, wherein the horizontal axis represents time and the vertical axis represents the output voltage of the first capacitive digital-to-analog converter 120, and the following description will be made with M being equal to 4. Since the binary window is a 4-bit window, four window areas surrounded by dotted lines, namely WIN1 to WIN4, are respectively shown in FIG2 in the first iteration operation (i.e., k=1) to the fourth iteration operation (i.e., k=4).

First, in a sample-and-hold operation (i.e., k=0), the first capacitive digital-to-analog converter 120 receives and samples the first analog input signal VIP through the sampling switch 121 to generate a first voltage VP0. In one embodiment, the amplitude of the first analog input signal VIP is, for example, equal to the reference voltage Vref, and the common mode voltage of the first analog input signal VIP is, for example, equal to the reference voltage Vref. The comparator 140 can determine whether the first voltage VP0 is greater than the comparison reference voltage Vr, thereby generating a first comparison result CQ1. Then, in the first iteration operation (i.e., k=1), the controller 160 can generate a first control signal SP1 according to the first comparison result CQ1 to control the switching operation of the switched capacitor group SCP1. The following first describes the case where the first voltage VP0 is greater than the comparison reference voltage Vr.

In the sample-and-hold operation (i.e., k=0), if the first voltage VP0 is greater than the comparison reference voltage Vr, the comparator 140 may output a first comparison result CQ1 such as logic 1. Therefore, in the first iteration operation (i.e., k=1), the controller 160 switches the switch WP1 in the switched capacitor group SCP1 to pull down the first voltage VP0, so that the first capacitive digital-to-analog converter 120 generates a corresponding second voltage VP1, wherein VP1=VP0-(Vref/2 ^k )=VP0-(Vref/2)=VP0-(Vr/2). It is worth mentioning that the reference voltage Vref here is the comparison reference voltage Vr, so the following example assumes that Vref=Vr. Then, the comparator 140 may compare the second voltage VP1 of the first iteration operation (i.e., k=1) with the comparison reference voltage Vr to determine whether the second voltage VP1 is greater than the comparison reference voltage Vr. If the second voltage VP1 is greater than the comparison reference voltage Vr, the comparator 140 will output a second comparison result CQ2_1, for example, of logic 1. It is understandable that if the second voltage VP1 is greater than the comparison reference voltage Vr, it means that the first voltage VP0 is greater than 1.5Vref and is located outside the window area WIN1, so the controller 160 maintains the switch WP1 in the switching capacitor group SCP1 in the switched state, at which time VP1=VP0-(Vr/2). Conversely, if the second voltage VP1 is less than the comparison reference voltage Vr, the comparator 140 will output a second comparison result CQ2_1, for example, of logic 0. It is understandable that if the second voltage VP1 is less than the comparison reference voltage Vr, it means that the first voltage VP0 is less than 1.5Vref and is located within the window area WIN1, so the controller 160 returns the switch WP1 in the switching capacitor group SCP1 to the state before switching, at which time VP1=VP0.

Next, in the second iteration operation (i.e., k=2), the controller 160 switches the switch WP2 in the switched capacitor group SCP2 to pull down the second voltage VP1, so that the first capacitive digital-to-analog converter 120 generates a corresponding second voltage VP2, wherein VP2=VP1-(Vr/2 ^k )=VP1-(Vr/4). Next, the comparator 140 can compare the second voltage VP2 of the second iteration operation (i.e., k=2) with the comparison reference voltage Vr to determine whether the second voltage VP2 is greater than the comparison reference voltage Vr. If the second voltage VP2 is greater than the comparison reference voltage Vr, the comparator 140 will output a second comparison result CQ2_2 such as logic 1. It can be understood that if the second voltage VP2 is greater than the comparison reference voltage Vr, it means that the second voltage VP1 is greater than 1.25Vref and is outside the window area WIN2, so the controller 160 maintains the switch WP2 in the switched capacitor group SCP2 in the switched state, and at this time VP2=VP1-(Vr/4). In contrast, if the second voltage VP2 is less than the comparison reference voltage Vr, the comparator 140 will output a second comparison result CQ2_2, for example, a logic 0. It is understandable that if the second voltage VP2 is less than the comparison reference voltage Vr, it means that the second voltage VP1 is less than 1.25Vref and is located within the window area WIN2, so the controller 160 returns the switch WP2 in the switching capacitor group SCP2 to the state before switching, and VP2=VP1 at this time. It is worth mentioning that the second voltage VP1 here is determined according to the result of the first iteration operation (i.e., k=1) (i.e., the second comparison result CQ2_1). If the second comparison result CQ2_1 is, for example, a logic 1, VP1=VP0-(Vr/2); if the second comparison result CQ2_1 is, for example, a logic 0, VP1=VP0.

As for the operation of the SAR ADC 100 in the third iteration operation (i.e., k=3) and the fourth iteration operation (i.e., k=4), it can be inferred from the description of the first iteration operation (i.e., k=1) and the second iteration operation (i.e., k=2) mentioned above, so it will not be repeated here.

The following is a description of the case where the first voltage VP0 is less than the comparison reference voltage Vr. In the sample-and-hold operation (i.e., k=0), if the first voltage VP0 is less than the comparison reference voltage Vr, the comparator 140 may output a first comparison result CQ1, such as logic 0. Therefore, in the first iteration operation (i.e., k=1), the controller 160 switches the switch WP1 in the switched capacitor group SCP1 to pull up the first voltage VP0, so that the first capacitive digital-to-analog converter 120 generates a corresponding second voltage VP1, wherein VP1=VP0+(Vr/2 ^k )=VP0+(Vr/2). Then, the comparator 140 may compare the second voltage VP1 of the first iteration operation (i.e., k=1) with the comparison reference voltage Vr to determine whether the second voltage VP1 is greater than the comparison reference voltage Vr. If the second voltage VP1 is greater than the comparison reference voltage Vr, the comparator 140 will output a second comparison result CQ2_1, such as logic 1. It is understood that if the second voltage VP1 is greater than the comparison reference voltage Vr, it means that the first voltage VP0 is greater than 0.5Vref and is located within the window area WIN1, so the controller 160 returns the switch WP1 in the switched capacitor group SCP1 to the state before switching, and VP1=VP0 at this time. In contrast, if the second voltage VP1 is less than the comparison reference voltage Vr, the comparator 140 will output a second comparison result CQ2_1 of, for example, logic 0. It is understood that if the second voltage VP1 is less than the comparison reference voltage Vr, it means that the first voltage VP0 is less than 0.5Vref and is located outside the window area WIN1, so the controller 160 maintains the switch WP1 in the switched capacitor group SCP1 in the state after switching, and VP1=VP0+(Vr/2).

Next, in the second iteration operation (i.e., k=2), the controller 160 switches the switch WP2 in the switched capacitor group SCP2 to pull up the second voltage VP1, so that the first capacitive digital-to-analog converter 120 generates a corresponding second voltage VP2, wherein VP2=VP1+(Vr/2 ^k )=VP1+(Vr/4). Next, the comparator 140 can compare the second voltage VP2 of the second iteration operation (i.e., k=2) with the comparison reference voltage Vr to determine whether the second voltage VP2 is greater than the comparison reference voltage Vr. If the second voltage VP2 is greater than the comparison reference voltage Vr, the comparator 140 will output a second comparison result CQ2_2 such as logic 1. It can be understood that if the second voltage VP2 is greater than the comparison reference voltage Vr, it means that the second voltage VP1 is greater than 0.75Vref and is within the window area WIN2, so the controller 160 returns the switch WP2 in the switched capacitor group SCP2 to the state before switching, and at this time VP2=VP1. In contrast, if the second voltage VP2 is less than the comparison reference voltage Vr, the comparator 140 will output a second comparison result CQ2_2, for example, of logic 0. It is understandable that if the second voltage VP2 is less than the comparison reference voltage Vr, it means that the second voltage VP1 is less than 0.75Vref and is outside the window area WIN2, so the controller 160 maintains the switch WP2 in the switched capacitor group SCP2 in the switched state, and at this time VP2=VP1+(Vr/4). It is worth mentioning that the second voltage VP1 here is determined according to the result of the first iteration operation (i.e., k=1) (i.e., the second comparison result CQ2_1). If the second comparison result CQ2_1 is, for example, logic 1, VP1=VP0; if the second comparison result CQ2_1 is, for example, logic 0, VP1=VP0+(Vr/2).

As for the operation of the SAR ADC 100 in the third iteration operation (i.e., k=3) and the fourth iteration operation (i.e., k=4), it can be inferred from the description of the first iteration operation (i.e., k=1) and the second iteration operation (i.e., k=2) mentioned above.

FIG3 is a circuit block diagram of a SAR analog-to-digital converter 200 according to another embodiment of the present disclosure. The SAR analog-to-digital converter 200 is a differential input analog-to-digital converter. The SAR analog-to-digital converter 200 is used to convert a differential pair signal (including a first analog input signal VIP and a second analog input signal VIN) into a digital output signal SDO.

The SAR ADC 200 may include a first capacitive digital-to-analog converter 220, a second capacitive digital-to-analog converter 280, a comparator 240, and a controller 260. The architectures of the first capacitive digital-to-analog converter 220, the comparator 240, and the controller 260 are similar to the first capacitive digital-to-analog converter 120, the comparator 140, and the controller 160 of FIG. 1 , respectively, and thus the relevant descriptions of FIG. 1 may be referred to and analogized, and will not be described in detail herein.

The second capacitive digital-to-analog converter 280 may include a sampling switch 281 and a switching capacitor group SCN1-SCN10. The second capacitive digital-to-analog converter 280 may receive and sample the second analog input signal VIN through the sampling switch 281 at a time point to generate a third voltage VN0. The sampling switch 281 may be, for example, a bootstrap switch controlled by a sampling clock signal CLKS. The second capacitive digital-to-analog converter 280 is controlled by a plurality of second control signals SN1-SN10 to respectively control the switching operation of the switching capacitor group SCN1-SCN10. In detail, the switching capacitor group SCNi may include a capacitor CNi and a switch WNi, where i is an integer from 1 to 10. The first end of the capacitor CN1-CN10 is coupled to the inverting input terminal of the comparator 240, and the second end of the capacitor CN1-CN10 is switched between the reference voltage Vref and the ground voltage GND through the switches WN1-WN10, respectively. The switches WN1-WN10 are controlled by second control signals SN1-SN10 respectively. The capacitance values of capacitors CN1-CN8 are twice the capacitance values of capacitors CN2-CN9 respectively, and the capacitance value of capacitor CN9 is equal to the capacitance value of capacitor CN10.

In operation, the comparator 240 receives the first voltage VP0 from the first capacitive digital-to-analog converter 220 and the third voltage VN0 from the second capacitive digital-to-analog converter 280. The comparator 240 can be controlled by the comparison clock signal CLKC to compare the difference between the first voltage VP0 and the third voltage VN0 with the zero crossing point to generate a first comparison result CQ1. In particular, the controller 260 can generate the first control signals SP1-SP10 and the second control signals SN1-SN10 according to the first comparison result CQ1 to control the switching operations of the switched capacitor groups SCP1-SCP10 and SCN1-SCN10, respectively.

Further, the controller 260 has a binary window function. The controller 260 can determine the switching operation of at least one of the switched capacitor groups SCP1-SCP10 and at least one of the switched capacitor groups SCN1-SCN10 according to the output of the comparator 240 (i.e., the first comparison result CQ1), so as to make the output of the first capacitive digital-to-analog converter 220 and the output of the second capacitive digital-to-analog converter 280 approach the above-mentioned binary window, wherein the above-mentioned binary window is an M-bit window, and M is a positive integer less than or equal to N. In detail, in the k-th iteration operation (k is less than or equal to M) of the M-th iteration operation of the continuous approximate register analog-to-digital converter 200, the controller 260 can switch the k-th switched capacitor group SCPk among the switched capacitor groups SCP1-SCP10 (for example, from the first state to the second state), so that the first capacitive digital-to-analog converter 220 generates the corresponding second voltage VPk. In addition, the controller 260 may switch the kth switched capacitor group SCNk among the switched capacitor groups SCN1-SCN10 (e.g., switching from the first state to the second state), so that the second capacitive digital-to-analog converter 280 generates a corresponding fourth voltage VNk. Then, the comparator 240 may compare the difference between the second voltage VPk and the fourth voltage VNk of the kth iteration operation with a zero crossing point (e.g., 0 volts) to generate a corresponding second comparison result CQ2_k. The controller 260 may define (or determine) a window area WINk based on the first comparison result CQ1 and the second comparison result CQ2_k. In addition, the controller 260 may determine whether to switch the kth switched capacitor group of the first capacitive digital-to-analog converter 220 and the kth switched capacitor group of the second capacitive digital-to-analog converter 280 back to the first state (i.e., the state before switching) or maintain them in the second state based on the first comparison result CQ1 and the second comparison result CQ2_k.

Referring to FIG. 3 and FIG. 4 , FIG. 4 is a schematic diagram of a switching mechanism when a differential input continuous approximation register analog-to-digital converter performs a binary window function according to an embodiment of the present disclosure, wherein the horizontal axis represents time and the vertical axis represents the voltage difference between the output voltage of the first capacitive digital-to-analog converter 220 and the output voltage of the second capacitive digital-to-analog converter 280 (i.e., the differential input voltage of the comparator 240). For the convenience of explanation, the following will be described with M equal to 4 (i.e., the above-mentioned binary window is a 4-bit window) as an example, and the embodiments where M is other positive integers can be analogized according to the following description. Based on the binary window being a 4-bit window, in the first iteration operation (i.e., k=1) to the fourth iteration operation (i.e., k=4) of FIG. 4 , four window areas WIN1 to WIN4 surrounded by dotted lines are respectively shown.

First, in a sample-and-hold operation (i.e., k=0), the first capacitive digital-to-analog converter 220 controls the sampling switch 221 to receive and sample the first analog input signal VIP to generate a first voltage VP0 through the sampling clock signal CLKS, and the second capacitive digital-to-analog converter 280 controls the sampling switch 281 to receive and sample the second analog input signal VIN to generate a third voltage VN0 through the sampling clock signal CLKS. In one embodiment, the amplitudes of the first analog input signal VIP and the second analog input signal VIN are, for example, equal to the reference voltage Vref, and the common mode voltages of the first analog input signal VIP and the second analog input signal VIN are, for example, equal, and the phase difference between the first analog input signal VIP and the second analog input signal VIN is, for example, 180 degrees. The comparator 240 is controlled by the comparison clock signal CLKC, and can determine whether the difference between the first voltage VP0 and the third voltage VN0 is greater than the zero crossing point, thereby generating a first comparison result CQ1. Next, in the first iteration operation (i.e., k=1), the controller 260 can generate the first control signal SP1 and the second control signal SN1 according to the first comparison result CQ1 to control the switching operation of the switched capacitor groups SCP1 and SCN1. The following will first be described with respect to the difference between the first voltage VP0 and the third voltage VN0 being greater than the zero crossing point (i.e., VP0-VN0>0).

In the sample-and-hold operation (i.e., k=0), if the difference between the first voltage VP0 and the third voltage VN0 is greater than the zero-crossing point, the comparator 240 may output a first comparison result CQ1, such as a logic 1. Therefore, in the first iteration operation (i.e., k=1), the controller 260 switches the switch WP1 in the switched capacitor group SCP1 to pull down the first voltage VP0, so that the first capacitive digital-to-analog converter 220 generates a corresponding second voltage VP1, wherein VP1=VP0-(Vref/2). At the same time, the controller 260 switches the switch WN1 in the switched capacitor group SCN1 to pull up the third voltage VN0, so that the second capacitive digital-to-analog converter 280 generates a corresponding fourth voltage VN1, wherein VN1=VN0+(Vref/2). Then, the comparator 240 may compare the second voltage VP1 of the first iteration operation (i.e., k=1) with the fourth voltage VN1 to determine whether the difference between the second voltage VP1 and the fourth voltage VN1 is greater than the zero-crossing point. If the difference between the second voltage VP1 and the fourth voltage VN1 is greater than the zero crossing point, the comparator 240 will output a second comparison result CQ2_1, for example, of logic 1. It can be understood that if the difference between the second voltage VP1 and the fourth voltage VN1 is greater than the zero crossing point, it means that the difference between the first voltage VP0 and the third voltage VN0 is greater than Vref and is outside the window area WIN1, so the controller 260 maintains the switch WP1 in the switched capacitor group SCP1 and the switch WN1 in the switched capacitor group SCN1 in the switched state, and at this time, the difference between the second voltage VP1 and the fourth voltage VN1 is VP1-VN1=[VP0-(Vref/2)]-[VN0+(Vref/2)]=(VP0-VN0)-Vref. In contrast, if the difference between the second voltage VP1 and the fourth voltage VN1 is less than the zero crossing point, the comparator 240 will output a second comparison result CQ2_1, for example, of logic 0. It can be understood that if the difference between the second voltage VP1 and the fourth voltage VN1 is less than the zero crossing point, it means that the difference between the first voltage VP0 and the third voltage VN0 is less than Vref and is within the window area WIN1, so the controller 260 restores the switch WP1 in the switching capacitor group SCP1 and the switch WN1 in the switching capacitor group SCN1 to the state before switching. At this time, the difference between the second voltage VP1 and the fourth voltage VN1 is VP1-VN1=VP0-VN0.

Then, in the second iteration operation (i.e., k=2), the controller 260 switches the switch WP2 in the switched capacitor group SCP2 to pull down the second voltage VP1, so that the first capacitive digital-to-analog converter 220 generates a corresponding second voltage VP2, wherein VP2=VP1-(Vref/4). At the same time, the controller 260 switches the switch WN2 in the switched capacitor group SCN2 to pull up the fourth voltage VN1, so that the second capacitive digital-to-analog converter 280 generates a corresponding fourth voltage VN2, wherein VN2=VN1+(Vref/4). Then, the comparator 240 can compare the second voltage VP2 of the second iteration operation (i.e., k=2) with the fourth voltage VN2 to determine whether the difference between the second voltage VP2 and the fourth voltage VN2 is greater than the zero crossing point. If the difference between the second voltage VP2 and the fourth voltage VN2 is greater than the zero crossing point, the comparator 240 will output a second comparison result CQ2_2, such as logic 1. It can be understood that if the difference between the second voltage VP2 and the fourth voltage VN2 is greater than the zero crossing point, it means that the difference between the second voltage VP1 and the fourth voltage VN1 is greater than 0.5Vref and is outside the window area WIN2, so the controller 260 maintains the switch WP2 in the switched capacitor group SCP2 and the switch WN2 in the switched capacitor group SCN2 in the switched state, at which time VP2-VN2=[VP1-(Vref/4)]-[VN1+(Vref/4)]=(VP1-VN1)-0.5Vref. In contrast, if the difference between the second voltage VP2 and the fourth voltage VN2 is less than the zero crossing point, the comparator 240 will output a second comparison result CQ2_2 of, for example, logic 0. It can be understood that if the difference between the second voltage VP2 and the fourth voltage VN2 is less than the zero crossing point, it means that the difference between the second voltage VP1 and the fourth voltage VN1 is less than 0.5Vref and is within the window area WIN2, so the controller 260 restores the switch WP2 in the switching capacitor group SCP2 and the switch WN2 in the switching capacitor group SCN2 to the state before switching, at which time VP2-VN2=(VP1-VN1).

As for the switching operation of the first capacitive digital-to-analog converter 220 and the second capacitive digital-to-analog converter 280 in the third iteration operation (i.e., k=3) and the fourth iteration operation (i.e., k=4), respectively, it can be inferred from the description of the first iteration operation (i.e., k=1) and the second iteration operation (i.e., k=2), so it is not repeated here. It can be understood that when the difference between the first voltage VP0 and the third voltage VN0 is greater than the zero crossing point, the controller will control the switching operation of the first capacitive digital-to-analog converter 220 and the second capacitive digital-to-analog converter 280 according to the first comparison result CQ1 and the second comparison result CQ2_k. On the other hand, when the difference between the first voltage VP0 and the third voltage VN0 is less than the zero crossing point, the controller 260 will control the switching operation of the first capacitive digital-to-analog converter 220 and the second capacitive digital-to-analog converter 280 according to the first comparison result CQ1 and the second comparison result CQ2_k, and its detailed operation can be inferred from the description above, so it is not repeated here.

Calibration method

In one embodiment, the analog-to-digital converter performs normal operation of analog-to-digital conversion in the operation mode and performs calibration in the calibration mode; in one embodiment, the calibration mode may be entered before the operation mode; in one embodiment, the calibration mode may be entered after a period of operation in the operation mode; in one embodiment, the calibration mode may be entered after each period of operation in the operation mode (periodically). Next, the method of capacitor calibration of the disclosed embodiment will be described. The circuit architecture described in FIG. 3 above is used as an example for explanation. In the architecture of this example, the circuit diagram is slightly simplified in order to focus on the part of capacitor calibration. In this example, 11 capacitors are used as an example, where capacitors CP1~CP5 and CN1~CN5 are capacitors to be calibrated, and capacitors CP6~CP11 and CN6~CN11 are accurate capacitors; in implementation, each capacitor may be a capacitor group, for example, capacitors CP1 and CN1 may each be composed of 8 smaller capacitors, and capacitors CP2 and CN2 may each be composed of 4 smaller capacitors, and the present invention is not limited thereto. When manufacturing capacitors CP6-CP11 and CN6-CN11, the required accuracy can be achieved by requiring process parameters. In one embodiment, accurate capacitors are used as references to calibrate relatively inaccurate capacitors without adding additional circuits. In this embodiment, accurate capacitors CP6-CP11 and CN6-CN11 are used to calibrate relatively inaccurate capacitors CP1-CP5 and CN1-CN5.

FIG5 is a timing diagram of the calibration of an embodiment of the present disclosure. In the embodiment of the present disclosure, the calibration process can be performed multiple times, and the obtained flicker noise and the offset of the comparator and the average value of the capacitors C1 to C5 can be calibrated multiple times to make the obtained calibration value more accurate. As shown in FIG5, the calibration sequence in each calibration cycle is to first calibrate the flicker noise and the offset of the comparator (i.e., O&F in the figure, both are collectively referred to as noise), and then calibrate the capacitors CP5 to CP1 and CN5 to CN1. In one embodiment, the flicker noise and the offset of the comparator are calibrated in the first cycle of the sampling clock CLKS, and the capacitors CP5 to CP1 and CN5 to CN1 are calibrated in the second to sixth cycles of the sampling clock CLKS. In the first cycle of the sampling clock CLKS, the information Do[x] of the offset and flicker noise of the comparator is obtained. Then, in each sampling clock CLKS, the capacitors CP5-CP1 and CN5-CN1 are calibrated in sequence to obtain the calibration information Do[x+1]-Do[x+5], where Do[x] is the binary digital code output by the analog-to-digital converter, where x represents each calibration cycle, x is a positive integer, and y represents the number of repetitions of a calibration procedure, which is a natural number. Similarly, the above calibration procedure is repeated. For example, in the seventh to twelfth cycles of the sampling clock CLKS, the calibration information Do[x+6]-Do[x+11] of the offset and flicker noise of the comparator and the capacitors CP5-CP1 and CN5-CN1 can be obtained. By analogy, this overall calibration procedure will continue for several cycles for averaging.

Next, the correction method is explained in conjunction with the circuit structure, in which the correction of flicker noise and comparator offset, capacitors CP5, CN5 and capacitors CP1, CN1 will be explained. The correction method of capacitors CP4, CN5 to CP2, CN2 is similar to the correction method of capacitors CP5, C1 and capacitors CN5, CN1.

Next, the capacitance calibration method of the present disclosure is described with reference to Figures 6 to 8. Figure 6 is a schematic diagram of calibrating flicker noise and offset of the comparator 340 according to an embodiment of the present disclosure.

As shown in FIG6 , the SAR analog-to-digital converter 300 may include a first capacitive digital-to-analog converter 310, a second capacitive digital-to-analog converter 320, a comparator 340, and a controller 360. The outputs VCP and VCN of the first capacitive digital-to-analog converter 310 and the second capacitive digital-to-analog converter 320 are connected to two input terminals of the comparator 340, respectively. Capacitors CP1 and CN1 correspond to the MSB, followed by capacitors CP2 and CN2, capacitors CP3 and CN4, etc., but the present invention is not limited thereto. The comparison result output by the comparator 340 is then transmitted to the controller 360. In one embodiment, the controller 360 performs the control of the analog-to-digital conversion illustrated in FIGS. 1 to 4 , and/or performs the control of the capacitance correction and the quantization of the flicker noise and the offset of the comparator 360.

First, the flicker noise and the offset of the comparator 340 are corrected. As shown in FIG6 , when the sampling clock CLKS is at a high level, the switches SW _TOP1 and SW _TOP2 of the first ends (or top plates) of the capacitors CP1-CP11 and CN1-CN11 are connected. At this time, the first ends of the capacitors CP1-CP11 of the first capacitive digital-to-analog converter 310 are connected to the first input voltage VIP via the switch SW _TOP1 , and the first ends of the capacitors CN1-CN11 of the second capacitive digital-to-analog converter 320 are connected to the second input voltage VIN via the switch SW _TOP2 . In one embodiment, the voltage of the first input voltage VIP and the second input voltage VIN is an arbitrary voltage value, and this arbitrary voltage value is determined based on the input common mode voltage Vicm of the comparator; in one embodiment, at this time, the voltage value of the first input voltage VIP and the second input voltage VIN is the input common mode voltage Vicm, and the second ends (or bottom plates) of the capacitors CP1-CP11 and CN1-CN11 are switched to the first reference voltage Vcm by switches WP1-WP11 and WN1-WN11, respectively, thereby resetting all the capacitors CP1-CP11 and CN1-CN11. In one embodiment, the voltage of the first input voltage VIP and the second input voltage VIN is Vcm, and the second ends of the capacitors CP1-CP11 and the capacitors CN1-CN11 are switched to the input common mode voltage Vicm or other voltages by switches WP1-WP11 and switches WN1-WN11, thereby resetting all the capacitors CP1-CP11 and CN1-CN11. In one embodiment, the input common mode voltage Vicm of the operation mode = (VIP+VIN)/2. In one embodiment, the first reference voltage Vcm may be an input common mode voltage Vicm. In one embodiment, when resetting the capacitors CP1-CP11 and the capacitors CN1-CN11, the voltages at the first and second ends of the capacitors CP1-CP11 and the capacitors CN1-CN11 may be the same.

When the sampling clock CLKS turns to a low level, the controller 360 turns off the switches SW _TOP1 and SW _TOP2 , so that the first ends of the capacitors CP1-CP11 and the capacitors CN1-CN11 are disconnected from the first input voltage VIP and the second input voltage VIN, and the second ends of the capacitors CP1-CP5 and the capacitors CN1-CN5 (i.e., the capacitors to be calibrated) are maintained at the first reference voltage Vcm by the switches WP1-WP5 and the switches WN1-WN5, respectively. When the sampling clock CLKS turns from a high level to a low level, the calibration procedure is entered, and the calibration of the offset and flicker noise is started in the T0 cycle of the comparator clock CLKC. In one embodiment, in the T1-T5 cycles of the comparator clock CLKC, the switches WP1-WP5 of the capacitors CP1-CP5 and the switches WN1-WN5 of the capacitors CN1-CN5 do not perform switching actions. After 5 cycles (T1-T5) of the comparison clock CLKC, the digital-to-analog conversion operation of the SAR ADC 300 is performed by the accurate capacitors CP6-CP11 of the first capacitive digital-to-analog converter 310 and the accurate capacitors CN6-CN11 of the second capacitive digital-to-analog converter 320 (zADC 5 shown in FIG. 6 ). When performing the digital-to-analog conversion operation of the SAR ADC 300, the second ends of the capacitors CP6-CP11 and the capacitors CN6-CN11 do not need to be connected to the first reference voltage Vcm, but can be connected to the second reference voltage Vref or the third reference voltage GND according to the operation of the SAR ADC 300. In one embodiment, the zADC is a corresponding analog-to-digital converter composed of accurate capacitors and/or calibrated capacitors. The corresponding capacitor switching is determined by the result of each bit of the zADC 5, that is, the binary search method of the SAR ADC 300 is performed. If the result of comparator 340 is 1 at this bit, it means that the capacitor on the VCP side of this bit is switched from Vcm to GND through the switch at the second end, and the capacitor on the VCN side is switched from the first reference voltage Vcm to the second reference voltage Vref through the switch at the second end. On the contrary, if the result of comparator 340 is 0 at this bit, it means that the capacitor on the VCP side of this bit is switched from the first reference voltage Vcm to the second reference voltage Vref through the switch at the second end, and the capacitor on the VCN side is switched from the first reference voltage Vcm to the third reference voltage GND through the switch at the second end. In this way, after the switching is completed, the comparison of the next bit is performed until all the bit conversions are completed. The binary seven-digit output obtained by zADC 5 is the information of flicker noise and the offset of comparator 340. In this embodiment, all accurate capacitors are used to measure the information of flicker noise and offset of the comparator 340, but the present invention is not limited thereto. In one embodiment, the information of flicker noise and offset of the comparator 340 can be measured by partial accurate capacitors, for example, the corresponding ADC of several capacitors with lower bits of LSB can measure the information of flicker noise and offset of the comparator 340. Specifically, for example, CP7-CP11 and CN7-CN11 can be measured. The measurement method is similar to the above. For example, when the sampling clock CLKS changes from a high potential to a low potential, the calibration procedure is entered. In the T0 cycle of the comparison clock CLKC, the calibration of offset and flicker noise begins. In the T1-T5 cycle of the comparison clock CLKC, the switches WP1-WP6 of the capacitors CP1-CP6 and the switches WN1-WN6 of the capacitors CN1-CN6 will not perform switching actions. After 6 cycles (T1-T6, T6 is not shown, T6 is the next cycle of T5) of the comparison clock CLKC, the digital-to-analog conversion operation of the SAR ADC 300 is performed by the accurate capacitors CP7-CP11 of the first capacitive digital-to-analog converter 310 and the accurate capacitors CN7-CN11 of the second capacitive digital-to-analog converter 320. When the digital-to-analog conversion operation of the SAR ADC 300 is performed, the second ends of the capacitors CP7-CP11 and the capacitors CN7-CN11 do not need to be connected to the first reference voltage Vcm, and can be connected to the second reference voltage Vref or the third reference voltage GND according to the operation of the SAR ADC 300. The obtained binary six-digit output is the information of the flicker noise and the offset of the comparator 340. The high voltage and low voltage in this embodiment are only for example. In another embodiment, the capacitors can be reset when the sampling clock CLKS is at a low voltage, and the calibration can be performed when the sampling clock CLKS is at a high voltage. The present disclosure is not limited to this.

After the flicker noise and the offset of the comparator 340 are quantized, the calibration process of the capacitors CP1-CP5 and the capacitors CN1-CN5 of the first capacitive digital-to-analog converter 310 and the second capacitive digital-to-analog converter 320 is performed. In one embodiment, the capacitor calibration starts from the smallest bit in the capacitor to be calibrated. In this embodiment, it starts from the capacitor CP5 and the capacitor CN5, that is, the capacitors CP6-CP11 and the capacitors CN6-CN11 whose bit order is closest to the accuracy.

FIG. 7 is a schematic diagram of capacitor calibration according to an embodiment of the present disclosure. The calibration of capacitors CP5 and CN5 is described below by way of an embodiment. As shown in FIG. 7 , when the sampling clock CLKS is at a high level, the first ends of capacitors CP1 to CP11 of the first capacitive digital-to-analog converter 310 are all connected to the first input voltage VIP via the switch SW _TOP1 , and the first ends of capacitors CN1 to CN11 of the second capacitive digital-to-analog converter 320 are all connected to the second input voltage VIN via the switch SW _TOP2 . In one embodiment, the voltage of the first input voltage VIP and the second input voltage VIN is the input common mode voltage Vicm, and the second ends of capacitors CP1 to CP11 and capacitors CN1 to CN11 are switched to Vcm by switches WP1 to WP11 and WN1 to WN11, thereby resetting all capacitors CP1 to CP11 and CN1 to CN11.

After the sampling clock CLKS turns to a low potential, during the T0-T4 period of the comparison clock CLKC, the second ends of the capacitors CP1-CP4 and the capacitors CN1-CN4 of the corresponding first capacitive digital-to-analog converter 310 and the second capacitive digital-to-analog converter 320 are maintained at the first reference voltage Vcm via switches WP1-WP4 and switches WN1-WN4, respectively, while SW _TOP1 and SW _TOP2 corresponding to the first capacitive digital-to-analog converter 310 and the second capacitive digital-to-analog converter 320 are disconnected. During the T0-T4 period of the comparison clock CLKC, the comparator 340 can make comparisons, but the voltages of the second ends of the capacitors are not switched. In one embodiment, the switch control signal generated by the controller 360 can be blocked by the logic gate circuit inside the controller 360, so that the switches WP1-WP4 of the capacitors CP1-CP4 and the switches WN1-WN4 of the capacitors CN1-CN4 are not switched during the T1-T4 period.

Next, at the T5 cycle of the comparison clock CLKC, the calibration of the capacitors CP5 and CN5 is started. At this time, the second end of the capacitor CP5 of the first capacitive digital-to-analog converter 310 is connected to the second reference voltage Vref (reference voltage) through the switch WP5, and the second end of the capacitor CN5 of the second capacitive digital-to-analog converter 320 is connected to the third reference voltage GND (ground voltage) through the switch WN5. Next, after the T5 cycle of the comparison clock CLKC, the analog-to-digital conversion operation of the zADC 5 corresponding to the capacitors CP6-CP11 and CN6-CN11 is performed.

As mentioned above, the capacitors CP6-CP11 of the first capacitive digital-to-analog converter 310 and the capacitors CN6-CN11 of the second capacitive digital-to-analog converter 320 can be accurately manufactured by requiring process parameters, so the analog-to-digital conversion performed by zADC 5 corresponding to CP6-CP11 and CN6~CN11 can obtain accurate results to calibrate the capacitors CP5 and CN5.

In one embodiment, the result obtained by analog-to-digital conversion by zADC 5 includes flicker noise and the offset of comparator 340. In one embodiment, the result obtained by analog-to-digital conversion by zADC 5 is subtracted from flicker noise and the offset of comparator 340 (e.g., the flicker noise and the offset of comparator 340 obtained above) to obtain the capacitance weight W _C5 of capacitor CP5 and/or capacitor CN5. In one embodiment, such as the differential circuit shown in FIG7 , the capacitance weight W _C5 is the weight of the bit corresponding to capacitor CP5 and capacitor CN5. In another embodiment, such as the single-ended circuit shown in FIG1 , the capacitance weight W _C5 is the weight of the bit corresponding to capacitor CP5. In another embodiment, the capacitance weight W _C5 is the weight of the bit corresponding to capacitor CN5. The capacitance weights W _C1 to W _C4 are similar to the capacitance weight W _C5 , and the same can be said.

FIG8 is a schematic diagram of capacitor calibration according to an embodiment of the present disclosure. The calibration of capacitors CP1 and CN1 is described below by way of an embodiment. As shown in FIG8 , when the sampling clock CLKS is at a high potential, the first ends of capacitors CP1 to CP11 of the first capacitive digital-to-analog converter 310 are all connected to the first input voltage VIP via the switch SW _TOP1 , and the first ends of capacitors CN1 to CN11 of the second capacitive digital-to-analog converter 320 are all connected to the second input voltage VIN via the switch SW _TOP2 . In one embodiment, the voltage of the first input voltage VIP and the second input voltage VIN is the input common mode voltage Vicm, and the second ends of capacitors CP1 to CP11 and capacitors CN1 to CN11 are respectively switched to Vcm by switches WP1 to WP11 and switches WN1 to WN11, thereby resetting all capacitors CP1 to CP11 and CN1 to CN11.

After the sampling clock CLKS turns to a low potential, the SW _TOP1 and SW _TOP2 corresponding to the first capacitive digital-to-analog converter 310 and the second capacitive digital-to-analog converter 320 are both disconnected. In the T0 cycle of the comparison clock CLKC, the comparator 340 can make comparisons, but the voltage of the second end of the capacitor is not switched. In the T1 cycle of the comparison clock CLKC, the capacitors CP1 and CN1 are calibrated. At this time, the second end of the capacitor CP1 of the first capacitive digital-to-analog converter 310 is connected to the second reference voltage Vref (reference voltage) through the switch WP1, and the second end of the capacitor CN1 of the second capacitive digital-to-analog converter 320 is connected to the third reference voltage GND (ground voltage) through the switch WN1. Then, after the cycle T1 of the comparison clock CLKC, the analog-to-digital conversion is performed with zADC1 (including the SARADC corresponding to the calibrated capacitors CP2-CP5, CN2-CN5 and the accurate capacitors CP6-CP11, CN6-CP11), and the voltage of the second end of the capacitor corresponding to each bit is switched with the comparison result of each bit of zADC1. The eleven-bit binary digital output obtained in this way is the weight of the capacitors CP1 and CN1. In one embodiment, the result obtained by analog-to-digital conversion of zADC1 includes flicker noise and the offset of the comparator 340. The weight of the capacitors CP1 and CN1 obtained by analog-to-digital conversion of zADC 1 minus the flicker noise and the offset of the comparator 340 (such as the flicker noise and the offset of the comparator 340 obtained above) can obtain the capacitance weight W _C1 of the capacitors CP1 and CN1.

As mentioned above, the capacitors CP6-CP11 of the first capacitive digital-to-analog converter 310 and the capacitors CN6-CN11 of the second capacitive digital-to-analog converter 320 are accurate capacitors, and the capacitors CP2-CP5 and CN2-CN5 have also been calibrated. When the capacitors CP2-CP11 and CN2-CN11 of zADC1 perform a general continuous approximate analog-to-digital conversion operation, the capacitors CP1 and CN1 can be calibrated. The weights of the capacitors CP1 and CN1 obtained in this way include the flicker noise and the offset of the comparator 340, so the flicker noise and the offset of the comparator 340 can be subtracted to obtain the capacitance weight W _C1 of the capacitors CP1 and CN1.

In a similar manner to the above, the capacitance weights of the capacitors CP2-CP4 of the first capacitive digital-to-analog converter 310 and the capacitors CN2-CN4 of the second capacitive digital-to-analog converter 320 can be calibrated. Taking the calibration capacitors CP4 and CN4 as an example, when the sampling clock CLKS is at a high level, the capacitors CP1-CP11 and CN1-CN11 are reset, when the sampling clock CLKS is at a low level and during the T0-T3 cycle of the comparison clock CLKC, SW _TOP1 and SW _TOP2 are disconnected, and during the T4 cycle of the comparison clock CLKC, the second ends of the capacitors CP1-CP3 and CN1-CN3 are maintained at the first reference voltage Vcm, and the second end of the capacitor CP4 of the first capacitive digital-to-analog converter 310 is switched to the second reference voltage Vref through the switch WP4, and the second end of the capacitor CN4 of the second capacitive digital-to-analog converter 320 is switched to the third reference voltage GND through the switch WN4. In cycle T4 of the comparison clock CLKC, the capacitors CP4 and CN4 are calibrated, and zADC4 (including the calibrated capacitors CP5 and CN5 and the SAR ADC corresponding to the accurate capacitors CP6-CP11 and CN6-CN11) performs a general continuous approximate analog-to-digital conversion operation, and then subtracts the flicker noise and the offset of the comparator 340 to obtain the capacitance weight W _C4 of the capacitors CP4 and CN4. The calibration method of the capacitors CP2 and CN2, and CP3 and CN3 is similar to the above, and can be inferred by analogy.

In one embodiment, the timing of the calibration procedure of the SAR ADC 300 in the calibration mode is the same or similar to that in the operation mode, so that the calibration of capacitance and the measurement of flicker noise and offset of the comparator 340 can be achieved without adding or changing circuits.

In one embodiment, after obtaining the capacitance weight of each capacitor, the capacitance weight can be used to correct the digital code output by the first capacitive digital-to-analog converter 310 and/or the second capacitive digital-to-analog converter 320 to obtain an accurate digital code. In one embodiment, due to inaccurate capacitance, the digital code output by the first capacitive digital-to-analog converter 310 and/or the second capacitive digital-to-analog converter 320 may deviate from the correct digital code. After obtaining the capacitance weight of each capacitor, a redundant circuit (not shown) can be used to correct the deviation to obtain the correct digital code. In one embodiment, flicker noise and the offset of the comparator 340 can be quantified.

The following is another example of how to calculate the capacitance weights W _C1 ～W _C5 of the capacitors CP1 ～ CP5 and the capacitors CN1 ～ CN5. As described above, in the circuit architecture examples shown in FIGS. 6-8 , a calibration procedure is performed over 6 cycles of the sampling clock CLKS, and the flicker noise and comparator offset as well as the calibration of the capacitors CP5 ～ CP1 and the capacitors CN5 ～ CN1 are performed in six cycles. In one implementation, the calibration procedure can be performed multiple times, and the calibration values obtained each time are averaged to obtain a more accurate capacitance calibration value. In conjunction with FIG. 5 , when the above procedure is performed y times, the average weights W _C1avg ～W _C5avg of the capacitors CP5 ～ CP1 and CN5 ～ CN1 can be calculated by formula (1), where W _C1avg is the average weight of the capacitors CP1 and CN1, and D0[x+6y] is the flicker noise and the offset of the comparator 340 obtained at the y+1th time. Wherein, x represents each calibration cycle, and x is a positive integer. y represents the number of repetitions of a calibration procedure, which is a natural number. By executing the calibration procedure multiple times, the influence of white noise on the capacitance calibration weight can be eliminated. D0[(x+1)+6y]~D0[(x+5)+6y] and D0[x+6y] are binary digital codes obtained by the operation of SARADC 300 in each calibration cycle.

FIG9A is a schematic diagram of a circuit block variation example of an embodiment of the present disclosure. As shown in FIG9A , the SAR analog-to-digital converter 300 may further include: an encoder 380 coupled to the controller 360 for receiving the output of the controller 360; and a calibration processor 400 coupled to the encoder 380. In the calibration mode, taking the calibration capacitors CP5 and CN5 as an example, the SAR ADC 300 outputs a binary digital result to the encoder 380, and the encoder 380 encodes the binary digital result to generate a decimal encoding result, and then transmits the encoding result to the calibration processor 400. The calibration processor 400 may use a loop to average the calibration procedure performed y times. In one embodiment, the calibration processor 400 may perform the operation of formula (1). In one embodiment, the digital code output by the first capacitive digital-to-analog converter 310 and/or the second capacitive digital-to-analog converter 320 may be corrected by the averaged capacitance weights W _C1avg ～W _C5avg , and analog-to-digital conversion is performed in the operation mode to obtain an accurate analog-to-digital conversion result. In one embodiment, the influence of white noise can be eliminated by averaging the data obtained from multiple calibrations. In one embodiment, the digital code output by the first capacitive digital-to-analog converter 310 and/or the second capacitive digital-to-analog converter 320 can be corrected by using the unaveraged single capacitance weights W _C1 -W _C5 .

FIG9B is a schematic diagram of a circuit block variation of an embodiment of the present disclosure. As shown in FIG9B , the SAR ADC 300 may further include a clock reduction circuit 345, which may be used to generate a reduced comparison clock RCLKC. In one embodiment, the clock reduction circuit 345 may reduce the comparison clock CLKC to generate the reduced comparison clock RCLKC. In one embodiment, the reduced comparison clock RCLKC may be used to further reduce the calibration time.

In the above embodiment, after measuring the noise, the calibration starts from the capacitor to be calibrated that is closest to the LSB until the capacitor to be calibrated that is closest to the MSB. For example, the calibration of capacitors CP1 to CP5 and CN1 to CN5 starts from capacitors CP5 and CN5, and then calibrates to capacitors CP1 and CN1 in sequence. In this order, the first calibrated capacitors CP5 and CN5 are the capacitors to be calibrated that are closest to the LSB, and the capacitors CP6 to CP11 and CN6 to CN11 that serve as the basis for calibration are all accurate capacitors. After calibrating capacitors CP5 and CN5, the capacitors CP5 to CP11 and CN5 to CN11 are used to calibrate the next capacitors CP4 and CN4 that are closest to the LSB. By analogy, the capacitor to be calibrated that is closest to the LSB is calibrated each time, and the capacitors used to calibrate the capacitors to be calibrated include previously calibrated capacitors and accurate capacitors.

However, the present disclosure is not limited thereto. In another embodiment, after measuring the noise, calibration is started from the capacitor to be calibrated closest to the MSB until the capacitor to be calibrated closest to the LSB. However, the description of calibration from the MSB side to the LSB side is as follows.

First, capacitors CP2-CP11 and CN2-CN11 (e.g., zADC 1 in FIG8 ) are used to calibrate capacitors CP1 and CN1. At this time, capacitors CP6-CP11 and CN6-CN11 in zADC 1 are accurate, but capacitors CP2-CP5 and CN2-CN5 have not been calibrated. Therefore, when the weight W _C1' of capacitors CP1 and CN1 is obtained in the above manner, W _C1' may include the errors of capacitors CP2-CP5 and CN2-CN5. Similarly, the weight W _C2' of capacitors CP2 and CN2 may include the errors of capacitors CP3-CP5 and CN3-CN5, the W _C3' of capacitor CP3 may include the errors of capacitors CP4-CP5 and CN4-CN5, and the weight W _C4' of capacitors CP4 and CN4 may include the errors of capacitors CP5 and CN5. When calibrating capacitors CP5 and CN5, the correct capacitance weight W _C5 of capacitors CP5 and CN5 can be obtained in the same or similar manner as in FIG7 .

Next, from the calibration processor 400 shown in FIG. 9A or 9B, the capacitance weight W _C5 of the capacitor CP5 and CN5 is used to calculate the correct capacitance weight W _C4 of the capacitor CP4 and CN4, and the weights W _C5 and W C4 of the capacitor CP5 and CN5 and the capacitor CP4 and CN4 are used to calculate the correct capacitance weight W _C3 of the capacitor CP3 and CN3. And so on, finally, the correct capacitance weight W _C1 of the capacitor CP1 and CN1 is calculated using the weights W _C5 to W _{C2 .} In one embodiment, the average capacitance weight calculation method of the capacitors CP1 to CP5 and CN1 to CN5 can be calculated by formula (1).

In one embodiment, if the accurate capacitance of the analog-to-digital converter of the continuous approximate register is from the 0th to the ath bit, then in one embodiment, the calibration sequence may be repeated increasing from the i-th bit from i=a+1 bit upwards to generate the capacitance weight of each capacitor until the capacitance weight of the (Nd-1)th bit is generated. In one embodiment, the calibration sequence may be repeated decreasing from the i-th bit from i=Nd-1 bit downwards to generate the capacitance weight of each capacitor until the capacitance weight of the a+1th bit is generated.

In one embodiment, the calibration timing uses the clock sequence of the continuous approximation register analog-to-digital converter in the operation mode, so the calibration of the capacitor and the measurement of the flicker noise and the offset of the comparator 340 can be achieved without adding or changing the hardware structure of the circuit. In another embodiment, the calibration time can be further reduced. For example, as shown in FIG. 7, when the calibration of the capacitors CP5 and CN5 is performed, the timing of the original operation mode is used. During the T0-T4 period of the comparison clock CLKC, the capacitor is not switched. Therefore, the T0-T4 period can be shortened to reduce the calibration time.

10A and 10B are schematic diagrams of clock signal reduction according to an embodiment of the present disclosure. As shown in the upper half of FIG. 10A , in the operation mode, the T0 period is the period of the sample-and-hold operation, and the T1-T5 periods are the corresponding analog-to-digital conversion periods of the capacitors CP1-CP5 and CN1-CN5. In the calibration mode, after the flicker noise and the offset of the comparator 340 are measured, the capacitors CP1-CP5 and CN1-CN5 are not switched during the period T1-T5, and the analog-to-digital conversion of the zADC 5 is performed after the next period of the comparison clock CLKC. In one embodiment, as shown in the lower half of FIG. 10A , the T1-T5 periods are omitted in the calibration mode; that is, the operation of the zADC 5 is performed in the next period of the period T0, and its timing is shown in the waveform of the reduced comparison clock RCLKC.

In one embodiment, as shown in the upper half of FIG. 10B , in the operation mode, the T0 period is the period of the sample-and-hold operation, and the T1-T5 periods are the corresponding analog-to-digital conversion periods of the capacitors CP1-CP5 and CN1-CN5; in the calibration mode, after the flicker noise and the offset of the comparator 340 are measured, the capacitors CP1-CP4 and CN1-CP4 are not switched during the period T1-T4, until the voltages at the second terminals of the capacitors CP5 and CN5 are switched in the period T5, and then the analog-to-digital conversion of the zADC 5 is performed. In one embodiment, as shown in the lower half of FIG. 10B , the T0-T4 periods are omitted in the calibration mode; that is, after the sampling clock CLKS turns to a low level, the first period of the comparison clock CLKC can be the period T5, and the calibration procedure of the capacitors CP5 and CN5 is directly entered, and its timing is shown in the waveform of the reduced comparison clock RCLKC. In this embodiment, it is not necessary to wait for the period T0-T4, so that the calibration time is faster. Similarly, when calibrating capacitors CP4 and CN4, the waiting period of periods T0 to T3 can be omitted. When calibrating capacitors CP3 and CN3, the waiting period of periods T0 to T2 can be omitted. When calibrating capacitors CP2 and CN2, the waiting period of periods T0 to T1 can be omitted. When calibrating capacitors CP1 and CN1, the waiting period of period T0 can be omitted. In this way, the overall calibration time can be further shortened.

In one embodiment, the capacitive digital-to-analog converter has Nd bits, where Nd is a positive integer. When the capacitance of the i-th bit is corrected, the comparison clock RCLKC is reduced to omit the waiting period from the Nd-1-th bit capacitance to the (i+1)-th bit in the operation mode timing (comparison clock CLKC), where i is an integer less than Nd. In one embodiment, as shown in FIG. 9B , a clock reduction circuit 345 can be added to the continuous approximate register analog-to-digital converter 300 to perform clock reduction, that is, the comparison clock CLKC of the operation mode is reduced to the reduced comparison clock RCLKC, and the waiting period is omitted.

In addition, in the above-mentioned calibration procedure, when the calibration capacitor is calibrated, the second terminal voltage of the calibration capacitor of the first capacitive digital-to-analog converter 310 is switched and connected to the second reference voltage Vref, and the second terminal of the calibration capacitor of the second capacitive digital-to-analog converter 320 is switched and connected to the third reference voltage GND, but the present disclosure is not limited to this. For example, the second terminal voltage of the calibration capacitor of the first capacitive digital-to-analog converter 310 is switched and connected to the third reference voltage GND, and the second terminal of the calibration capacitor of the second capacitive digital-to-analog converter 320 is switched and connected to the second reference voltage Vref. In another embodiment, the second terminal voltage of the calibration capacitor of the first capacitive digital-to-analog converter 310 can be connected to the second reference voltage Vref or the third reference voltage GND, that is, it can be switched to different reference voltages, and in another embodiment, it can also be switched to other voltages. Similarly, the second terminal voltage of the calibration capacitor of the second capacitive digital-to-analog converter 320 can be connected to the second reference voltage Vref or the third reference voltage GND, that is, it can be switched to different reference voltages, and in another embodiment, it can also be switched to other voltages. In another embodiment, the second reference voltage may be one of Vref and GND, and the third reference voltage may be the other of Vref and GND. For example, the second reference voltage may be GND, and the third reference voltage may be Vref.

In the above embodiment, the capacitance correction procedure is described with a differential circuit (e.g., the circuit shown in FIG. 3 ), but a single-ended circuit (e.g., the circuit shown in FIG. 1 ) can also be applied to the capacitance correction method of the present disclosure. That is, the input end of the comparator 340 is only connected to a capacitive digital-to-analog converter, and the capacitance correction method of the present disclosure can also be applied. The capacitance correction method under the single-ended circuit architecture is the same or similar to the correction method of the differential circuit, and its description is omitted here.

FIG. 11 is a flow chart of a calibration method of a continuous approximate register analog-to-digital converter of the present disclosure. In one embodiment, the continuous approximate register analog-to-digital converter includes at least one Nd-bit capacitive digital-to-analog converter, and the capacitors of the capacitive digital-to-analog converter correspond to the 0th bit to the Nd-1th bit, wherein the capacitors from the 0th bit to the i-1th bit are, for example, the above-mentioned accurate capacitors (e.g., capacitors CP11 to CP6, CN11 to CN6), and the capacitors from the ith bit to the Nd-1th bit are, for example, capacitors to be calibrated (e.g., the above-mentioned capacitors CP5 to CP1, CN5 to CN1), and i is an integer less than Nd. In one embodiment, the digital code converted by the Nd-bit capacitive digital-to-analog converter can obtain a digital code of Nd+1 bits after conversion by the SAR ADC. For example, the SAR ADC can compare the difference between VIP and VIN without capacitor operation to obtain a digital code with one more bit. As shown in FIG11 , in step S100 , the capacitors from the i-th to the (Nd-1)th bits are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the (i-1)th to the 0th bits, where i is an integer less than Nd. In one embodiment, step S100 may obtain noise, which may include flicker noise and offset of a comparator.

In one embodiment, the first ends of the capacitors from the Nd-1th bit to the 0th bit are connected to an input voltage (e.g., VIP, VIN), and the second ends of the capacitors are connected to a first reference voltage (e.g., Vcm); the first ends of the capacitors from the Nd-1th bit to the 0th bit are disconnected from the input voltage; and a continuous approximate register analog-to-digital converter corresponding to the capacitors from the (i-1)th bit to the 0th bit is used to generate a first digital code to measure the noise.

Next, step S102 is executed. In step S102, the capacitors of the (i+1)th to (Nd-1)th positions are coupled to a first reference voltage, the capacitor of the ith position is coupled to a second reference voltage, and a second digital code is generated according to the operation of the capacitors of the (i-1)th to 0th positions. In one embodiment, step S102 calibrates the capacitor of the ith position based on the operation of the capacitors of the (i-1)th to 0th positions, and generates a second digital code by the comparator, and subtracts the second digital code from the first digital code to generate the weight of the capacitor of the ith position.

In one embodiment, the i-th bit capacitor is coupled to a second reference voltage or a third reference voltage, and the (Nd-1)-th to (i+1)-th bit capacitors are coupled to the first reference voltage, and a second digital code is generated by a continuous approximate register analog-to-digital converter corresponding to the (i-1)-th to 0-th bit capacitors, and a weight of the i-th bit capacitor is generated by the second digital code and the first digital code.

In one embodiment, the first end of the capacitor from the (Nd-1)th bit to the 0th bit (such as CP1~CP11, CN1~CN11) is connected to the input voltage (such as VIP, VIN), and the second end of the capacitor is connected to the first reference voltage (such as Vcm); the first end of the capacitor from the Nd-1th bit to the 0th bit is disconnected from the input voltage; the second end of the capacitor of the i-th bit is coupled to the second reference voltage (such as Vref) or the third reference voltage (such as GND); and a continuous approximate register analog-to-digital converter corresponding to the capacitor from the (i-1)th bit to the 0th bit is used to generate a second digital code, and the capacitance weight of the i-th bit capacitor is generated by the second digital code and the first digital code.

In step S106, it is determined whether i is equal to Nd-1, that is, whether the above action has been performed to the Nd-1th bit. If it has not yet been performed to the Nd-1th bit, that is, the judgment result is no, then step S108 is performed. Step S108 increments i, that is, i=i+1, and then continues to execute step S102 until i=Nd-1. In addition, when in step S106, it is determined whether i is equal to Nd-1, that is, the capacitance weights of the capacitors up to the (Nd-1)th bit have been generated, and the continuous approximate buffer analog-to-digital converter calibration is completed. In one embodiment, a step can be added between steps S102 and S106 to generate the capacitance weight of the capacitor of the i-th bit according to the first digital code and the second digital code; in one embodiment, after judging i=Nd-1 in step S106, the capacitance weights of the capacitors of each bit can be generated according to each second digital code obtained by executing step S102 each time. After obtaining the capacitance weights of each bit or all bits, the corresponding SAR analog-to-digital converter can be corrected according to the obtained capacitance weights.

FIG. 12 is a flow chart of a calibration method for a continuous approximate register analog-to-digital converter according to an embodiment of the present invention. In this embodiment, it is not necessary to use all accurate capacitors to obtain flicker noise and comparator offset. The continuous approximate register analog-to-digital converter includes at least one capacitive digital-to-analog converter and a controller, and at least one capacitive digital-to-analog converter includes Nd capacitors corresponding to Nd bits, where Nd is a positive integer. As shown in FIG. 12. In step S1202, the capacitors from the zth bit to the (Nd-1)th bit are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the (z-1)th bit to the 0th bit, where z is an integer less than Nd. In one embodiment, for example, the capacitive digital-to-analog converters from the 0th to the 5th bit have accurate capacitors, Nd is, for example, 11, and z is, for example, 5, and the capacitors from the 5th bit to the 10th bit are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the 4th bit to the 0th bit, and the first digital code includes flicker noise and comparator offset. In step S1204, the capacitors of the (i+1)th to (Nd-1)th positions are coupled to a first reference voltage, the capacitor of the ith position is coupled to a second reference voltage, and a second digital code is generated according to the operation of the capacitors of the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i. In this embodiment, i is, for example, 6, the capacitors of the 7th to 10th positions are coupled to a first reference voltage, the capacitor of the 6th position is coupled to a second reference voltage, and a second digital code is generated according to the operation of the capacitors of the 5th to the 0th position. In step S1206, a capacitance weight of the capacitor of the ith position is generated according to the first digital code and the second digital code. In this embodiment, a capacitance weight of the capacitor of the 6th position is generated according to the first digital code generated by the operation of the capacitors of the 4th to the 0th position and the second digital code generated by the capacitors of the 5th to the 0th position, and in step S1208, a continuous approximate register analog-to-digital converter is calibrated according to the capacitance weight of the capacitor of the ith position.

FIG13 is a flow chart of a calibration method for a continuous approximate register analog-to-digital converter according to an embodiment of the present invention. The continuous approximate register analog-to-digital converter includes at least one capacitive digital-to-analog converter and a controller, and at least one capacitive digital-to-analog converter includes Nd capacitors corresponding to Nd bits, where Nd is a positive integer. As shown in FIG13 . In step S1302, the capacitors from the i-th to (Nd-1)-th bits are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the (i-1)-th to the 0-th bits, where i is an integer less than Nd. In one embodiment, Nd is, for example, 11, and i is, for example, 6, and the capacitors from the 6th to the 10th bits are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the 5th to the 0th bits, and the first digital code includes flicker noise and an offset of a comparator. In step S1304, the capacitors from the (i+1)th to the (Nd-1)th are coupled to the first reference voltage, the capacitor from the ith is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors from the (i-1)th to the 0th. In this embodiment, i is 6, for example, and the capacitors from the 7th to the 10th are coupled to the first reference voltage, and the capacitor from the 6th is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors from the 5th to the 0th. In step S1306, a capacitance weight of the capacitor from the ith is generated according to the first digital code and the second digital code. In this embodiment, a capacitance weight of the capacitor from the 6th is generated according to the first digital code generated by the operation of the capacitors from the 5th to the 0th and the second digital code generated by the capacitors from the 5th to the 0th, and in step S1308, a continuous approximate register analog-to-digital converter is calibrated according to the capacitance weight of the capacitor from the ith.

It can be known from the above description that the capacitor calibration method of the disclosed embodiment can be performed under the original operation structure of the continuous approximate register analog-to-digital converter without adding an additional circuit structure. For example, the comparison clock CLKC that drives the continuous approximate register analog-to-digital converter to perform analog-to-digital conversion is used as the calibration clock. During the T1-T5 period of the comparison clock CLKC, it can be used to drive the capacitors CP1-CP5 and CN1-CN5 to perform analog-to-digital conversion in the operation mode. In the calibration mode, the capacitor to be calibrated can be connected to the second reference voltage Vref or the third reference voltage GND, while other capacitors that have not been calibrated are connected to the first reference voltage Vcm. Therefore, in one embodiment, the control sequence in the controller 360 can be changed to be suitable for the operation mode and the calibration mode without significantly changing the overall circuit structure or increasing the area of the capacitor, and the size of the overall circuit will not be increased.

In summary, based on the above description of the present disclosure, if the number of capacitors to be corrected is NumC, the time required for correction can be reduced to (NumC+1) cycles, which is about twice as fast as the 2NumC cycles required for traditional correction. If the correction process is repeated multiple times in succession, it can also be used to eliminate the white noise generated by the circuit, making the correction more accurate. An embodiment of the present disclosure can obtain information about flicker noise and comparator offset without adding circuits to the signal path.

In addition, an embodiment of the present disclosure can improve the capacitance weight deviation accumulated due to calibration, so as to further enhance the integral nonlinearity of the capacitive digital-to-analog converter.

According to an embodiment of the present disclosure, a calibration method for a continuous approximate register analog-to-digital converter is provided. The continuous approximate register analog-to-digital converter includes at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter includes Nd capacitors corresponding to Nd bits, where Nd is a positive integer. The capacitance correction method of the continuous approximate register analog-to-digital converter includes: coupling the capacitors from the zth to (Nd-1)th bits to a first reference voltage, generating a first digital code according to the operation of the capacitors from the (z-1)th to the 0th bits, wherein z is an integer less than Nd; coupling the capacitors from the (i+1)th to the (Nd-1)th bits to the first reference voltage, coupling the capacitors from the i-th bit to a second reference voltage, generating a second digital code according to the operation of the capacitors from the (i-1)th to the 0th bits, wherein i is an integer less than Nd, and z is less than i; generating a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and calibrating the continuous approximate register analog-to-digital converter according to the capacitance weight of the capacitor at the i-th bit.

In the above-mentioned capacitor correction method of the continuous approximate register analog-to-digital converter, the capacitors from the zth bit to the (Nd-1)th bit are coupled to the first reference voltage, and the first digital code is generated according to the operation of the capacitors from the (z-1)th bit to the 0th bit, including: coupling the first end of the capacitors from the (Nd-1)th bit to the 0th bit to the input voltage, and coupling the second end of the capacitors from the (Nd-1)th bit to the 0th bit to the first reference voltage; disconnecting the first end of the capacitors from the (Nd-1)th bit to the 0th bit from the input voltage; and generating the first digital code using the continuous approximate register analog-to-digital converter corresponding to the capacitors from the (z-1)th bit to the 0th bit.

According to an embodiment of the present disclosure, a calibration method for a continuous approximate register analog-to-digital converter is provided, wherein the continuous approximate register analog-to-digital converter includes at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter includes Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer. The capacitance calibration method for the continuous approximate register analog-to-digital converter includes: coupling the capacitors from the i-th bit to the (Nd-1)-th bit to a first reference voltage, generating a first digital code according to the operation of the capacitors from the (i-1)-th bit to the 0th bit, wherein i is an integer less than Nd; coupling the capacitors from the (i+1)-th bit to the (Nd-1)-th bit to the first reference voltage, coupling the capacitors from the i-th bit to the second reference voltage, generating a second digital code according to the operation of the capacitors from the (i-1)-th bit to the 0th bit; generating a capacitance weight of the capacitors from the i-th bit according to the first digital code and the second digital code; and calibrating the continuous approximate register analog-to-digital converter according to the capacitance weight of the capacitors from the i-th bit.

The capacitance calibration method of the SAR analog-to-digital converter further includes executing the capacitance calibration method multiple times to obtain an average value of the capacitance weight of the i-th bit.

In the above-mentioned capacitor correction method of the continuous approximate register analog-to-digital converter, the capacitors from the i-th to the (Nd-1)th bits are coupled to the first reference voltage, and the first digital code is generated according to the operation of the capacitors from the (i-1)th to the 0th bits, including: coupling the first ends of the capacitors from the (Nd-1)th to the 0th bits to the input voltage, and coupling the second ends of the capacitors from the (Nd-1)th to the 0th bits to the first reference voltage; disconnecting the first ends of the capacitors from the (Nd-1)th to the 0th bits from the input voltage; and generating the first digital code using the continuous approximate register analog-to-digital converter corresponding to the capacitors from the (i-1)th to the 0th bits.

In the above-mentioned capacitor calibration method of the continuous approximate register analog-to-digital converter, the capacitors from the (i+1)th bit to the (Nd-1)th bit are coupled to the first reference voltage, and the capacitors from the i-th bit are coupled to the second reference voltage. The second digital code is generated according to the operation of the capacitors from the (i-1)th bit to the 0th bit, including: coupling the second ends of the capacitors from the (i+1)th bit to the (Nd-1)th bit to the first reference voltage, and coupling the second ends of the capacitors from the i-th bit to the second reference voltage; and generating the second digital code using the continuous approximate register analog-to-digital converter corresponding to the capacitors from the (i-1)th bit to the 0th bit.

In the above-mentioned capacitance correction method of the continuous approximate register analog-to-digital converter, the at least one capacitive digital-to-analog converter includes a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter, wherein coupling the second end of the i-th capacitor to the second reference voltage includes: coupling the second end of the i-th capacitor of the first capacitive digital-to-analog converter to the second reference voltage; and coupling the second end of the i-th capacitor of the second capacitive digital-to-analog converter to a third reference voltage.

In the above-mentioned capacitance calibration method of the SAR ADC, the SAR ADC further includes a comparator, and the input voltage is determined by an input common mode voltage of the comparator.

The capacitance calibration method of the above-mentioned continuous approximate register analog-to-digital converter further includes: after generating the second digital code, coupling the capacitors at the (i+2)th to the (Nd-1)th positions to the first reference voltage, coupling the capacitors at the (i+1)th position to the second reference voltage, generating a third digital code according to the operation of the capacitors at the i-th to the 0th positions; and generating a capacitance weight of the capacitor at the i+1th position according to the first digital code and the third digital code. In one embodiment, i is repeatedly incremented upward to generate capacitance weights of each capacitor until the capacitance weight of the (Nd-1)th position is generated.

The capacitance calibration method of the above-mentioned continuous approximate register analog-to-digital converter further includes: after generating the second digital code, coupling the capacitors from the i-th to the (Nd-1)th to the first reference voltage, coupling the capacitors from the (i-1)th to the second reference voltage, generating a third digital code according to the operation of the capacitors from the (i-2)th to the 0th; and generating a capacitance weight of the capacitor from the i-1th to the 1st according to the first digital code and the third digital code. In one embodiment, i is repeatedly decreased downward to generate capacitance weights of each capacitor until the capacitance weight of the (a+1)th is generated.

The capacitance calibration method of the above-mentioned continuous approximate buffer analog-to-digital converter also includes: obtaining the capacitance weight of the j-th capacitor according to the capacitance weights of the capacitors from the (j-1)th to the i-th bit, where Nd>j>i.

In the above-mentioned capacitance calibration method of the SAR ADC, the calibration timing of the capacitance calibration method is the same as the operation mode timing of the SAR ADC.

In the above-mentioned capacitance correction method of the continuous approximate register analog-to-digital converter, when the capacitance correction method corrects the capacitance of the i-th bit, the correction timing of the capacitance correction method omits the waiting period from the (Nd-1)th bit capacitance to the (i+1)th bit capacitance in the operation mode timing.

In the above-mentioned capacitance calibration method of the SAR ADC, the SAR ADC further includes a comparator, and the first digital code includes flicker noise and information of an offset of the comparator.

In the above-mentioned capacitance correction method of the continuous approximate register analog-to-digital converter, generating the capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code includes subtracting the first digital code from the second digital code to generate the capacitance weight of the capacitor at the i-th bit.

According to another embodiment of the present disclosure, a continuous approximate register analog-to-digital converter with a calibration function is provided, comprising: at least one capacitive digital-to-analog converter, which is controlled by a plurality of control signals to respectively control the switching operation of Nd switching capacitors of the at least one capacitive digital-to-analog converter, wherein Nd is a positive integer; a comparator, coupled to the at least one capacitive digital-to-analog converter, for comparing the output of the at least one capacitive digital-to-analog converter with a comparison voltage; and a controller, coupled to the comparator and the at least one capacitive digital-to-analog converter, for generating the control signal and the digital output signal according to the output of the comparator. In the calibration mode, the controller obtains the capacitance weight of the i-th bit of the at least one capacitive digital-to-analog converter by the result of the (Nd+1)th operation of the comparator, wherein i is an integer less than Nd.

In the above-mentioned continuous approximate register analog-to-digital converter with correction function, the controller, when in operation mode, approaches the output of the at least one capacitive digital-to-analog converter to a window of Nd bits according to the output of the comparator, and completes an operation of approaching the output of the at least one capacitive digital-to-analog converter to the window of Nd bits by the result of (Nd+1) comparison operations of the comparator.

According to another embodiment of the present disclosure, a continuous approximate buffer analog-to-digital converter with a correction function is provided, comprising: at least one Nd-bit capacitive digital-to-analog converter having Nd-bit capacitance, where Nd is a positive integer; and a controller coupled to the at least one capacitive digital-to-analog converter. The controller is used to perform the following capacitor correction procedure: coupling the capacitors from the zth to (Nd-1)th bits to a first reference voltage, generating a first digital code based on the operation of the capacitors from the (z-1)th to the 0th bits, wherein z is an integer less than Nd; coupling the capacitors from the (i+1)th to the (Nd-1)th bits to the first reference voltage, coupling the capacitors from the i-th bit to a second reference voltage, generating a second digital code based on the operation of the capacitors from the (i-1)th to the 0th bits, wherein i is an integer less than Nd, and z is less than i; generating a capacitance weight of the capacitor at the i-th bit based on the first digital code and the second digital code; and calibrating the continuous approximate register analog-to-digital converter based on the capacitance weight of the capacitor at the i-th bit.

According to another embodiment of the present disclosure, a continuous approximate register analog-to-digital converter with a correction function is provided, comprising: at least one Nd-bit capacitive digital-to-analog converter having Nd-bit capacitors, wherein Nd is a positive integer; and a controller coupled to the at least one capacitive digital-to-analog converter. The controller is used to perform the following capacitor correction procedure: coupling the capacitors from the i-th to (Nd-1)-th bits to a first reference voltage, generating a first digital code according to the operation of the capacitors from the (i-1)-th to the 0-th bits, wherein i is an integer less than Nd; coupling the capacitors from the (i+1)-th to the (Nd-1)-th bits to the first reference voltage, coupling the capacitors from the i-th bit to a second reference voltage, generating a second digital code according to the operation of the capacitors from the (i-1)-th to the 0-th bits; generating a capacitance weight of the capacitor from the i-th bit according to the first digital code and the second digital code; and calibrating the continuous approximate register analog-to-digital converter according to the capacitance weight of the capacitor from the i-th bit.

In the above-mentioned SAR ADC with correction function, the controller executes the correction procedure more times to obtain the average value of the capacitance weight of the i-th bit.

In the above-mentioned continuous approximate register analog-to-digital converter with correction function, the controller performs the operation of coupling the capacitors from the i-th to the (Nd-1)-th bits to the first reference voltage, and generates the first digital code according to the operation of the capacitors from the (i-1)-th to the 0-th bits, including: coupling the first ends of the capacitors from the (Nd-1)-th to the 0-th bits to the input voltage, and coupling the second ends of the capacitors from the (Nd-1)-th to the 0-th bits to the first reference voltage; disconnecting the first ends of the capacitors from the (Nd-1)-th to the 0-th bits from the input voltage; and generating the first digital code using the continuous approximate register analog-to-digital converter corresponding to the capacitors from the (i-1)-th to the 0-th bits.

In the above-mentioned continuous approximate register analog-to-digital converter with correction function, the controller performs the operation of coupling the capacitors from the (i+1)th bit to the (Nd-1)th bit to the first reference voltage and coupling the capacitor from the i-th bit to the second reference voltage, and generates the second digital code according to the operation of the capacitors from the (i-1)th bit to the 0th bit, including: coupling the second ends of the capacitors from the (i+1)th bit to the (Nd-1)th bit to the first reference voltage and coupling the second ends of the capacitors from the i-th bit to the second reference voltage; and generating the second digital code using the continuous approximate register analog-to-digital converter corresponding to the capacitors from the (i-1)th bit to the 0th bit.

In the above-mentioned continuous approximate register analog-to-digital converter with correction function, wherein the at least one capacitive digital-to-analog converter includes a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter, wherein the controller couples the second end of the i-th capacitor to the second reference voltage including: coupling the second end of the i-th capacitor of the first capacitive digital-to-analog converter to the second reference voltage; and coupling the second end of the i-th capacitor of the second capacitive digital-to-analog converter to a third reference voltage.

In the above-mentioned SAR ADC with correction function, the SAR ADC further includes a comparator, and the input voltage is determined by the input common mode voltage of the comparator.

In the above-mentioned continuous approximate register analog-to-digital converter with correction function, the controller is further used to perform: after generating the second digital code, coupling the capacitors at the (i+2)th to the (Nd-1)th positions to the first reference voltage, coupling the capacitors at the (i+1)th positions to the second reference voltage, generating a third digital code based on the operation of the capacitors at the i-th to the 0th positions; and generating a capacitance weight of the capacitor at the i+1th position based on the first digital code and the third digital code.

In the above-mentioned continuous approximate register analog-to-digital converter with correction function, the controller also performs: after generating the second digital code, coupling the capacitors from the i-th bit to the (Nd-1)-th bit to the first reference voltage, coupling the capacitors from the (i-1)-th bit to the second reference voltage, generating a third digital code based on the operation of the capacitors from the (i-2)-th bit to the 0th bit; and generating the capacitance weight of the capacitor at the i-1-th bit based on the first digital code and the third digital code.

In the above-mentioned continuous approximate register analog-to-digital converter with correction function, the controller is also used to execute: obtaining the capacitance weight of the capacitor at the jth position according to the capacitance weights of the capacitors at the (j-1)th position to the i-th position, where Nd>j>i.

In the above-mentioned SAR ADC with calibration function, the calibration timing of the capacitance calibration procedure of the controller is the same as the operation mode timing of the SAR ADC.

The above-mentioned continuous approximate register analog-to-digital converter with correction function also includes: a clock reduction circuit, coupled between the controller and the comparator, for omitting the waiting period from the (Nd-1)th capacitor to the (i+1)th capacitor in the operation mode timing of the correction timing of the capacitor correction program when correcting the i-th capacitor.

In the above-mentioned SAR ADC with correction function, the SAR ADC further includes a comparator, and the first digital code includes flicker noise and information of an offset of the comparator.

In the above-mentioned SAR ADC with correction function, the controller subtracts the first digital code from the second digital code to generate the capacitance weight of the capacitor at the i-th bit.

Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person having ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the definition of the appended claims.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims (31)

1. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The calibration timing of the capacitance calibration method is the same as the operation mode timing of the SAR ADC. 2. The calibration method of a successive approximate register analog-to-digital converter according to claim 1, further comprising executing the capacitance calibration method multiple times to obtain an average value of the capacitance weight of the i-th bit. 3. The calibration method of a SAR ADC according to claim 1 , wherein the capacitors at the z-th bit to the (Nd-1)-th bit are coupled to the first reference voltage, and the first digital code is generated according to the operation of the capacitors at the (z-1)-th bit to the 0-th bit, comprising: The first ends of the capacitors from the (Nd-1)th to the 0th are coupled to an input voltage, and the second ends of the capacitors from the (Nd-1)th to the 0th are coupled to the first reference voltage; Disconnecting the first ends of the capacitors from the (Nd-1)th to the 0th from the input voltage; and The first digital code is generated by using the sequential approximate register analog-to-digital converter corresponding to the capacitors at the (z-1)th bit to the 0th bit. 4. The calibration method of a SAR ADC according to claim 3, wherein the capacitors at the (i+1)th to (Nd-1)th bits are coupled to the first reference voltage, the capacitor at the i-th bit is coupled to the second reference voltage, and the second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th bit, comprising: coupling the second ends of the capacitors at the (i+1)th to (Nd-1)th positions to the first reference voltage, and coupling the second end of the capacitor at the i-th position to the second reference voltage; and The second digital code is generated by using the sequential approximate register analog-to-digital converter corresponding to the capacitors from the (i-1)th bit to the 0th bit. 5. The calibration method of a SAR ADC according to claim 4, wherein the at least one capacitive digital-to-analog converter comprises a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter, wherein coupling the second end of the i-th capacitor to the second reference voltage comprises: The second end of the capacitor of the i-th bit of the first capacitive digital-to-analog converter is coupled to the second reference voltage; and The second end of the capacitor of the i-th bit of the second capacitive digital-to-analog converter is coupled to a third reference voltage. 6 . The calibration method of a SAR ADC as claimed in claim 5 , wherein the SAR ADC further comprises a comparator, and the input voltage is determined by an input common mode voltage of the comparator. 7. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The calibration method of the SAR analog-to-digital converter also includes: After the second digital code is generated, the capacitors at the (i+2)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the (i+1)th position is coupled to the second reference voltage, and a third digital code is generated according to the operation of the capacitors at the i-th to the 0th positions; and A capacitance weight of the (i+1)th capacitor is generated according to the first digital code and the third digital code. 8. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The calibration method of the SAR analog-to-digital converter also includes: After the second digital code is generated, the capacitors from the i-th to the (Nd-1)-th bits are coupled to the first reference voltage, the capacitor from the (i-1)-th bit is coupled to the second reference voltage, and a third digital code is generated according to the operation of the capacitors from the (i-2)-th bit to the 0-th bit; and A capacitance weight of the (i-1)th capacitor is generated according to the first digital code and the third digital code. 9. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is corrected according to the capacitance weight of the capacitor at the i-th bit. The correction method of the SAR analog-to-digital converter further includes: The capacitance weight of the capacitor at the jth position is obtained according to the capacitance weights of the capacitors at the (j-1)th position to the i-th position, wherein Nd>j>i. 10. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The continuous approximate register analog-to-digital converter is calibrated according to the capacitance weight of the capacitor at the i-th bit, wherein when the capacitance correction method calibrates the capacitance at the i-th bit, the correction timing of the capacitance correction method omits the waiting period from the (Nd-1)th capacitance to the (i+1)th capacitance in the operation mode timing. 11. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, wherein the SAR analog-to-digital converter further includes a comparator, and the first digital code includes flicker noise and information of an offset of the comparator. 12. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The continuous approximate register analog-to-digital converter is calibrated according to the capacitance weight of the capacitor at the i-th bit, wherein generating the capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code includes subtracting the first digital code from the second digital code to generate the capacitance weight of the capacitor at the i-th bit. 13. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors from the i-th to the (Nd-1)-th bits are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the (i-1)-th to the 0-th bits, wherein i is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the i-th position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The calibration timing of the capacitance calibration method is the same as the operation mode timing of the SAR ADC. 14 . The calibration method of a SAR analog-to-digital converter according to claim 13 , further comprising executing the capacitance calibration method multiple times to obtain an average value of the capacitance weight of the i-th bit. 15. The calibration method of a SAR ADC as claimed in claim 13, wherein the capacitors at the i-th to (Nd-1)-th bits are coupled to the first reference voltage, and the first digital code is generated according to the operation of the capacitors at the (i-1)-th to the 0-th bits, comprising: The first ends of the capacitors from the (Nd-1)th to the 0th are coupled to an input voltage, and the second ends of the capacitors from the (Nd-1)th to the 0th are coupled to the first reference voltage; Disconnecting the first ends of the capacitors from the (Nd-1)th to the 0th from the input voltage; and The first digital code is generated by using the sequential approximate register analog-to-digital converter corresponding to the capacitors at the (i-1)th to the 0th bit. 16. The calibration method of a SAR ADC as claimed in claim 15, wherein the capacitors at the (i+1)th to (Nd-1)th bits are coupled to the first reference voltage, the capacitor at the i-th bit is coupled to the second reference voltage, and the second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th bit, comprising: coupling the second ends of the capacitors at the (i+1)th to (Nd-1)th positions to the first reference voltage, and coupling the second end of the capacitor at the i-th position to the second reference voltage; and The second digital code is generated by using the sequential approximate register analog-to-digital converter corresponding to the capacitors from the (i-1)th bit to the 0th bit. 17. The calibration method of a SAR ADC according to claim 16, wherein the at least one capacitive digital-to-analog converter comprises a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter, wherein coupling the second end of the i-th capacitor to the second reference voltage comprises: The second end of the capacitor of the i-th bit of the first capacitive digital-to-analog converter is coupled to the second reference voltage; and The second end of the capacitor of the i-th bit of the second capacitive digital-to-analog converter is coupled to a third reference voltage. 18. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors from the i-th to the (Nd-1)-th bits are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the (i-1)-th to the 0-th bits, wherein i is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the i-th position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The calibration method of the SAR analog-to-digital converter also includes: The capacitance weight of the capacitor at the jth position is obtained according to the capacitance weights of the capacitors at the (j-1)th position to the i-th position, wherein Nd>j>i. 19. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors from the i-th to the (Nd-1)-th bits are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the (i-1)-th to the 0-th bits, wherein i is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the i-th position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, When the capacitance correction method corrects the capacitance of the i-th capacitor, the correction timing of the capacitance correction method omits the waiting period from the (Nd-1)th capacitance to the (i+1)th capacitance in the operation mode timing. 20. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors from the i-th to the (Nd-1)-th bits are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the (i-1)-th to the 0-th bits, wherein i is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the i-th position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The SAR ADC further includes a comparator, and the first digital code includes flicker noise and information of an offset of the comparator. 21. A calibration method for a CASCR analog-to-digital converter, wherein the CASCR analog-to-digital converter comprises at least one capacitive digital-to-analog converter and a controller, wherein the at least one capacitive digital-to-analog converter comprises Nd capacitors corresponding to Nd bits, wherein Nd is a positive integer, and the capacitance calibration method for the CASCR analog-to-digital converter comprises: The capacitors from the i-th to the (Nd-1)-th bits are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the (i-1)-th to the 0-th bits, wherein i is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the i-th position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, Generating the capacitance weight of the capacitor at the i-th position according to the first digital code and the second digital code includes subtracting the first digital code from the second digital code to generate the capacitance weight of the capacitor at the i-th position. 22. A successive approximate buffer analog-to-digital converter with a correction function, comprising: At least one capacitive digital-to-analog converter, controlled by a plurality of control signals to respectively control the switching operations of Nd switching capacitors of the at least one capacitive digital-to-analog converter, wherein Nd is a positive integer; a comparator coupled to the at least one capacitive digital-to-analog converter, for comparing an output of the at least one capacitive digital-to-analog converter with a comparison voltage; and a controller coupled to the comparator and the at least one capacitive digital-to-analog converter, for generating the control signal and the digital output signal according to the output of the comparator, Wherein, when the controller is in the calibration mode, the capacitance weight of the i-th bit of the at least one capacitive digital-to-analog converter is obtained by the result of the (Nd+1)th operation of the comparator, where i is an integer less than Nd, When the controller is in the operating mode, the output of the at least one capacitive digital-to-analog converter is approached to a window of Nd bits according to the output of the comparator, and the operation of approaching the output of the at least one capacitive digital-to-analog converter to the window of Nd bits is completed by the result of (Nd+1) comparison operations of the comparator. 23. A successive approximate buffer analog-to-digital converter with a correction function, comprising: At least one Nd-bit capacitive digital-to-analog converter having Nd-bit capacitance, wherein Nd is a positive integer; a controller coupled to the at least one capacitive digital-to-analog converter, The controller is used to perform the following capacitance calibration procedure: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The calibration timing of the capacitance calibration procedure of the controller is the same as the operation mode timing of the SAR ADC. 24. The SAR ADC with calibration function as claimed in claim 23, wherein the controller couples the capacitors from the zth bit to the (Nd-1)th bit to the first reference voltage, and generates the first digital code according to the operation of the capacitors from the (z-1)th bit to the 0th bit, comprising: The first ends of the capacitors from the (Nd-1)th to the 0th are coupled to an input voltage, and the second ends of the capacitors from the (Nd-1)th to the 0th are coupled to the first reference voltage; Disconnecting the first ends of the capacitors from the (Nd-1)th to the 0th from the input voltage; and The first digital code is generated by using the sequential approximate register analog-to-digital converter corresponding to the capacitors at the (z-1)th bit to the 0th bit. 25. The SAR ADC with calibration function as claimed in claim 24, wherein the controller performs the steps of coupling the capacitors of the (i+1)th to (Nd-1)th bits to the first reference voltage, coupling the capacitor of the i-th bit to the second reference voltage, and generating the second digital code according to the operation of the capacitors of the (i-1)th to the 0th bit, comprising: coupling the second ends of the capacitors at the (i+1)th to (Nd-1)th positions to the first reference voltage, and coupling the second end of the capacitor at the i-th position to the second reference voltage; and The second digital code is generated by using the sequential approximate register analog-to-digital converter corresponding to the capacitors from the (i-1)th bit to the 0th bit. 26. A successive approximate buffer analog-to-digital converter with a correction function, comprising: At least one Nd-bit capacitive digital-to-analog converter having Nd-bit capacitance, wherein Nd is a positive integer; a controller coupled to the at least one capacitive digital-to-analog converter, The controller is used to perform the following capacitance calibration procedure: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The at least one capacitive digital-to-analog converter comprises a first capacitive digital-to-analog converter and a second capacitive digital-to-analog converter, wherein the controller performs the step of coupling the second end of the i-th capacitor to the second reference voltage, comprising: The second end of the capacitor of the i-th bit of the first capacitive digital-to-analog converter is coupled to the second reference voltage; and The second end of the capacitor of the i-th bit of the second capacitive digital-to-analog converter is coupled to a third reference voltage. 27. A successive approximate buffer analog-to-digital converter with a correction function, comprising: At least one Nd-bit capacitive digital-to-analog converter having Nd-bit capacitance, wherein Nd is a positive integer; a controller coupled to the at least one capacitive digital-to-analog converter, The controller is used to perform the following capacitance calibration procedure: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The controller is further configured to calibrate the SAR analog-to-digital converter according to the capacitance weight of the capacitance at the i-th bit. The capacitance weight of the capacitor at the jth position is obtained according to the capacitance weights of the capacitors at the (j-1)th position to the i-th position, wherein Nd>j>i. 28. A successive approximate buffer analog-to-digital converter with a correction function, comprising: At least one Nd-bit capacitive digital-to-analog converter having Nd-bit capacitance, wherein Nd is a positive integer; a controller coupled to the at least one capacitive digital-to-analog converter, The controller is used to perform the following capacitance calibration procedure: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The successive approximation buffer analog-to-digital converter further comprises: The frequency reduction circuit is coupled between the controller and the comparator, and is used to omit the waiting period from the (Nd-1)th capacitor to the (i+1)th capacitor in the operation mode timing when calibrating the i-th capacitor. 29. A successive approximate buffer analog-to-digital converter with a correction function, comprising: At least one Nd-bit capacitive digital-to-analog converter having Nd-bit capacitance, wherein Nd is a positive integer; a controller coupled to the at least one capacitive digital-to-analog converter, The controller is used to perform the following capacitance calibration procedure: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The SAR ADC further includes a comparator, and the first digital code includes flicker noise and information of an offset of the comparator. 30. A successive approximate buffer analog-to-digital converter with a correction function, comprising: At least one Nd-bit capacitive digital-to-analog converter having Nd-bit capacitance, wherein Nd is a positive integer; a controller coupled to the at least one capacitive digital-to-analog converter, The controller is used to perform the following capacitance calibration procedure: The capacitors at the zth to (Nd-1)th positions are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors at the (z-1)th to 0th positions, wherein z is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the ith position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position, wherein i is an integer less than Nd, and z is less than i; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The controller subtracts the first digital code from the second digital code to generate a capacitance weight of the capacitance at the i-th bit. 31. A successive approximate buffer analog-to-digital converter with a correction function, comprising: At least one Nd-bit capacitive digital-to-analog converter having Nd-bit capacitance, wherein Nd is a positive integer; a controller coupled to the at least one capacitive digital-to-analog converter, The controller is used to perform the following capacitance calibration procedure: The capacitors from the i-th to the (Nd-1)-th bits are coupled to a first reference voltage, and a first digital code is generated according to the operation of the capacitors from the (i-1)-th to the 0-th bits, wherein i is an integer less than Nd; The capacitors at the (i+1)th to (Nd-1)th positions are coupled to the first reference voltage, the capacitor at the i-th position is coupled to the second reference voltage, and a second digital code is generated according to the operation of the capacitors at the (i-1)th to the 0th position; Generate a capacitance weight of the capacitor at the i-th bit according to the first digital code and the second digital code; and The SAR analog-to-digital converter is calibrated according to the capacitance weight of the capacitance of the i-th bit, The calibration timing of the capacitance calibration procedure is the same as the operation mode timing of the SAR ADC.