CN113131890A - Manufacturing method of packaging structure - Google Patents
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- CN113131890A CN113131890A CN201911399348.1A CN201911399348A CN113131890A CN 113131890 A CN113131890 A CN 113131890A CN 201911399348 A CN201911399348 A CN 201911399348A CN 113131890 A CN113131890 A CN 113131890A
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- H—ELECTRICITY
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- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
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- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00269—Bonding of solid lids or wafers to the substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
A method of manufacturing a package structure, comprising: providing a device wafer and a wafer-level covering substrate, wherein the device wafer and the wafer-level covering substrate are combined through a bonding layer positioned between the device wafer and the wafer-level covering substrate, the device wafer comprises a plurality of semiconductor chips, the semiconductor chips comprise an active area and an input/output electrode area, the semiconductor chips, the bonding layer and the wafer-level covering substrate form a cavity at the position of the active area, the input/output electrode is positioned outside the cavity, and the wafer-level covering substrate is made of lithium niobate or lithium tantalate; cutting the wafer-level covering substrate between the adjacent semiconductor chips by using a soft cutter to form chip-level covering substrates corresponding to the semiconductor chips one by one, wherein an included angle between the side wall of each chip-level covering substrate and the surface of each chip-level covering substrate, which is back to the device wafer, forms an obtuse angle; an interconnect layer is formed conformally covering the input/output electrode surface, the bonding layer, and the sidewalls of the chip-scale cover substrate and a portion of the top surface of the chip-scale cover substrate. The invention improves the yield of the packaging structure.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a packaging structure.
Background
In a semiconductor device, a cavity environment needs to be provided in an active region of a part of the device to ensure normal operation, and therefore, during device fabrication or packaging, an air gap needs to be formed in the active region of the device, such as a filter, a MEMS device, and the like.
Taking a Surface Acoustic Wave (SAW) filter as an example, the SAW filter is a special filter device that is made by utilizing the piezoelectric effect and the physical characteristics of the propagation of the SAW. In the SAW filter, a signal undergoes two electro-acoustic-electric conversions, thereby realizing a frequency-selective characteristic. The SAW filter has the advantages of high working frequency, simple manufacturing process, low manufacturing cost, high consistency of frequency characteristics and the like, and the application field of the SAW filter almost extends to the whole radio communication from the beginning military radar development to the present, and particularly, the development of the SAW technology is further promoted along with the high-speed development of the mobile communication technology.
In the packaging process of the present SAW filter, at least an upper cover is used, that is, the SAW filter chip is sealed by the upper cover, so that an air gap is formed in an active area of the SAW filter.
Disclosure of Invention
The embodiment of the invention provides a manufacturing method of a packaging structure, which can improve the yield of the packaging structure while reducing the process difficulty.
To solve the above problems, an embodiment of the present invention provides a method for manufacturing a package structure, including: providing a device wafer and a wafer-level covering substrate, wherein the device wafer and the wafer-level covering substrate are combined through a bonding layer positioned between the device wafer and the wafer-level covering substrate, the device wafer comprises a plurality of semiconductor chips, the semiconductor chips comprise active regions and input/output electrode regions, the semiconductor chips, the bonding layer and the wafer-level covering substrate surround a cavity at the position of the active regions, the input/output electrodes of the input/output electrode regions are positioned on the outer sides of the cavity, and the wafer-level covering substrate is made of lithium niobate or lithium tantalate; cutting the wafer-level covering substrates between the adjacent semiconductor chips by using a soft cutter to form a plurality of discrete chip-level covering substrates which are in one-to-one correspondence with the semiconductor chips, wherein the chip-level covering substrates expose input/output electrodes of the input/output electrode regions, and an included angle formed by the side walls of the chip-level covering substrates and the surfaces of the chip-level covering substrates, which are back to the device wafer, is an obtuse angle; forming an interconnect layer conformally covering the input/output electrodes of the input/output electrode regions, the bonding layer and the sidewalls of the chip-scale cover substrate, and a portion of the top surface of the chip-scale cover substrate.
The embodiment of the invention also provides a manufacturing method of the packaging structure, which comprises the following steps: providing a device wafer and a wafer-level covering substrate, wherein the device wafer and the wafer-level covering substrate are combined through a bonding layer positioned between the device wafer and the wafer-level covering substrate, the device wafer comprises a plurality of semiconductor chips, the semiconductor chips comprise active regions and input/output electrode regions, the semiconductor chips, the bonding layer and the wafer-level covering substrate enclose a cavity at the positions of the active regions, the input/output electrodes of the input/output electrode regions are positioned on the outer sides of the cavity, and the substrate of the device wafer is made of lithium niobate or lithium tantalate; cutting the device wafer at the junction of the adjacent semiconductor chips by using a soft cutter to form an interconnection opening in the device wafer, wherein the interconnection opening exposes an input/output electrode of the input/output electrode area of the adjacent semiconductor chip, and an included angle between the side wall of the interconnection opening and the surface of the device wafer, which faces away from the wafer-level covering substrate, is an obtuse angle; forming an interconnect layer conformally covering a surface of an input/output electrode of the input/output electrode region exposed by the interconnect opening, a sidewall of the interconnect opening, and a portion of a surface of the device wafer facing away from the wafer-level cover substrate.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, the wafer-level covering substrate between adjacent semiconductor chips is cut by using a soft cutter to form a plurality of discrete chip-level covering substrates which are in one-to-one correspondence with the semiconductor chips, the chip-level covering substrates expose input/output electrodes of input/output electrode regions, and an included angle between the side wall of each chip-level covering substrate and the surface of each chip-level covering substrate, which is back to the device wafer, forms an obtuse angle; on one hand, the soft knife can cut the wafer-level covering substrate made of lithium niobate or lithium tantalate, on the other hand, in the actual manufacturing process, by selecting the soft knife with a proper knife edge angle, an included angle between the side wall of the chip-level covering substrate and the surface of the chip-level covering substrate, which is opposite to the device wafer, is easy to form an obtuse angle, so that the cutting is performed by using the soft knife, the process difficulty of forming the chip-level covering substrate is reduced, in addition, the appearance of the side wall of the chip-level covering substrate is easy to meet the process requirements, the step coverage (step coverage) capacity of a subsequent interconnection layer is improved, and the forming quality and performance of the interconnection layer are correspondingly improved; in summary, the embodiment of the invention can improve the yield of the packaging structure while reducing the process difficulty.
According to the embodiment of the invention, a device wafer of which the substrate material is lithium niobate or lithium tantalate is cut by using a soft cutter, an interconnection opening is formed in the device wafer, the interconnection opening exposes an input/output electrode of an input/output electrode area of an adjacent semiconductor chip, and an included angle between the side wall of the interconnection opening and the surface of the device wafer, back to the wafer-level cover substrate, forms an obtuse angle; on one hand, the soft knife can cut lithium niobate or lithium tantalate materials, and on the other hand, in the actual manufacturing process, by selecting the soft knife with a proper knife edge angle, an included angle between the side wall of the interconnection opening and the surface of the device wafer, which faces away from the wafer-level covering substrate, is easy to form an obtuse angle, so that the cutting is performed by using the soft knife, the process difficulty of forming the interconnection opening is reduced, the side wall appearance of the interconnection opening is easy to meet the process requirement, the step coverage (step coverage) capability of a subsequent interconnection layer is improved, and the forming quality and performance of the interconnection layer are correspondingly improved; in summary, the embodiment of the invention can improve the yield of the packaging structure while reducing the process difficulty.
Drawings
Fig. 1 to 3 are schematic structural diagrams corresponding to steps in a manufacturing method of a package structure;
FIG. 4 is a flow chart of one embodiment of a method for fabricating a package structure according to the present invention;
fig. 5 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for manufacturing a package structure of the present invention;
fig. 14 to 16 are schematic structural diagrams corresponding to steps in another embodiment of the method for manufacturing a package structure of the present invention.
Detailed Description
As is known from the background art, for an air gap type semiconductor device, an air gap needs to be formed in an active region of the device. Taking the SAW filter as an example, the cavity is formed in the active region, so that the sound wave in the filter can propagate without interference, thereby ensuring the normal operation of the filter.
One common Packaging process for SAW filters is the Die-Sized SAW Packaging (DSSP) process. Referring to fig. 1 to 3, schematic structural diagrams corresponding to steps in a manufacturing method of a package structure are shown.
Referring to fig. 1, a device wafer 10 and a wafer-level cover substrate 30 are provided, the device wafer 10 and the wafer-level cover substrate 30 being joined by an adhesive layer 20 therebetween, the device wafer 10 comprising a plurality of semiconductor chips (not labeled) including an active region 11 and an input/output electrode region 12, the semiconductor chips, the adhesive layer 20 and the wafer-level cover substrate 30 enclosing a cavity (not labeled) at the location of the active region 11, the input/output electrodes of the input/output electrode region 12 being located outside the cavity.
Referring to fig. 2, the wafer-level cover substrate 30 between adjacent semiconductor chips is etched to form a plurality of discrete chip-level cover substrates 35 corresponding to the semiconductor chips one-to-one, and the chip-level cover substrates 35 expose the input/output electrodes of the input/output electrode regions 12.
Specifically, the chip-scale cover substrate 35, adhesive layer 20, and device wafer 10 enclose an opening 40.
Referring to fig. 3, an interconnection layer 50 is formed, the interconnection layer 50 conformally covering the surfaces of the input/output electrodes of the input/output electrode regions 12, the adhesive layer 20 and the sidewalls of the chip-scale cover substrate 35, and a portion of the top surface of the chip-scale cover substrate 35.
One particular way of performing the DSSP process is to use a wafer-level cover substrate 30 made of silicon. By selecting the wafer-level cover substrate 30 made of silicon, the wafer-level cover substrate 30 between adjacent semiconductor chips can be etched by using an etching process, and the included angle between the side wall of the chip-level cover substrate and the surface of the chip-level cover substrate, which faces away from the device wafer 10, can be adjusted easily by adjusting the parameters of the etching process, so that the process for forming the chip-level cover substrate is simpler.
However, the substrate material of the device wafer 10 corresponding to the SAW filter is usually lithium niobate (LiNbO)3) Or lithium tantalate (LiTaO)3) The difference between the thermal expansion coefficients of the two materials and silicon is large, so that the warpage of the device wafer 10 is increased, and the device wafer 10 is easily broken in the packaging process, or the problem of photolithography shift is caused in the subsequent process, and both the problems can cause the yield of the packaging structure to be reduced.
In order to improve the problem of large difference in thermal expansion coefficient, there is also a method of replacing the substrate of the wafer-level cover substrate with lithium niobate or lithium tantalate so that the substrate materials of the wafer-level cover substrate and the device wafer are matched.
However, the lithium niobate or lithium tantalate is hard, and the difficulty in etching the wafer-level cover substrate made of the two materials is high, so that the difficulty in forming the chip-level cover substrate is high, and the included angle between the side wall of the chip-level cover substrate and the surface of the chip-level cover substrate, which faces away from the device wafer, is difficult to adjust by the etching process, so that the verticality of the side wall of the opening surrounded by the chip-level cover substrate, the bonding layer and the device wafer is high, the step coverage of the interconnection layer is reduced, the performance of the interconnection layer is reduced, and accordingly, the yield of the packaging structure is reduced. If the step coverage of the interconnection layer is to be improved, the thickness of the interconnection layer needs to be increased, which in turn leads to high packaging cost.
Therefore, when the substrate is covered with the wafer level made of lithium niobate or lithium tantalate, the process difficulty is easily increased, and the yield of the package structure is reduced.
In order to solve the technical problem, an embodiment of the present invention provides a method for manufacturing a package structure, including: providing a device wafer and a wafer-level covering substrate, wherein the device wafer and the wafer-level covering substrate are combined through a bonding layer positioned between the device wafer and the wafer-level covering substrate, the device wafer comprises a plurality of semiconductor chips, the semiconductor chips comprise active regions and input/output electrode regions, the semiconductor chips, the bonding layer and the wafer-level covering substrate surround a cavity at the position of the active regions, the input/output electrodes of the input/output electrode regions are positioned on the outer sides of the cavity, and the wafer-level covering substrate is made of lithium niobate or lithium tantalate; cutting the wafer-level covering substrates between the adjacent semiconductor chips by using a soft cutter to form a plurality of discrete chip-level covering substrates which are in one-to-one correspondence with the semiconductor chips, wherein the chip-level covering substrates expose input/output electrodes of the input/output electrode regions, and an included angle formed by the side walls of the chip-level covering substrates and the surfaces of the chip-level covering substrates, which are back to the device wafer, is an obtuse angle; forming an interconnect layer conformally covering the input/output electrodes of the input/output electrode regions, the bonding layer and the sidewalls of the chip-scale cover substrate, and a portion of the top surface of the chip-scale cover substrate.
On one hand, the soft knife can cut the wafer-level covering substrate made of lithium niobate or lithium tantalate, on the other hand, in the actual manufacturing process, an included angle between the side wall of the chip-level covering substrate and the surface of the chip-level covering substrate, which faces away from the device wafer, is easy to form an obtuse angle by selecting the soft knife with a proper knife edge angle, so that the cutting is performed by using the soft knife, the process difficulty of forming the chip-level covering substrate is reduced, in addition, the appearance of the side wall of the chip-level covering substrate is easy to meet the process requirements, the step covering capacity of a subsequent interconnection layer is improved, and the forming quality and performance of the interconnection layer are correspondingly improved; in summary, the embodiment of the invention can improve the yield of the packaging structure while reducing the process difficulty.
Referring to fig. 4, a flow chart of an embodiment of a method for manufacturing a package structure of the present invention is shown. The manufacturing method of the package structure in this embodiment includes the following basic steps:
step S1: providing a device wafer and a wafer-level covering substrate, wherein the device wafer and the wafer-level covering substrate are combined through a bonding layer positioned between the device wafer and the wafer-level covering substrate, the device wafer comprises a plurality of semiconductor chips, the semiconductor chips comprise active regions and input/output electrode regions, the semiconductor chips, the bonding layer and the wafer-level covering substrate surround a cavity at the position of the active regions, the input/output electrodes of the input/output electrode regions are positioned on the outer sides of the cavity, and the wafer-level covering substrate is made of lithium niobate or lithium tantalate;
step S2: cutting the wafer-level covering substrates between the adjacent semiconductor chips by using a soft cutter to form a plurality of discrete chip-level covering substrates which are in one-to-one correspondence with the semiconductor chips, wherein the chip-level covering substrates expose input/output electrodes of the input/output electrode regions, and an included angle formed by the side walls of the chip-level covering substrates and the surfaces of the chip-level covering substrates, which are back to the device wafer, is an obtuse angle;
step S3: forming an interconnect layer conformally covering a surface of the input/output electrodes of the input/output electrode regions, the bonding layer and sidewalls of the chip-scale cover substrate, and a portion of the top surface of the chip-scale cover substrate.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for manufacturing a package structure of the present invention.
With combined reference to fig. 5 to 8, step S1 is executed to provide a device wafer 100 and a wafer-level cover substrate 300, the device wafer 100 and the wafer-level cover substrate 300 are combined by a bonding layer 200 therebetween, the device wafer 100 includes a plurality of semiconductor chips 105, the semiconductor chips 105 include an active area (active zone)110 and an input/output (I/O) electrode area 120, the semiconductor chips 105, the bonding layer 200, and the wafer-level cover substrate 300 enclose a cavity 130 at the position of the active area 110 (as shown in fig. 8), and an input/output electrode of the input/output electrode area 120 is located outside the cavity 130, wherein the material of the wafer-level cover substrate 300 is lithium niobate or lithium tantalate.
The device wafer 100 and the wafer-level cover substrate 300 are combined through the bonding layer 200 therebetween, so that wafer-level packaging is realized, which is beneficial to improving manufacturing efficiency, reducing manufacturing cost, and improving reliability of a packaging structure.
The above steps are described in detail below with reference to the accompanying drawings.
Referring to fig. 5, a device wafer 100 is provided, the device wafer 100 including a plurality of semiconductor chips 105, the semiconductor chips 105 including an active region, 110 and input/output electrode regions 120.
The device wafer 100 includes a plurality of semiconductor chips 105, thereby realizing wafer level packaging, which is beneficial to improving manufacturing efficiency, reducing manufacturing cost, and improving reliability of a packaging structure. For ease of illustration, the present embodiment illustrates only two semiconductor chips 105.
In this embodiment, the manufacturing method is used to form a filter, i.e., the semiconductor chip 105 is a filter chip.
Specifically, the filter chip may be a Surface Acoustic Wave (SAW) filter chip or a bulk acoustic wave (bulk acoustic wave) filter chip, wherein the bulk acoustic wave filter chip may include a reflection array type bulk acoustic wave (BAW-SMR) filter chip, a diaphragm type film bulk acoustic wave (FBAR) filter chip, or an air gap type film bulk acoustic wave (airgap) filter chip.
The surface acoustic wave is an elastic wave which is propagated by concentrating energy on the surface of a medium, wherein the acoustic wave is propagated in a limited depth on the surface of an object and is propagated along the interface between a solid and air; the bulk acoustic wave utilizes that when a bulk acoustic wave signal is transmitted in different media, the bulk acoustic wave signal is reflected at the junction of the two electrodes and air, and an air cavity is formed between the bulk acoustic wave and the surface of the carrier, so that the acoustic wave is limited in the piezoelectric oscillation cavity. Therefore, for both surface acoustic waves and bulk acoustic waves, it is necessary to form a closed cavity at the interface with the carrier to limit the propagation path of the acoustic wave.
In other embodiments, the manufacturing method may also be used to form other types of air gap semiconductor device package structures, as the case may be, for example: the semiconductor chip may be a MEMS chip, an image sensor chip, or a biosensor chip.
In this embodiment, a method for manufacturing an air gap type semiconductor device package structure is described by taking the semiconductor chip 105 as a saw filter chip as an example.
In this embodiment, the substrate of the device wafer 100 is a piezoelectric substrate (piezoelectric substrate), so that the saw filter chip can perform filtering processing by using a piezoelectric effect.
Therefore, the substrate material of the device wafer 100 is lithium niobate or lithium tantalate. Lithium niobate or lithium tantalate can provide very high electromechanical coupling coefficients and can be used to fabricate filters exhibiting a relative bandwidth of about 50%.
The active region 110 is used as a working region of the SAW filter for realizing a filtering function, a cavity needs to be formed above the active region 110 of the SAW filter chip to protect the active region 110, acoustic waves are limited in the cavity, and the cavity is used as a piezoelectric oscillation cavity, so that the normal operation of the SAW filter chip is guaranteed. Accordingly, the active region 110 includes a region where an interdigital transducer (IDT) is disposed.
In this embodiment, the number of the semiconductor chips 105 is plural, and the plural semiconductor chips 105 are integrated in the device wafer 100, so that the device wafer 100 includes plural active regions 110.
The input/output electrode region 120 is formed with input/output electrodes electrically connected to the interdigital transducers of the active region 110.
As an example, in each semiconductor chip 105, the number of the input/output electrode regions 120 is plural, and the plurality of input/output electrode regions 120 are located around the active region 110. For example, the semiconductor chips 105 have a square shape, and in each of the semiconductor chips 105, the active region 110 has a square shape, and the input/output electrode regions 120 are located at four corners of the active region 105.
Referring to fig. 6, a wafer-level cover substrate 300 is provided.
The wafer-level cover substrate 300 is used to form a plurality of discrete chip-level cover substrates after subsequent dicing processes.
The wafer-level cover substrate 300 and the device wafer 100 are subsequently bonded using a bonding layer having openings, at which the semiconductor chips 105 and the wafer-level cover substrate 300 enclose a cavity. After the wafer-level cover substrate 300 is subsequently diced, the chip-level cover substrates correspond to the semiconductor chips 105 one by one, and the chip-level cover substrates are used as cover plates of air-gap semiconductor devices, so that the cavities are used as air gaps, and a cavity working environment is provided.
In this embodiment, the material of the wafer-level cover substrate 300 is lithium niobate or lithium tantalate.
The substrate material of the device wafer 100 is lithium niobate or lithium tantalate, so that the problem of large difference in thermal expansion coefficient between the wafer-level cover substrate 300 and the device wafer 100 is solved by adopting the wafer-level cover substrate 300 made of lithium niobate or lithium tantalate, the warping problem of the device wafer 100 is solved, the probability of the device wafer 100 breaking in the packaging process is reduced, and the yield of the packaging structure is improved.
As an example, the wafer-level cover substrate 300 is the same material as the substrate of the device wafer 100, thereby matching the coefficient of thermal expansion between the wafer-level cover substrate 300 and the device wafer 100.
Referring to fig. 7, a bonding layer 200 is formed on the device wafer 100, and an opening 201 is formed in the bonding layer 200, where the opening 201 is adapted to correspond to the active region 110 (shown in fig. 5) in a one-to-one manner.
The bonding layer 200 is formed on the device wafer 100 to implement a wafer-level forming manner, thereby improving the efficiency of forming the bonding layer 200. Moreover, the bonding layer 200 is formed on the device wafer 100, which is beneficial to improving the alignment precision.
The material of the bonding layer 200 is a material that can be patterned and has adhesive properties for bonding the device wafer 100 and the wafer-level cover substrate 300 (shown in fig. 6).
The openings 201 formed in the bonding layer 200 correspond to the active regions 110 of the semiconductor chips 105 (as shown in fig. 5) one by one, so that after the bonding layer 200 is subsequently used to bond the device wafer 100 and the wafer-level cover substrate 300, the wafer-level cover substrate 300 and the semiconductor chips 105 enclose a cavity at the positions of the openings 201.
In this embodiment, the bonding layer 200 is made of a photosensitive material, and therefore, the opening 201 may be formed in a patterning manner by using a photolithography process, which is not only beneficial to reducing the process complexity for forming the opening 201, but also beneficial to improving the topography quality, the dimensional accuracy, and the position accuracy of the opening 201, and in addition, can also reduce the damage to the semiconductor chip 105 in the patterning process, thereby ensuring the integrity of the semiconductor chip 105.
In this embodiment, the material of the bonding layer 200 is a dry film (dry film). The dry film is a sticky photosensitive polymer material used in semiconductor chip packaging or printed circuit board manufacturing, and the dry film is a permanent bonding film, and the bonding strength of the dry film is high, which improves the bonding force between the subsequent wafer-level cover substrate 300 and the device wafer 100, which correspondingly improves the sealing property of the cavity. In other embodiments, the material of the bonding layer may also be Polyimide (PI), benzocyclobutene (BCB), or Polybenzoxazole (PBO).
Specifically, the step of forming the bonding layer 200 includes: forming a bonding material layer (not shown) on the device wafer 100, wherein the bonding material layer is made of a photosensitive material; the bonding material layer is patterned by using a photolithography process, and the patterned bonding material layer is used as the bonding layer 200.
In this embodiment, the bonding layer 200 has a plurality of openings 201 formed therein, and the openings 201 are adapted to correspond to the active regions 110 of the semiconductor chip 105 one to one.
In this embodiment, the bonding layer 200 exposes the input/output electrode regions 120, so as to prepare for subsequently leading out the input/output electrode regions 120.
It should be noted that, in this embodiment, on the premise of ensuring the bonding force between the device wafer 100 and the wafer-level cover substrate 300, the bonding layer 200 covers the device wafer 100 in a smaller area, that is, the bonding layer 200 exposes not only the semiconductor chip 105 at the position of the opening 201, but also the edge area of the semiconductor chip 105, so as to facilitate the subsequent formation of an interconnection layer.
Specifically, in the same semiconductor chip 105, the bonding layer 200 is located between the active region 110 and the input/output electrode region 120. Accordingly, an initial interconnect opening 202 is also formed in the bonding layer 200. The initial interconnect opening 202 spans adjacent input/output electrode regions 120 in two adjacent semiconductor chips 105. The initial interconnect opening 202 is used in preparation for a subsequent formation of an interconnect opening.
In other embodiments, the bonding layer may also be formed on the wafer-level cover substrate, and the forming position of the bonding layer on the wafer-level cover substrate is determined according to the relative position relationship between the bonding layer and the semiconductor chip. Accordingly, in the process of forming the bonding layer, a bonding material layer is formed on the wafer-level cover substrate.
In this embodiment, the thickness of the bonding layer 200 directly determines the thickness of a cavity formed subsequently, and the thickness of the cavity is related to the resonant frequency of the filter, so the thickness of the bonding layer 200 can be set according to the resonant frequency required by the filter. As an example, the bonding layer 200 may have a thickness of 2 μm to 200 μm, for example, 50 μm or 80 μm or 100 μm.
Referring to fig. 8, the bonding layer 200 is used to bond the wafer-level cover substrate 300 and the device wafer 100, the semiconductor chip 105 (shown in fig. 5) and the wafer-level cover substrate 300 enclose a cavity 130 at the position of the opening 201 (shown in fig. 7), the cavity 130 exposes at least a portion of the active region 110, and the input/output electrodes of the input/output electrode regions 120 are located outside the cavity 130.
The input/output electrodes of the input/output electrode regions 120 are located outside the cavity 130 in preparation for the subsequent formation of an interconnect layer electrically connected to the input/output electrodes.
The bonding layer 200 has viscosity, so that after the wafer-level cover substrate 300 is combined with the device wafer 100, the wafer-level cover substrate 300 functions as a cover plate, the wafer-level cover substrate 300 and the semiconductor chip 105 enclose a cavity 130 at the position of the opening 201, that is, the cavity 130 is aligned with the active region 110, and the cavity 130 is used as an air gap, so as to provide a cavity working environment for the active region 110, which not only simplifies the packaging process (and accordingly improves the manufacturing efficiency), but also reduces the packaging volume.
Specifically, the wafer-level cover substrate 300 is placed on the bonding layer 200, thereby bonding the wafer-level cover substrate 300 and the device wafer 100.
As an example, the area of the cavity 130 is equal to the area of the active region 110 of the semiconductor chip 105, and the cavity 130 is completely aligned with the active region 110. In other embodiments, the area of the cavity may not be equal to the area of the active region, as long as the cavity exposes at least a portion of the active region.
After the wafer-level cover substrate 300 is bonded to the device wafer 100, the manufacturing method further includes: the device wafer 100 is attached to the adhesive film layer 400.
Subsequently, the wafer-level cover substrate 300 needs to be cut, and the adhesive film layer 400 is used to provide a process platform and mechanical support for the cutting.
The viscosity of the glue film layer 400 should not be too high to facilitate subsequent separation of the glue film layer 400 from the device wafer 100. Thus, the device wafer 100 is temporarily bonded to the adhesive film layer 400.
In this embodiment, the adhesive film layer 400 is a uv (ultraviolet) adhesive film. The UV adhesive film has a high viscosity before being irradiated by ultraviolet light, and the viscosity is significantly reduced after being irradiated by ultraviolet light, so that the viscosity between the adhesive film layer 400 and the device wafer 100 is easily degraded, thereby removing the adhesive film layer 400.
Specifically, the adhesive film layer 400 is further attached to the bottom of the wafer frame 410 with a larger diameter, and passes through the wafer frame 410 to play a role in stretching the film.
Referring to fig. 9 and 10 in combination, step S2 is performed to cut the wafer-level cover substrate 300 between adjacent semiconductor chips 105 (shown in fig. 5) by using a soft knife 420 (shown in fig. 9) to form a plurality of discrete chip-level cover substrates 310 (shown in fig. 10) corresponding to the semiconductor chips 105 one by one, the chip-level cover substrates 310 expose the input/output electrodes of the input/output electrode regions 120, and an included angle α (shown in fig. 10) between a sidewall of the chip-level cover substrate 310 and a surface of the chip-level cover substrate 310 facing away from the device wafer 100 is an obtuse angle.
On one hand, the soft knife 420 can cut the wafer-level cover substrate 300 made of lithium niobate or lithium tantalate, and on the other hand, in the actual manufacturing process, by selecting the soft knife 420 with a proper knife edge angle, an included angle α between the side wall of the chip-level cover substrate 300 and the surface of the chip-level cover substrate 310 facing away from the device wafer 100 is easy to form an obtuse angle, so that the soft knife 420 is used for cutting, the process difficulty of forming the chip-level cover substrate 310 is reduced, and the appearance of the side wall of the chip-level cover substrate 310 is easy to meet the process requirements, so that the step coverage capability of subsequent interconnection layers is improved, and the formation quality and the electrical property of the interconnection layers are correspondingly improved; in summary, the embodiment of the invention can improve the yield of the packaging structure while reducing the process difficulty.
The chip-scale cover substrates 310 correspond to the semiconductor chips 105 one by one, so as to prepare for forming an air-gap semiconductor device packaging structure.
Adjacent chip-scale cover substrates 310, bonding layers 200 underlying the chip-scale cover substrates 310, and device wafers 100 enclose interconnect openings 320 (shown in fig. 10) at the location of the initial interconnect openings 202 (shown in fig. 7), the interconnect openings 320 spanning adjacent input/output electrode regions 120 in adjacent chip-scale cover substrates 310, the interconnect openings 320 for providing spatial locations for formation of subsequent interconnect layers.
In this embodiment, along the direction that the chip-scale cover substrate 310 points to the device wafer 100, the longitudinal cross-sectional shape of the chip-scale cover substrate 310 is trapezoidal, that is, the side wall of the chip-scale cover substrate 310 and the included angle α of the chip-scale cover substrate 310 back to the surface of the device wafer 100 are obtuse angles. Accordingly, the size (not labeled) of the top opening of the interconnection opening 320 is larger than the size (not labeled) of the bottom opening thereof, which is beneficial to reducing the process difficulty of the subsequent formation of the interconnection layer and improving the step coverage capability of the interconnection layer, thereby improving the formation quality and the electrical property of the interconnection layer and further improving the yield of the package structure.
It should be noted that during the cutting process, the soft knife 420 can also move in the horizontal plane direction, so that the opening size of the interconnection opening 320 meets the process requirement.
In this embodiment, after the soft knife 420 is used to cut the wafer-level cover substrate 300 between the adjacent semiconductor chips 105 (as shown in fig. 5), the included angle α between the sidewall of the chip-level cover substrate 310 and the surface of the chip-level cover substrate 310 facing away from the device wafer 100 should not be too small or too large. If the included angle alpha is too small, the step coverage capability of a subsequent interconnection layer is easily reduced, and the formation quality and the electrical property of the interconnection layer are not favorably improved; if the included angle α is too large, the planar size of the chip-scale cover substrate 310 is too small, so that the bonding force between the chip-scale cover substrate 310 and the bonding layer 200 is reduced, and the yield of the package structure is reduced. For this reason, in the present embodiment, an included angle α between the sidewall of the chip-scale cover substrate 310 and the surface of the chip-scale cover substrate 310 facing away from the device wafer 100 is 120 degrees to 150 degrees.
In this embodiment, the cutting is performed by using a mechanical cutting method, and the cutting tool used for the mechanical cutting is a soft knife 420. The soft knife 420 is assembled on a cutter head of the cutting equipment, the device wafer 100 is arranged on a workbench of the cutting equipment, and the soft knife 420 is driven by the cutter head to cut the wafer-level covering substrate 300 on the workbench.
In the industrial field, grooving or cutting machining is often required, a cutter used in grooving or cutting machining is usually a thin grinding wheel, and in order to distinguish different grinding wheels, the thin stone grinding wheel is conventionally divided into a soft cutter and a hard cutter. Among them, the ring-sheet grinding wheel is generally called a soft cutter, the grinding wheel combined with the aluminum alloy tool rest into a whole is called a hard cutter, the material of the grinding wheel comprises an adhesive, and the type of the adhesive of the soft cutter is various, so that the soft cutter with different adhesives can be selected for cutting different materials, and the process flexibility is high
In this embodiment, the material of the soft blade 420 includes diamond. The diamond hardness is high, which can improve the sharpness of the soft knife 420, and is beneficial to improving the cutting efficiency and the side wall smoothness of the chip-level cover substrate 310.
In the material of the soft cutter 420, the particle size of the diamond particles is not necessarily too small, and is not necessarily too large. If the particle diameter of the diamond particles is too small, the cutting speed and cutting ability are easily reduced, and accordingly the side wall smoothness of the chip-scale cover substrate 310 is also easily reduced; if the particle diameter of the diamond particles is too large, a chipping problem is likely to occur. For this reason, in the present embodiment, in the material of the soft blade 420, the particle diameter of diamond is 1 to 3 micrometers.
In this embodiment, an included angle α between the sidewall of the chip-scale cover substrate 310 and the surface of the chip-scale cover substrate 310 facing away from the device wafer 100 is 120 to 150 degrees, and thus, in order to make the sidewall profile of the chip-scale cover substrate 310 meet the process requirements, the blade angle of the soft knife 420 is 30 to 60 degrees. The blade angle of the soft knife 420 is matched with the included angle alpha.
It should be noted that, during the cutting process, the cutting speed should not be too low, and should not be too high. If the cutting speed is too low, the abrasion of the soft knife 420 is relatively large, and the output of the equipment is low; if the cutting speed is too high, the edge chipping problem is serious, so that the cutting quality is poor, and the formation quality of a subsequent interconnection layer is poor. For this purpose, in the present embodiment, the cutting speed is 5mm/s to 15mm/s, for example 10 mm/s.
It should also be noted that the shaft rotation speed should not be too low or too high during the cutting process. If the shaft rotating speed is too low, the edge breakage problem is serious, so that the cutting quality is poor, and the formation quality of a subsequent interconnection layer is poor; if the shaft rotation speed is too large, the process stability of the cutting process is poor, which easily results in that the top opening size of the interconnect opening 320 cannot be secured. For this reason, in the present embodiment, the shaft rotation speed is 10000rpm to 30000rpm, for example, 15000rpm, 20000rpm, 25000 rpm.
In this embodiment, in order to ensure that the wafer-level cover substrate 300 can be completely cut, i.e., to ensure that the input/output electrodes of the input/output electrode regions 120 can be exposed, the longitudinal feed of the cutting process is greater than the thickness of the wafer-level cover substrate 300.
In this embodiment, in order to ensure that the wafer-level cover substrate 300 can be completely cut, the longitudinal feed amount of the cutting process is greater than the thickness of the wafer-level cover substrate 300, and the difference between the longitudinal feed amount of the cutting process and the thickness of the wafer-level cover substrate 300 is greater than or equal to 5 μm.
However, the difference between the amount of vertical feed of the dicing process and the thickness of the wafer-level cover substrate 300 is not necessarily large. If the difference is too large, it is liable that the input/output electrodes of the input/output electrode region 120 are damaged during the cutting process.
Therefore, in the present embodiment, the difference between the vertical feed of the dicing process and the thickness of the wafer-level cover substrate 300 is 5 to 10 μm. In which the thickness of the dry film is generally at least 15 micrometers, and thus, by setting the difference between the longitudinal feed amount of the dicing process and the thickness of the wafer-level cover substrate 300 to be 5 micrometers to 10 micrometers, the probability of damage to the input/output electrodes of the input/output electrode region 120 is low.
Referring to fig. 11 in combination, it should be noted that after the soft knife 420 is used to perform the cutting process on the wafer-level cover substrate 300 (shown in fig. 9) between the adjacent semiconductor chips 105 (shown in fig. 5), the manufacturing method further includes: the adhesive film layer 400 is removed (as shown in fig. 10).
The subsequent process further includes forming an interconnection layer, and the glue film layer 400 is removed first to prevent contamination to a machine required for forming the interconnection layer.
Specifically, the adhesive film layer 400 is irradiated with ultraviolet light to reduce the adhesion between the adhesive film layer 400 and the device wafer 100, thereby removing the adhesive film layer 400.
With combined reference to fig. 12-13, step S3 is performed to form an interconnect layer 520 (shown in fig. 13), the interconnect layer 520 conformally covering the surfaces of the input/output electrodes of the input/output electrode regions 120, the bonding layer 200 and the sidewalls of the chip-scale cover substrate 310, and a portion of the top surface of the chip-scale cover substrate 310.
The interconnect layer 520 leads out the input/output electrodes of the input/output electrode regions 120 in preparation for a subsequent electrical connection process, for example, conductive bumps may be subsequently formed on the interconnect layer 520 on the top surface of the chip-scale cover substrate 310 in preparation for a subsequent flip chip bonding.
In this embodiment, the interconnection layer 520 is a redistribution layer (RDL), and the RDL process is selected to reduce the process cost.
The material of the interconnect layer 520 may include one or more of copper, aluminum, nickel, gold, silver, and titanium. In this embodiment, the redistribution layer 410 is made of copper.
It should be noted that, in each semiconductor chip 105 (as shown in fig. 5), the number of the input/output electrode regions 120 is plural, and therefore, in each semiconductor chip 105, the interconnection layers 520 are isolated from each other and are connected to the electrodes of the input/output electrode regions 120 in a one-to-one correspondence, so that voltages can be applied to the electrodes of the corresponding input/output electrode regions 120, respectively.
A specific formation step of the interconnect layer 520 is described in detail below with reference to the accompanying drawings.
Referring to fig. 12, a seed layer 500 is formed, the seed layer 500 conformally covering the surface of the device wafer 100 exposed by the wafer-level cover substrate 310, the sidewalls of the bonding layer 200, and the sidewalls and top surface of the chip-level cover substrate 310.
The seed layer 500 is used to provide a process foundation for the formation of subsequent interconnect layers.
As an example, the seed layer 500 includes a titanium layer and a copper layer on the titanium layer, and the seed layer 500 is formed by using a physical vapor deposition process.
In this embodiment, an included angle α (as shown in fig. 10) between the sidewall of the chip-scale cover substrate 310 and the surface of the chip-scale cover substrate 310 facing away from the device wafer 100 is an obtuse angle, so that the step coverage of the seed layer 500 is better. Correspondingly, the step coverage of the seed layer 500 can be ensured without forming the seed layer 500 with overlarge thickness, which is beneficial to reducing the process cost price.
With continued reference to fig. 12, a photoresist layer 510 is formed on the seed layer 500, and a pattern opening (not labeled) is formed in the photoresist layer 510, and the pattern opening exposes the input/output electrode surface of the input/output electrode region 120, the bonding layer 200, the sidewalls of the chip-scale cover substrate 310, and a portion of the seed layer 500 on the top surface of the chip-scale cover substrate 310.
The pattern openings in the photoresist layer 510 are used to define the locations where interconnect layers are formed.
Specifically, the patterned photoresist layer 510 is formed using a photolithography process including coating photoresist, exposure, and development.
Referring to fig. 13, an interconnect layer 520 is formed on the seed layer 500 exposed by the pattern openings (not labeled).
The interconnect layer 520 is formed only on the surface of the seed layer 500, so that the interconnect layer 520 is formed on the exposed region of the photoresist layer 510 (shown in fig. 12).
In this embodiment, the interconnect layer 520 is formed by an electroplating process.
In this embodiment, after the interconnection layer 520 is formed, the photoresist layer 510 is removed by an ashing process; after the photoresist layer 510 is removed, the seed layer 500 exposed by the interconnect layer 520 is removed.
Similarly, the step coverage of the interconnection layer 520 is better because the included angle α (as shown in fig. 10) between the sidewall of the chip-scale cover substrate 310 and the surface of the chip-scale cover substrate 310 facing away from the device wafer 100 is an obtuse angle. Accordingly, the step coverage is ensured without forming the interconnection layer 520 with an excessive thickness, which is beneficial to reducing the process cost price.
It should be noted that the subsequent process further includes cutting the formed package structure to form a plurality of semiconductor devices. For example: each semiconductor device includes a semiconductor chip 105.
Fig. 14 to 16 are schematic structural diagrams corresponding to steps in another embodiment of the method for manufacturing a package structure of the present invention.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: and cutting the device wafer by adopting a soft cutter.
Referring to fig. 14, a device wafer 600 and a wafer-level cover substrate 800 are provided, the device wafer 600 and the wafer-level cover substrate 800 are combined through a bonding layer 700 located therebetween, the device wafer 600 includes a plurality of semiconductor chips 605, the semiconductor chips 605 include active regions 610 and input/output electrode regions 620, the semiconductor chips 605, the bonding layer 700 and the wafer-level cover substrate 800 enclose a cavity 630 at the position of the active regions 610, input/output electrodes of the input/output electrode regions 620 are located outside the cavity 630, wherein a material of a substrate of the device wafer 600 is lithium niobate or lithium tantalate.
In this embodiment, the substrate material of the device wafer 600 is lithium niobate or lithium tantalate, and the material of the wafer-level cover substrate 800 is lithium niobate or lithium tantalate.
As an example, in the same semiconductor chip 605, the bonding layer 700 is located between the active region 610 and the input/output electrode region 620. In other embodiments, the bonding layer may also cover the input/output electrode regions.
In this embodiment, after the device wafer 600 and the wafer-level cover substrate 800 are combined by the bonding layer 700 located therebetween, the method for manufacturing the package structure further includes: the wafer-level cover substrate 800 is attached to the adhesive film layer 640.
Subsequently, the device wafer 600 needs to be cut, and the adhesive film layer 640 is used to provide a process platform and a mechanical support for the cutting. In this embodiment, the adhesive film layer 640 is a UV adhesive film.
Specifically, the adhesive film layer 640 is further attached to the bottom of the wafer frame 650 with a larger diameter, and passes through the wafer frame 650 to play a role of stretching the film.
For specific descriptions of the device wafer 600, the wafer-level cover substrate 800, the bonding layer 700, and the adhesive film layer 640, reference may be made to corresponding descriptions in the foregoing embodiments, and no further description is given here.
Referring to fig. 15, a soft knife is used to cut the device wafer 600 at the interface between adjacent semiconductor chips 605 (shown in fig. 14), so as to form an interconnection opening 660 in the device wafer 600, the interconnection opening 660 exposes the input/output electrodes of the input/output electrode regions 620 adjacent to the semiconductor chips 605, and an included angle β between the side wall of the interconnection opening 660 and the surface of the device wafer 600 facing away from the wafer-level cover substrate 800 is an obtuse angle.
The interconnect opening 660 exposes input/output electrodes of the input/output electrode regions 620 adjacent to the semiconductor chip 605, thereby providing a spatial location for subsequently forming interconnect layers that are electrically connected to the input/output electrodes of the input/output electrode regions 620.
An included angle β between the sidewall of the interconnection opening 660 and the surface of the device wafer 600 facing away from the wafer-level cover substrate 800 is an obtuse angle, which is beneficial to reducing the process difficulty of forming the interconnection layer subsequently and improving the step coverage capability of the interconnection layer, thereby improving the formation quality and the electrical property of the interconnection layer and further improving the yield of the package structure.
In this embodiment, the substrate material of the device wafer 600 is lithium niobate or lithium tantalate, the material of the lithium niobate or lithium tantalate is hard, the soft knife can cut the lithium niobate or lithium tantalate, and in the actual manufacturing process, by selecting the soft knife with a proper knife edge angle, an included angle β between the sidewall of the interconnection opening 660 and the surface of the device wafer 600 facing away from the wafer-level cover substrate 800 is easy to form an obtuse angle, so that the cutting is performed by using the soft knife, the process difficulty in forming the interconnection opening 660 is reduced, and the sidewall morphology of the interconnection opening 660 is easy to meet the process requirements, so that the step coverage capability of the subsequent interconnection layer is improved, and the formation quality and the electrical property of the interconnection layer are correspondingly improved; in summary, the embodiment of the invention can improve the yield of the packaging structure while reducing the process difficulty.
For the specific description of the cutting process, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated here.
Referring to fig. 16, an interconnect layer 900 is formed, the interconnect layer 900 conformally covering the surfaces of the input/output electrodes of the input/output electrode regions 620 exposed by the interconnect openings 660, the sidewalls of the interconnect openings 900, and the portion of the surface of the device wafer 600 facing away from the wafer-level cover substrate 800.
For a detailed description of the interconnect layer 900 and the formation process thereof, reference may be made to the corresponding description in the foregoing embodiments, and further description is omitted here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of manufacturing a package structure, comprising:
providing a device wafer and a wafer-level covering substrate, wherein the device wafer and the wafer-level covering substrate are combined through a bonding layer positioned between the device wafer and the wafer-level covering substrate, the device wafer comprises a plurality of semiconductor chips, the semiconductor chips comprise active regions and input/output electrode regions, the semiconductor chips, the bonding layer and the wafer-level covering substrate surround a cavity at the position of the active regions, the input/output electrodes of the input/output electrode regions are positioned on the outer sides of the cavity, and the wafer-level covering substrate is made of lithium niobate or lithium tantalate;
cutting the wafer-level covering substrates between the adjacent semiconductor chips by using a soft cutter to form a plurality of discrete chip-level covering substrates which are in one-to-one correspondence with the semiconductor chips, wherein the chip-level covering substrates expose input/output electrodes of the input/output electrode regions, and an included angle formed by the side walls of the chip-level covering substrates and the surfaces of the chip-level covering substrates, which are back to the device wafer, is an obtuse angle;
forming an interconnect layer conformally covering a surface of the input/output electrodes of the input/output electrode regions, the bonding layer and sidewalls of the chip-scale cover substrate, and a portion of the top surface of the chip-scale cover substrate.
2. The method of manufacturing of claim 1, wherein the wafer-level cover substrate is the same material as a substrate of the device wafer.
3. The method of manufacturing of claim 1, wherein after bonding the wafer-level cover substrate and the device wafer using the bonding layer, the method further comprises, before performing a dicing process on the wafer-level cover substrate between adjacent semiconductor chips using a soft knife: attaching the device wafer to a glue film layer;
after the wafer-level cover substrate between the adjacent semiconductor chips is cut by the soft knife, before the interconnection layer is formed, the manufacturing method further includes: and removing the adhesive film layer.
4. The manufacturing method of claim 1, wherein the step of forming the interconnect layer comprises: forming a seed layer, wherein the seed layer conformally covers the surface of the device wafer exposed by the wafer-level covering substrate, the side wall of the bonding layer, and the side wall and the top surface of the chip-level covering substrate;
forming a photoresist layer on the seed layer, wherein a pattern opening is formed in the photoresist layer, and the pattern opening exposes the surface of an input/output electrode positioned in the input/output electrode area, the side walls of the bonding layer and the chip-level covering substrate, and the seed layer on part of the top surface of the chip-level covering substrate;
forming an interconnection layer on the seed layer exposed by the pattern opening;
removing the photoresist layer;
and removing the seed layer exposed by the interconnection layer after removing the photoresist layer.
5. The manufacturing method according to claim 1 or 4, wherein after the dicing process is performed on the wafer-level cover substrate between the adjacent semiconductor chips by using a soft knife, an angle between a side wall of the chip-level cover substrate and a surface of the chip-level cover substrate facing away from the device wafer is 120 degrees to 150 degrees.
6. The method of manufacturing of claim 1 wherein the material of the soft knife comprises diamond.
7. The manufacturing method according to claim 6, wherein the particle size of the diamond is 1 to 3 μm.
8. The method of manufacturing according to claim 5, wherein the blade angle of the soft knife is 30 to 60 degrees.
9. The manufacturing method according to claim 1, wherein in the step of performing the dicing process on the wafer-level cover substrate between the adjacent semiconductor chips by using a soft blade, the process parameters of the dicing process include: the cutting speed is 5mm/s to 15mm/s and the shaft rotation speed is 10000rpm to 30000 rpm.
10. The manufacturing method according to claim 1, wherein a longitudinal feed amount of the dicing process is larger than a thickness of the wafer-level cover substrate, and a difference between the longitudinal feed amount of the dicing process and the thickness of the wafer-level cover substrate is 5 to 10 μm.
11. The manufacturing method according to claim 3, wherein the adhesive film layer comprises a UV adhesive film.
12. The manufacturing method according to claim 4, wherein the seed layer is formed by a physical vapor deposition process, and the interconnect layer is formed by an electroplating process.
13. The method of manufacturing of claim 1, wherein the step of bonding the device wafer and the wafer-level cover substrate with the bonding layer therebetween comprises:
forming a bonding layer having adhesion on the device wafer or the wafer-level cover substrate, the bonding layer having an opening formed therein, the opening adapted to correspond to the active region;
and combining the wafer-level cover substrate and the device wafer by using the bonding layer, wherein the semiconductor chip and the wafer-level cover substrate enclose a cavity at the position of the opening.
14. The method of manufacturing of claim 13, wherein the step of forming the bonding layer comprises: forming a bonding material layer on the device wafer or the wafer-level cover substrate, wherein the bonding material layer is made of photosensitive material;
and patterning the bonding material layer by utilizing a photoetching process, wherein the patterned bonding material layer is used as a bonding layer.
15. The manufacturing method according to claim 1, wherein a material of the bonding layer is a dry film, polyimide, benzocyclobutene, or polybenzoxazole.
16. The method of manufacturing of claim 1, wherein the semiconductor chip comprises a filter chip.
17. A method of manufacturing a package structure, comprising:
providing a device wafer and a wafer-level covering substrate, wherein the device wafer and the wafer-level covering substrate are combined through a bonding layer positioned between the device wafer and the wafer-level covering substrate, the device wafer comprises a plurality of semiconductor chips, the semiconductor chips comprise active regions and input/output electrode regions, the semiconductor chips, the bonding layer and the wafer-level covering substrate enclose a cavity at the positions of the active regions, the input/output electrodes of the input/output electrode regions are positioned on the outer sides of the cavity, and the substrate of the device wafer is made of lithium niobate or lithium tantalate;
cutting the device wafer at the junction of the adjacent semiconductor chips by using a soft cutter to form an interconnection opening in the device wafer, wherein the interconnection opening exposes an input/output electrode of the input/output electrode area of the adjacent semiconductor chip, and an included angle between the side wall of the interconnection opening and the surface of the device wafer, which faces away from the wafer-level covering substrate, is an obtuse angle;
forming an interconnect layer conformally covering a surface of an input/output electrode of the input/output electrode region exposed by the interconnect opening, a sidewall of the interconnect opening, and a portion of a surface of the device wafer facing away from the wafer-level cover substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113922783A (en) * | 2021-09-30 | 2022-01-11 | 电子科技大学 | Packaging structure of surface acoustic wave filter |
| CN118157618A (en) * | 2024-05-09 | 2024-06-07 | 苏州科阳半导体有限公司 | Wafer packaging structure and method thereof, filter packaging method and filter structure |
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