CN113130650B - Power semiconductor device and preparation process thereof - Google Patents

Abstract

In the power semiconductor device and the manufacturing process thereof provided by the embodiments of the present invention, the power semiconductor device is provided with a first conductivity type well region in the first conductivity type semiconductor layer, and a second conductivity type well region is provided in the first conductivity type well region, And the second conductive type well region is completely surrounded by the first conductive type well region, which can reduce the output capacitance (Coss) of the power semiconductor device and improve the ratio of its input capacitance (Ciss) to output capacitance (Coss), that is, Ciss The value of /Coss can also reduce the electric field of the gate oxide layer, and ultimately improve the stability of the device.

Description

Power semiconductor device and its manufacturing process

technical field

The present invention relates to the technical field of semiconductor devices, and more particularly, to a power semiconductor device and a manufacturing process thereof.

Background technique

Power metal oxide semiconductor field effect transistors ("MOSFETs") are a well-known type of semiconductor transistor that can be used as switching devices in high power applications. Power MOSFETs can be turned on or off by applying a gate bias to the gate electrode of the device. When the power MOSFET is turned on (ie it is in its "on state"), current is conducted through the channel of the MOSFET. When the bias is removed from the gate electrode (or reduced below a threshold level), current stops conducting through the channel. For example, an n-type MOSFET turns on when a gate bias sufficient to form a conductive n-type inversion layer in the p-type channel region of the device is applied. The n-type inversion layer electrically connects the n-type source and drain regions of the MOSFET, thereby allowing for majority carrier conduction between them.

A thin oxide gate insulating layer separates the gate electrode of the power MOSFET from the channel region. Since the gate of the MOSFET is isolated from the channel region, a minimum gate current is required to keep the MOSFET in its on state or to switch the MOSFET between its on state and its off state. Since the gate together with the channel region forms a capacitor, the gate current is kept small during switching. Therefore, only minimal charge and discharge currents are required during switching, allowing for lower complexity gate drive circuits. Furthermore, since MOSFETs are unipolar devices in which current conduction occurs entirely through majority carrier transport, MOSFETs can exhibit very high switching speeds. However, the drift region of power MOSFETs can exhibit relatively high on-resistance due to lack of minority carrier injection. This increased resistance may limit the forward current density achievable with power MOSFETs. Also, in the case of using a MOSFET, the gate oxide of the MOSFET may deteriorate over time.

Bipolar junction transistors ("BJTs") are another well-known type of semiconductor device that can be used as switching devices in high power applications. As known to those skilled in the art, a BJT consists of two p-n junctions formed in close proximity to each other in a semiconductor material. In operation, charge carriers enter a first region of the semiconductor material (which is called the emitter) adjacent to one of the p-n junctions. Most of the charge carriers leave the device from a second region of the semiconductor material adjacent to another p-n junction, which is called the collector. Collectors and emitters are formed in regions of the semiconductor material having the same conductivity type. A relatively thin third region of the semiconductor material, called the base, is located between the collector and the emitter and has an opposite conductivity type to that of the collector and emitter. Therefore, the two p-n junctions of the BJT are formed where the collector meets the base and where the base meets the emitter. By passing a small current through the base of the BJT, a proportionally larger current flows from the emitter to the collector.

A BJT is a current controlled device because the BJT is turned "on" by passing current through the base of the transistor (ie it is biased so that current flows between the emitter and collector). For example, in an NPN BJT (ie, a BJT with n-type collector and emitter regions and a p-type base region), the base-emitter p-n junction is typically forward-biased by applying a positive voltage to the base. The transistor is turned on. When the device is biased in this way, holes flow into the base of the transistor where they are injected into the emitter. Since the base is a p-type region, holes are called "majority carriers" and holes are "normal" charge carriers in such a region. At the same time, electrons are injected from the emitter into the base, where they diffuse towards the collector. Since electrons are not normal charge carriers in the p-type base region, these electrons are called "minority carriers". Since the emitter-collector current includes both electron and hole currents, the device is referred to as a "bipolar" device.

BJTs may require relatively large base currents to keep the device in its on state. As such, relatively complex external drive circuits may be required to provide the relatively large base currents that high power BJTs may require. Furthermore, due to the bipolar nature of current conduction, the switching speed of a BJT can be significantly slower than that of a power MOSFET.

Devices that incorporate a combination of bipolar current conduction and MOS control current are also known. An example of such a device is an insulated gate bipolar transistor ("IGBT"), which is a device that combines the high impedance gate of a power MOSFET with the small on-state conduction losses of a power BJT. An IGBT can be implemented, for example, as a Darlington pair comprising a high voltage n-channel MOSFET at the input and a BJT at the output. The base current of the BJT is supplied through the channel of the MOSFET, thereby allowing for a simplified external drive circuit. IGBTs combine the high temperature, high current density switching characteristics of BJTs with the minimal drive requirements of MOSFETs.

Most power semiconductor devices are formed from silicon ("Si"), but various other semiconductor materials have also been used. Silicon carbide ("SiC") is one of these candidates. Silicon carbide has potentially advantageous semiconductor properties including, for example, a wide band gap, high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturation electron drift velocity. Accordingly, electronic devices formed from silicon carbide may have the capability to operate at higher temperatures, at higher power densities, at higher speeds, at higher power levels and/or the ability to operate at high radiation densities.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a power semiconductor device is provided that includes:

a first conductivity type semiconductor layer having a first conductivity type;

a well region component, the well region component includes a first conductive type well region and a second conductive type well region;

a first conductivity type well region, having the first conductivity type, disposed in the first conductivity type semiconductor layer;

The second conductivity type well region, having the second conductivity type, is disposed within the first conductivity type well region and is completely surrounded by the first conductivity type well region.

In some embodiments, the doping concentration of the first conductive type well region is greater than the doping concentration of the first conductive type semiconductor layer; preferably, the doping concentration of the first conductive type well region is 1× 10 ¹⁶ cm ^-3 -5×10 ¹⁷ cm ^-3 , and the doping concentration of the first conductive type semiconductor layer is 1×10 ¹⁴ cm ^-3 -5×10 ¹⁷ cm ^-3 . For example, the doping concentration of the first conductive type well region is 1×10 ¹⁶ cm ^-3 -5×10 ¹⁷ cm ^-3 , and the doping concentration of the first conductive type semiconductor layer is 1×10 ¹⁴ cm ^{-3 3—5} ×10 ¹⁵ cm ^-3 .

In some embodiments, the first conductive type semiconductor layer includes at least two drift layers disposed in sequence, and the first conductive type well region is disposed in the first drift layer closest thereto and connected to the first drift layer Adjacent second drift layers overlap to form an overlapping region; preferably, the doping concentration of the first drift layer is less than the doping concentration of the second drift layer, and the doping concentration of the second drift layer is greater than the distance doping concentrations of other drift layers of the first conductivity type well region;

Preferably, the first drift layer is a first wide band gap drift layer, the second drift layer is a second wide band gap drift layer, and the first conductive type semiconductor layer is composed of first wide band gap drift layers stacked in sequence and a second wide band gap drift layer, the doping concentration of the first wide band gap drift layer is less than the doping concentration of the second wide band gap drift layer, and the first conductive type well region is at least partially connected to the second wide band gap. The drift layers overlap to form overlapping regions.

In some embodiments, along the depth direction of the second conductivity type well region, the doping concentration of the second conductivity type well region becomes smaller; preferably, it gradually becomes smaller.

In some embodiments, in the direction of the depth of the second conductive type well region, the second conductive type well region includes a first well region, a second well region and a third well region which are connected in sequence , the doping concentration of the first well section is not less than 1×10 ¹⁹ cm ^-3 , and the doping concentration of the second well section is 1×10 ¹⁷ cm ^-3 -5×10 ¹⁸ cm ^-3 , the doping concentration of the third well section is not less than 1×10 ¹⁶ cm ^-3 , preferably 1×10 ¹⁶ cm ^-3 to 5×10 ¹⁷ cm ^-3 .

In some embodiments, the wall thickness H1 of the first conductive type well region is not greater than 2 μm.

In some embodiments, the doping concentration of the first wide band gap drift layer is 1×10 ¹⁴ cm ⁻³ to 5×10 ¹⁷ cm ⁻³ ; the doping concentration of the second wide band gap drift layer is 1× 10 ¹⁴ cm ^-3 -5×10 ¹⁷ cm ^-3 ;

The depth d of the second conductive type well region is 1-2 μm.

In some embodiments, there are at least two well region components, adjacent well region components are arranged at intervals, and a wide band gap JFET region is formed between adjacent well region components, and the wide band gap JFET region has a first conductivity type;

It also includes a gate oxide layer located on the adjacent well region components and the wide band gap JFET region between the adjacent well region components and a gate electrode located on the gate oxide layer.

In some embodiments, the power semiconductor device includes a MOSFET, the MOSFET including,

a wide bandgap source region located in the second conductive type well region and having a first conductive type;

A wide bandgap drain region having a second conductivity type.

In some embodiments, the drift layer comprises an n-type silicon carbide drift layer, wherein the first conductivity type well region comprises an n-type silicon carbide n-well and the second conductivity type well region comprises a p-type silicon carbide p-well ;

the wide band gap source region includes an n-type silicon carbide source region;

the wide band gap drain region includes a p-type silicon carbide drain region;

The wide band gap JFET region includes an n-type silicon carbide JFET region.

In some embodiments, the power semiconductor device comprises a silicon carbide insulated gate bipolar junction transistor ("IGBT").

In some embodiments, an n-type silicon carbide substrate and an n ⁺ silicon carbide emitter region formed in the second conductivity type well region are further included, and wherein the first conductivity type semiconductor layer includes p-type silicon carbide a drift layer, wherein the second conductivity type well region comprises an n-type silicon carbide n-well;

Also includes a collector, disposed on the side of the n-type silicon carbide liner away from the second conductivity type well region, the collector is a p-type silicon carbide collector, and wherein the wide band gap JFET region includes p Type SiC JFET region.

In some embodiments, a p-type silicon carbide current spreading layer is further included, wherein the p-type silicon carbide JFET region is part of the p-type silicon carbide current spreading layer.

In addition, embodiments of the present invention also provide an insulated gate bipolar junction transistor (“IGBT”), which includes: a first conductivity type semiconductor layer having a first conductivity type on a wide band gap substrate, the wide band the gap substrate has a second conductivity type opposite the first conductivity type;

a well region component, the well region component includes a first conductive type well region and a second conductive type well region; the first conductive type well region, having the first conductive type, is disposed in the first conductive type semiconductor layer; A two-conductivity-type well region, having a second conductivity type, is disposed in the first-conductivity-type well region and is completely surrounded by the first-conductivity-type well region;

a wide bandgap emitter region located in the second conductive type well region and having a first conductive type;

a wide bandgap collector region having the second conductivity type and on the second conductivity type well region;

A wide band gap JFET region having the first conductivity type and located between adjacent well region components.

In some embodiments, the doping concentration of the first conductive type well region is greater than the doping concentration of the first conductive type semiconductor layer; preferably, the doping concentration of the first conductive type well region is 1× 10 ¹⁶ cm ^-3 -5×10 ¹⁷ cm ^-3 , and the doping concentration of the first conductive type semiconductor layer is 1×10 ¹⁴ cm ^-3 -5×10 ¹⁷ cm ^-3 .

In some embodiments, a gate oxide layer and a gate electrode on the gate oxide layer are also included on the adjacent well region components and the wide band gap JFET region between the adjacent well region components;

The first conductivity type is p-type and the second conductivity type is n-type.

In addition, an embodiment of the present invention also provides a process for preparing a power semiconductor device, including:

forming a first conductive type semiconductor layer;

forming a first conductive type well region within the first conductive type semiconductor layer;

A second conductive type well region is formed in the first conductive type well region, and the second conductive type well region is completely surrounded by the first conductive type well region.

Further, forming a first conductive type well region in the first conductive type semiconductor layer includes:

A first mask layer is formed on the first conductive type semiconductor layer, the first mask layer is etched through a dry or wet etching process to form a first opening to expose part of the first conductive type semiconductor layer, and a first opening is formed by etching the first mask layer through a dry or wet etching process. An opening is formed and a dopant having a second conductivity type (eg P-type dopant) is implanted into the first conductivity type semiconductor layer by means of ion implantation or oblique ion implantation to form a second conductivity type well region.

Further, forming a first conductive type well region in the first conductive type semiconductor layer includes:

A second conductive type well region is formed in the first conductive type well region, including:

The first mask layer near the first opening is etched by a dry or wet etching process, and the first conductive type semiconductor layer on which the first mask layer is etched is implanted by a self-alignment process A dopant of a first conductivity type (eg, an N-type dopant) is formed to form a well region of the first conductivity type.

In the present invention, the well region (for example, the well region of the first conductivity type and the well region of the second conductivity type) has a broader meaning, that is, it can refer to the usual meaning in a MOSFET or an IGBT, and it can also be used to describe the same features better. It can also not be the usual well region in MOSFET or IGBT, but customized, such as "first conductivity type well region" and "second conductivity type well region" in Schottky diodes (Figure 3 and Figure 4). " is custom and does not have the usual well region meaning in MOSFETs or IGBTs.

In the power semiconductor device provided by the embodiments of the present invention, a first conductive type well region is provided in the first conductive type semiconductor layer, a second conductive type well region is provided in the first conductive type well region, and the second conductive type well region is The first conductive type well region is completely surrounded, so the output capacitance (Coss) of the power semiconductor device can be reduced, and the ratio of its input capacitance (Ciss) to the output capacitance (Coss), that is, the value of Ciss/Coss, can also be improved. The electric field of the gate oxide is reduced, which ultimately improves the stability of the device. In addition, the power semiconductor device provided in the embodiments of the present invention can also reduce the unit cell size.

Description of drawings

In order to illustrate the specific embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the specific embodiments or the prior art. Obviously, the accompanying drawings in the following description The drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

1 is a schematic cross-sectional view of a power MOSFET according to an embodiment of the present invention.

2 is a schematic cross-sectional view of a power MOSFET according to a further embodiment of the present invention.

3 is a schematic cross-sectional view of a Schottky diode according to a further embodiment of the present invention.

4 is a schematic cross-sectional view of a Schottky diode according to a further embodiment of the present invention.

5 is a process flow diagram of a power semiconductor device according to an embodiment of the present invention;

6 is a schematic cross-sectional view of a power IGBT according to an embodiment of the present invention.

7 is a circuit diagram of a power IGBT according to some embodiments of the present invention.

8A-8E are flowcharts illustrating a fabrication process for forming a power MOSFET according to Embodiment 1 of the present invention.

Description of reference numbers:

1-first conductivity type semiconductor layer; 1a-first drift layer; 1b-second drift layer; 2-well region assembly; 2a-first conductivity type well region; 2b-second conductivity type well region; 3-broadband Gap JFET region; 4-gate oxide layer; 5-gate electrode; 6-insulating layer; 7-source electrode or emitter; 8-drain electrode or collector; 9-substrate; 10-cathode metal layer; 11-anode Metal layer; 12-protective layer; 13-passivation layer; 14-first mask layer; 15-second mask layer.

Detailed ways

The present invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on the other element or layer. An element or layer may be directly connected to, or coupled to, another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. . As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. The same reference numbers always refer to the same elements.

It will be understood that, although the terms first and second are used herein to describe various regions, layers and/or elements, these regions, layers and/or elements should not be limited by these terms. These terms are only used to distinguish one region, layer or element from another region, layer or element. Thus, a first region, layer or element discussed below could be termed a second region, layer or element, and, similarly, a second region, layer or element could be termed a first region, layer or element without departing from scope of the present invention.

Relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as illustrated in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both "lower" and "upper" orientations, depending on the particular orientation of the drawings. Similarly, if the device on one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "below" can encompass both an orientation of above and below.

The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and/or "comprising" when used herein designate the presence of stated features, elements and/or components, but do not exclude one or more other features, elements, The presence or addition of components and/or combinations thereof.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations. Accordingly, variations in the shape of the illustrations due, for example, to manufacturing techniques and/or tolerances should be expected. Thus, embodiments of the present invention should not be construed as limited to the specific shapes of the regions illustrated herein, but rather include deviations from the shapes due, for example, to manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curvilinear features, and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the context of the present disclosure and in the relevant art, and should not be taken in idealized or overly formalized terms. is construed in the sense of, unless expressly defined as such herein.

As used herein, source and drain regions may be collectively referred to as "source/drain regions," which is a term used to designate either a source region or a drain region.

It should be understood that the various embodiments disclosed herein may be combined. Thus, features depicted and/or described with respect to the first embodiment may be equally included in the second embodiment, and vice versa.

Some embodiments of the invention are described with reference to semiconductor layers and/or regions characterized as having a conductivity type such as n-type or p-type, which refers to the majority carrier concentration in the layer and/or region. Thus, the n-type material has a majority equilibrium concentration of negatively charged electrons, while the p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be assigned "+" or "-" (eg, n+, n-, p+, p-, n++, n--, p++, p--, etc.) to indicate a majority relative to another layer or region Relatively large ("+") or small ("-") concentration of charge carriers. However, this notation does not imply the presence of a particular concentration of majority or minority carriers in a layer or region.

As shown in FIG. 1 , a schematic cross-sectional view of a power MOSFET in an embodiment of the present invention. It can be known from FIG. 1 that the power MOSFET includes a first conductivity type semiconductor layer 1 with a first conductivity type, for example, the first conductivity type is N-type, which can be an N-type silicon carbide layer; a well region component 2, a well region component 2 It includes a first conductivity type well region 2a and a second conductivity type well region 2b; the first conductivity type well region 2a has a first conductivity type, for example, the first conductivity type is N type, and the first conductivity type well region 2a can be n type silicon carbide n-well, which is arranged in the first conductivity type semiconductor layer 1; the second conductivity type well region 2b has a second conductivity type, for example, the second conductivity type is p-type, and the second conductivity type well region 2b includes p-type The silicon carbide p-well is disposed in the first conductive type well region 2a and completely surrounded by the first conductive type well region 2a.

In the above-described power MOSFET, by providing the first conductive type well region 2a in the first conductive type semiconductor layer 1, the second conductive type well region 2b is provided in the first conductive type well region 2a, and the second conductive type well region 2b is The first conductive type well region 2a is completely surrounded, so the output capacitance (Coss) of the power semiconductor device can be reduced, and the ratio of the input capacitance (Ciss) to the output capacitance (Coss), that is, the value of Ciss/Coss, can also be improved. It can reduce the electric field of the gate oxide layer, and finally improve the stability of the device.

In some embodiments, the doping concentration of the first conductive type well region 2 a is greater than the doping concentration of the first conductive type semiconductor layer 1 ; preferably, the doping concentration of the first conductive type well region is 1×10 ¹⁶ cm ^-3 -5×10 ¹⁷ cm ^-3 , the doping concentration of the first conductive type semiconductor layer is 1×10 ¹⁴ cm ^-3 -5×10 ¹⁷ cm ^-3 , which can reduce COSS and gate oxide. electric field.

In some embodiments, the first conductive type semiconductor layer 1 includes at least two drift layers disposed in sequence, and the first conductive type well region 2a is disposed in the first drift layer 1a closest to the first drift layer 1a and connected to the first drift layer 1a Adjacent second drift layers 1b overlap to form an overlapping region; preferably, the doping concentration of the first drift layer 1a is less than that of the second drift layer 1b, and the doping concentration of the second drift layer 1b is greater than that farther away The doping concentration of the other drift layers in the first conductivity type well region 2a, for example, the other drift layers may be the third drift layer, the fourth drift layer, . . . The doping concentration from the third drift layer to the nth drift layer gradually decreases. The gate oxide electric field can be reduced by the above arrangement.

Preferably, the first drift layer 1a is a first wide band gap drift layer, the second drift layer 1b is a second wide band gap drift layer, and the first conductive type semiconductor layer 1 is composed of a first wide band gap drift layer and a second wide band gap drift layer that are stacked in sequence. It consists of a wide band gap drift layer, the doping concentration of the first wide band gap drift layer is lower than that of the second wide band gap drift layer, and the first conductive type well region 2a at least partially overlaps with the second wide band gap drift layer to form an overlapping region.

In some embodiments, as shown in FIG. 2 , along the depth direction of the second conductive type well region, the doping concentration of the second conductive type well region becomes smaller, so that the impact of the power semiconductor device can be improved. Breakthrough voltage; preferably gradually decreasing.

In some embodiments, along the depth direction of the second conductive type well region 2b, the second conductive type well region 2b includes a first well region, a second well region and a third well region which are connected in sequence. The doping concentration of one well section is not less than 1×10 ¹⁹ cm ^-3 , the doping concentration of the second well section is 1×10 ¹⁷ cm ^-3 -5×10 ¹⁸ cm ^-3 , the doping concentration of the third well section is 1×10 17 cm -3 -5×10 18 cm -3 , The doping concentration is not less than 1×10 ¹⁶ cm ^-3 , preferably 1×10 ¹⁶ cm ^{-3 -} 5×10 ¹⁷ cm ^-3 ; specifically, as shown in FIG. 2 , the first well segment is a P ⁺ segment , the second well segment is a P segment, ^and the third well segment is a P segment.

In some embodiments, the wall thickness H1 of the first conductive type well region is not greater than 2 μm.

In some embodiments, the doping concentration of the first wide band gap drift layer is 1×10 ¹⁴ cm ⁻³ to 5×10 ¹⁷ cm ⁻³ ; the doping concentration of the second wide band gap drift layer is 1× 10 ¹⁴ cm ^-3 -5×10 ¹⁷ cm ^-3 ; the depth d of the well region of the second conductivity type is 1-2 μm.

In some embodiments, there are at least two well region components 2, adjacent well region components 2 are arranged at intervals, and a wide band gap JFET region 3 is formed between adjacent well region components 2, and the wide band gap JFET region 3 has a first conductivity type, For example, the first conductivity type is N-type, specifically an n-type silicon carbide JFET region; it also includes a gate oxide layer 4 located on the wide band gap JFET region 3 between adjacent well region components 2 and adjacent well region components 2 and a gate electrode 5 located on the gate oxide layer 4; a wide band gap source region, located in the well region of the second conductivity type and having a first conductivity type; a wide band gap drain region, having a second conductivity type, such as the first conductivity type It can be N-type. In one embodiment, as shown in FIG. 1 , the wide-bandgap source region includes a P ⁺ region and an N ⁺ region that are in contact with each other, and further includes a source electrode 7 disposed on the insulating layer 6 and The drain electrode 8 disposed on the side of the substrate away from the source electrode 7 is connected to the wide band gap source region of the source electrode 7, and the drain electrode 8 is connected to the wide band gap drain region.

Further, a field confinement ring is also included, which is arranged in the drift layer on the side of the drift layer away from the substrate 9 ; specifically, several P ⁺ regions are arranged in the drift layer at intervals as shown in FIGS. 1 and 2 .

In some embodiments, the power semiconductor device comprises a silicon carbide insulated gate bipolar junction transistor ("IGBT").

In some embodiments, an n-type silicon carbide substrate and an n ⁺ silicon carbide emitter region formed in the second conductivity type well region are further included, and wherein the first conductivity type semiconductor layer includes p-type silicon carbide a drift layer, wherein the second conductivity type well region comprises an n-type silicon carbide n-well;

Also includes a collector, disposed on the side of the n-type silicon carbide liner away from the second conductivity type well region, the collector is a p-type silicon carbide collector, and wherein the wide band gap JFET region includes p Type SiC JFET region.

In some embodiments, a p-type silicon carbide current spreading layer is further included, wherein the p-type silicon carbide JFET region is part of the p-type silicon carbide current spreading layer.

Specifically, in addition, an embodiment of the present invention also provides an insulated gate bipolar junction transistor ("IGBT"), which includes: a semiconductor layer of a first conductivity type having a first conductivity type, which is located on a wide-bandgap substrate, the wide band gap substrate has a second conductivity type opposite to the first conductivity type;

a well region component, the well region component includes a first conductive type well region and a second conductive type well region; the first conductive type well region, having the first conductive type, is disposed in the first conductive type semiconductor layer; A two-conductivity-type well region, having a second conductivity type, is disposed in the first-conductivity-type well region and is completely surrounded by the first-conductivity-type well region;

a wide bandgap emitter region located in the second conductive type well region and having a first conductive type;

a wide bandgap collector region having the second conductivity type and on the second conductivity type well region;

A wide band gap JFET region having the first conductivity type and located between adjacent well region components.

In some embodiments, the doping concentration of the first conductive type well region is greater than the doping concentration of the first conductive type semiconductor layer; preferably, the doping concentration of the first conductive type well region is 1× 10 ¹⁶ cm ^-3 -5×10 ¹⁷ cm ^-3 , and the doping concentration of the first conductive type semiconductor layer is 1×10 ¹⁴ cm ^-3 -5×10 ¹⁷ cm ^-3 .

In some embodiments, a gate oxide layer and a gate electrode on the gate oxide layer are also included on the adjacent well region components and the wide band gap JFET region between the adjacent well region components;

The first conductivity type is p-type and the second conductivity type is n-type.

In addition, an embodiment of the present invention also provides a process for preparing a power semiconductor device, as shown in FIG. 5 , including:

S101, forming a first conductive type semiconductor layer; specifically, the first conductive type semiconductor layer may form a multi-layer drift layer on a substrate by means of epitaxial growth, ion implantation or oblique ion implantation;

S102, forming a first conductive type well region in the first conductive type semiconductor layer; it can also be formed by ion implantation or oblique ion implantation;

S103. A second conductivity type well region is formed in the first conductivity type well region, and the second conductivity type well region is completely surrounded by the first conductivity type well region; also ion implantation or oblique ion implantation can be used way of forming.

Further, forming a first conductive type well region in the first conductive type semiconductor layer includes:

A first mask layer is formed on the first conductive type semiconductor layer, the first mask layer is etched through a dry or wet etching process to form a first opening to expose part of the first conductive type semiconductor layer, and a first opening is formed by etching the first mask layer through a dry or wet etching process. An opening is formed and a dopant having a second conductivity type (eg P-type dopant) is implanted into the first conductivity type semiconductor layer by means of ion implantation or oblique ion implantation to form a second conductivity type well region.

Further, forming a first conductive type well region in the first conductive type semiconductor layer includes:

A second conductive type well region is formed in the first conductive type well region, including:

The first mask layer near the first opening is etched by a dry or wet etching process, and the first conductive type semiconductor layer on which the first mask layer is etched is implanted by a self-alignment process A dopant of a first conductivity type (eg, an N-type dopant) is formed to form a well region of the first conductivity type.

In order to illustrate the technical solutions of the present invention in detail, the following specific embodiments are provided:

Example 1

This embodiment provides a power MOSFET and a manufacturing process thereof. As shown in FIG. 1 , the power MOSFET includes a first conductivity type semiconductor layer 1 having a first conductivity type. For example, the first conductivity type semiconductor layer 1 consists of a first wide band gap drift layer and a second wide band gap drift layer that are stacked in sequence. composition, the doping concentration of the first wide band gap drift layer is less than the doping concentration of the second wide band gap drift layer, the first wide band gap drift layer is a lightly doped N ^- type silicon carbide layer, for example, the dopant can be phosphorus , nitrogen, the second wide band gap drift layer is a doped N-type silicon carbide layer, for example, the dopant can be phosphorus, nitrogen, the second wide band gap drift layer is arranged on the substrate 9, and the substrate 9 can be heavily doped The N ⁺ type silicon carbide layer, for example, the dopant can be phosphorus, nitrogen, the first wide band gap drift layer and the second wide band gap drift layer can be formed by epitaxial growth, ion implantation or inclined ion implantation; well region component 2. The well region component 2 includes a first conductivity type well region 2a and a second conductivity type well region 2b; the first conductivity type well region 2a has a first conductivity type, for example, the first conductivity type is N type, and the first conductivity type The well region 2a can be an n-type silicon carbide n-well, which is arranged in the first conductivity type semiconductor layer 1; the second conductivity type well region 2b has a second conductivity type, for example, the second conductivity type is P-type, and the second conductivity type is P-type. The well region 2b includes a p-type silicon carbide p-well, the dopants in the p-type silicon carbide p-well can be aluminum, boron, and gallium, which are arranged in the first conductive type well region 2a and are completely covered by the first conductive type well region 2a surrounded;

Adjacent well region components 2 are provided with wide band gap JFET regions 3 at intervals, the wide band gap JFET region 3 is an n-type silicon carbide JFET region, and is located on the wide band gap JFET region 3 between adjacent well region components 2 and adjacent well region components 2. The gate oxide layer 4, the gate electrode 5 on the gate oxide layer 4 and the insulating layer 6 on the gate electrode 5; the wide band gap source region, which is located in the second conductivity type well region and has the first conductivity type; wide band The gap drain region has a second conductivity type, for example, the first conductivity type can be N-type, as shown in FIG. 1 , the wide-bandgap source region includes a P ⁺ region and an N ⁺ region in contact with each other, and also includes an insulating layer provided The source electrode 7 on 6 and the drain electrode 8 disposed on the side of the substrate 9 away from the source electrode 7, the source electrode 7 is connected to the wide band gap source region, and the drain electrode 8 is connected to the wide band gap drain region.

The preparation process of the above-mentioned power MOSFET, as shown in Figures 8A-8E, includes the following steps:

(1) sequentially forming a second wide band gap drift layer and a first wide band gap drift layer on the substrate 9 by means of epitaxial growth, ion implantation or oblique ion implantation;

(2) Form a first mask layer (such as silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) on the first wide-bandgap drift layer, by dry method or wet method The etching process etches the first mask layer 14 to form a first opening to expose the first wide band gap drift layer, and implants the first wide band gap drift layer and the second wide band gap drift layer through the first opening and by means of ion implantation Dopants of aluminum, boron or gallium are implanted deep into the second wide band gap drift layer to form a second conductive type well region 2b, namely P-P#, the second conductive type well region 2b overlaps with the second wide band gap drift layer region; and then implant dopant phosphorus or nitrogen into the second conductive type well region 2b through a self-alignment process to form an N+ region;

(3) Etch the first mask layer near the first opening in step (2) by a dry or wet etching process, and in the first wide band gap drift layer on which the first mask layer is etched away Dopant phosphorus or nitrogen is implanted through a self-aligned process to form a first conductive type well region 2a, the first conductive type well region 2a completely surrounds the second conductive type well region 2b;

(4) Form a second mask layer (such as silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) on the first wide-bandgap drift layer, by dry method or wet method The etching process etches the second mask layer 15 to form a second opening to expose the second conductive type well region 2b, and through the second opening and by means of ion implantation, dopant aluminum or Boron or gallium to form the P+ region, at this time, the field limiting ring and the gate oxide layer 4 can be formed simultaneously;

(5) Etch the remaining second mask layer on the first wide-bandgap drift layer by dry or wet etching process, then perform annealing and clean the surface in sequence; then form a gate by forming a mask layer and selective etching Electrode 5, insulating layer 7, source electrode 7, drain electrode 8;

(6) The device obtained in step (5) can also be protected from the front, such as epitaxial growth protective layer (marked in FIG. 1 ), backside thinning, ohmic contact and metal deposition, etc., so that the process can be made by existing technology. Get it.

Example 2

This embodiment provides a power MOSFET and a manufacturing process thereof. As shown in FIG. 2 , the power MOSFET includes a first conductivity type semiconductor layer 1 having a first conductivity type. For example, the first conductivity type semiconductor layer 1 is composed of a first wide band gap drift layer and a second wide band gap drift layer that are stacked in sequence. composition, the doping concentration of the first wide band gap drift layer is less than the doping concentration of the second wide band gap drift layer, the first wide band gap drift layer is a lightly doped N ^- type silicon carbide layer, for example, the dopant can be phosphorus , nitrogen, the second wide band gap drift layer is a doped N-type silicon carbide layer, for example, the dopant can be phosphorus, nitrogen, the second wide band gap drift layer is arranged on the substrate 9, and the substrate 9 can be heavily doped The N ⁺ type silicon carbide layer, for example, the dopant can be phosphorus, nitrogen, the first wide band gap drift layer and the second wide band gap drift layer can be formed by epitaxial growth, ion implantation or inclined ion implantation; well region component 2. The well region component 2 includes a first conductivity type well region 2a and a second conductivity type well region 2b; the first conductivity type well region 2a has a first conductivity type, for example, the first conductivity type is N type, and the first conductivity type The well region 2a can be an n-type silicon carbide n-well, which is arranged in the first conductivity type semiconductor layer 1; the second conductivity type well region 2b has a second conductivity type, for example, the second conductivity type is P-type, and the second conductivity type is P-type. The well region 2b includes a p-type silicon carbide p-well, the dopants in the p-type silicon carbide p-well can be aluminum, boron, and gallium, which are arranged in the first conductive type well region 2a and are completely covered by the first conductive type well region 2a Surrounding; the second conductive type well region 2b in the direction of its depth, the second conductive type well region 2b includes a first well segment, a second well segment and a third well segment connected in sequence, the first well segment The doping concentration is not less than 1×10 ¹⁹ cm ^-3 , the doping concentration of the second well section is 1×10 ¹⁷ cm ^-3 -5×10 ¹⁸ cm ^-3 , the doping concentration of the third well section is 1×10 17 cm -3 -5×10 18 cm -3 is not less than 1×10 ¹⁶ cm ^-3 , preferably 1×10 ¹⁶ cm ^-3 to 5×10 ¹⁷ cm ^-3 ; specifically, as shown in FIG. 2 , the first well segment is the P+ segment, the second well The segment is a P segment, and the third well segment is a P- segment;

Adjacent well region components 2 are provided with wide band gap JFET regions 3 at intervals, the wide band gap JFET region 3 is an n-type silicon carbide JFET region, and is located on the wide band gap JFET region 3 between adjacent well region components 2 and adjacent well region components 2. The gate oxide layer 4, the gate electrode 5 on the gate oxide layer 4 and the insulating layer 6 on the gate electrode 5; the wide band gap source region, which is located in the second conductivity type well region and has the first conductivity type; wide band The gap drain region has a second conductivity type, for example, the first conductivity type can be N-type, as shown in FIG. 2 , the wide-bandgap source region includes P ⁺ regions in contact with each other, and also includes a source disposed on the insulating layer 6 The electrode 7 and the drain electrode 8 disposed on the side of the substrate 9 away from the source electrode 7, the source electrode 7 is connected to the wide band gap source region, and the drain electrode 8 is connected to the wide band gap drain region.

The preparation process of above-mentioned power MOSFET, comprises the following steps:

(1) sequentially forming a second wide band gap drift layer and a first wide band gap drift layer on the substrate 9 by means of epitaxial growth, ion implantation or oblique ion implantation;

(2) Form a first mask layer (such as silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) on the first wide-bandgap drift layer, by dry method or wet method The etching process etches the first mask layer to form a first opening to expose the first wide band gap drift layer, and implants dopant into the first wide band gap drift layer and the second wide band gap drift layer by means of ion implantation through the first opening Impurity aluminum, boron, or gallium is implanted deep into the second wide band gap drift layer to form a second conductive type well region 2b, that is, P-P#, and the second conductive type well region 2b and the second wide band gap drift layer have an overlapping region ; Implant dopant aluminum, boron or gallium into the second conductive type well region 2b again through the self-alignment process, and finally implant dopant aluminum or boron or gallium into the second conductive type well region 2b through the self-alignment process again. boron or gallium, so as to finally form a P- segment, a P segment and a P+ segment from bottom to top in the second conductivity type well region 2b;

(3) Etch the first mask layer near the first opening in step (2) by a dry or wet etching process, and in the first wide band gap drift layer on which the first mask layer is etched away Dopants phosphorus and nitrogen are implanted through a self-aligned process to form a first conductive type well region 2a, and the first conductive type well region 2a completely surrounds the second conductive type well region 2b;

(4) Form a second mask layer (such as silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) on the first wide-bandgap drift layer, by dry method or wet method The etching process etches the second mask layer to form a second opening to expose the part outside the second conductive type well region 2b, and implants the part outside the second conductive type well region 2b through the second opening by means of ion implantation Doping aluminum, boron or gallium to form a confinement ring (P+), at this time, the gate oxide layer 4 can be formed simultaneously;

(5) Etch the remaining second mask layer on the first wide-bandgap drift layer by dry or wet etching process, then perform annealing and clean the surface in sequence; then form a gate by forming a mask layer and selective etching Electrode 5, insulating layer 7, source electrode 7, drain electrode 8;

(6) The device obtained in step (5) can also be protected from the front, such as epitaxial growth protective layer (marked in FIG. 2 ), backside thinning, ohmic contact and metal deposition, etc., so that the process can be made by existing technology. Get it.

Example 3

This embodiment provides a Schottky diode and a manufacturing process thereof. As shown in FIG. 3 , the Schottky diode includes a first conductivity type semiconductor layer 1 having a first conductivity type. For example, the first conductivity type semiconductor layer 1 is composed of a first wide band gap drift layer and a second wide band gap which are stacked in sequence. Drift layer composition, the doping concentration of the first wide band gap drift layer is less than the doping concentration of the second wide band gap drift layer, the first wide band gap drift layer is lightly doped N ^- type silicon carbide layer, for example, the dopant can be is phosphorus or nitrogen, the second wide band gap drift layer is a doped N-type silicon carbide layer, for example, the dopant can be phosphorus or nitrogen, the second wide band gap drift layer is disposed on the substrate 9, and the substrate 9 can be heavy The doped N ⁺ type silicon carbide layer, for example, the dopant can be phosphorus or nitrogen, and both the first wide band gap drift layer and the second wide band gap drift layer can be formed by epitaxial growth, ion implantation or oblique ion implantation; well The region component 2, the well region component 2 includes a first conductivity type well region 2a and a second conductivity type well region 2b; the first conductivity type well region 2a has a first conductivity type, for example, the first conductivity type is N-type, and the first conductivity type is N-type. The conductivity-type well region 2a may be an n-type silicon carbide n-well, which is arranged in the first conductivity-type semiconductor layer 1; the second conductivity-type well region 2b has a second conductivity type, for example, the second conductivity type is P-type, and the second conductivity type is P-type. The conductive type well region 2b includes a p-type silicon carbide p-well, and the dopant in the p-type silicon carbide p-well may be aluminum, boron or gallium, which is arranged in the first conductive type well region 2a and is surrounded by the first conductive type well region. 2a is completely surrounded; in one embodiment, P+ is implanted into the p-type silicon carbide p-well, so that its doping concentration is higher than the doping concentration of the first drift layer 1a in the first conductive type semiconductor layer 1; in another embodiment, P+ is not implanted into the p-type silicon carbide p-well, so that its doping concentration is the same as the doping concentration of the first drift layer 1a in the first conductive type semiconductor layer 1, which can reduce the implantation steps and simplify the preparation process.

可以通过蒸发或者溅射的形式形成；The anode metal layer 11 (for example, an Al layer) located on the adjacent well region components 2 and between the adjacent well region components 2 and the cathode metal layer 10 disposed on the side of the substrate 9 away from the anode metal layer 11 are not shown. A protective layer (for example, a SiO ₂ layer or a Si ₃ N ₄ layer) is provided on the first wide band gap drift layer covered and contacted by the anode metal layer 11 to protect the drift layer and the first conductivity type well region 2a and the second conductivity type Well region 2b; A Schottky barrier layer (not shown in the figure) is provided between the anode metal layer 11 and the "adjacent well region component 2 and the adjacent well region component 2", and the material of the Schottky barrier layer can be Choose Ti, Ni, Al, Mo, W, polysilicon, etc. The general thickness is

It can be formed by evaporation or sputtering;

The preparation process of the above-mentioned Schottky diode includes the following steps:

(1) sequentially forming a second wide band gap drift layer and a first wide band gap drift layer on the substrate 9 by means of epitaxial growth, ion implantation or oblique ion implantation;

(2) Form a first mask layer (such as silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) on the first wide-bandgap drift layer, by dry method or wet method The etching process etches the first mask layer to form a first opening to expose the first wide band gap drift layer, and implants dopant into the first wide band gap drift layer and the second wide band gap drift layer by means of ion implantation through the first opening Impurity aluminum, boron, or gallium is implanted deep into the second wide band gap drift layer to form a second conductive type well region 2b, that is, P-P#, and the second conductive type well region 2b and the second wide band gap drift layer have an overlapping region ;

(3) Etch the first mask layer near the first opening in step (2) by a dry or wet etching process, and in the first wide band gap drift layer on which the first mask layer is etched away Dopant phosphorus or nitrogen is implanted through a self-aligned process to form a first conductive type well region 2a, the first conductive type well region 2a completely surrounds the second conductive type well region 2b;

(4) forming a Schottky barrier layer on the adjacent well region components 2 and the regions between adjacent well region components 2 by evaporation or sputtering;

(5) The anode metal layer 11 is formed on the Schottky barrier layer by sputtering or evaporation. The anode metal layer 11 at least partially covers the first conductivity type well region and the second conductivity type well region 2b, and is not covered by the anode metal layer. A protective layer (for example, a SiO ₂ layer or a Si ₃ N ₄ layer) is formed on the first wide band gap drift layer covered and contacted by the layer 11 by sputtering or chemical vapor deposition; and the substrate 9 is far from the anode metal layer 11 The cathode metal layer 10 is formed on one side by evaporation or sputtering.

Example 4

This embodiment provides a Schottky diode and a manufacturing process thereof. As shown in FIG. 3 , the Schottky diode includes a first conductivity type semiconductor layer 1 having a first conductivity type. For example, the first conductivity type semiconductor layer 1 is composed of a first wide band gap drift layer and a second wide band gap which are stacked in sequence. Drift layer composition, the doping concentration of the first wide band gap drift layer is less than the doping concentration of the second wide band gap drift layer, the first wide band gap drift layer is lightly doped N ^- type silicon carbide layer, for example, the dopant can be is phosphorus or nitrogen, the second wide band gap drift layer is a doped N-type silicon carbide layer, for example, the dopant can be phosphorus or nitrogen, the second wide band gap drift layer is disposed on the substrate 9, and the substrate 9 can be heavy The doped N ⁺ type silicon carbide layer, for example, the dopant can be phosphorus or nitrogen, and both the first wide band gap drift layer and the second wide band gap drift layer can be formed by epitaxial growth, ion implantation or oblique ion implantation; well The region component 2, the well region component 2 includes a first conductivity type well region 2a and a second conductivity type well region 2b; the first conductivity type well region 2a has a first conductivity type, for example, the first conductivity type is N-type, and the first conductivity type is N-type. The conductivity-type well region 2a may be an n-type silicon carbide n-well, which is arranged in the first conductivity-type semiconductor layer 1; the second conductivity-type well region 2b has a second conductivity type, for example, the second conductivity type is P-type, and the second conductivity type is P-type. The conductive type well region 2b includes a p-type silicon carbide p-well, and the dopant in the p-type silicon carbide p-well may be aluminum, boron or gallium, which is arranged in the first conductive type well region 2a and is surrounded by the first conductive type well region. 2a completely surrounded;

可以通过蒸发或者溅射的形式形成；The anode metal layer 11 (for example, an Al layer) located on the adjacent well region components 2 and between the adjacent well region components 2 and the cathode metal layer 10 disposed on the side of the substrate 9 away from the anode metal layer 11 are located in The anode metal layer 11 in the second conductive type well region 2b protrudes toward the second conductive type well region 2b and enters the second conductive type well region 2b; a passivation layer 13 (for example, SiO ₂ ) is provided on the anode metal layer 11 layer or Si ₃ N ₄ layer) and is completely covered by the passivation layer 13; a Schottky barrier layer (not shown in the figure) is arranged between the anode metal layer 11 and the “adjacent well region component 2 and the adjacent well region component 2” Draw), the material of the Schottky barrier layer can be selected from Ti, Ni, Al, Mo, W, polysilicon, etc. The general thickness is

It can be formed by evaporation or sputtering;

The preparation process of the above-mentioned Schottky diode includes the following steps:

(1) sequentially forming a second wide band gap drift layer and a first wide band gap drift layer on the substrate 9 by means of epitaxial growth, ion implantation or oblique ion implantation;

(2) Form a first mask layer (such as silicon dioxide, or a photoresist, or a polysilicon layer, or a nitride layer, such as silicon nitride) on the first wide-bandgap drift layer, by a dry method or a wet method The etching process etches the first mask layer to form a first opening to expose the first wide band gap drift layer, and implants dopant into the first wide band gap drift layer and the second wide band gap drift layer by means of ion implantation through the first opening The impurity aluminum, boron or gallium is implanted deep into the second wide band gap drift layer to form a second conductive type well region 2b, namely P-P#, the second conductive type well region 2b and the second wide band gap drift layer have an overlapping area ; Implant dopant phosphorus or nitrogen in the second conductive type well region 2b through a self-alignment process to form an N+ region;

(3) Etch the first mask layer near the first opening in step (2) by a dry or wet etching process, and in the first wide band gap drift layer on which the first mask layer is etched away Dopant phosphorus or nitrogen is implanted through a self-aligned process to form a first conductive type well region 2a, the first conductive type well region 2a completely surrounds the second conductive type well region 2b;

(4) forming a Schottky barrier layer on the adjacent well region components 2 and the regions between adjacent well region components 2 by evaporation or sputtering;

(5) The anode metal layer 11 is formed on the Schottky barrier layer by sputtering or evaporation. The anode metal layer 11 at least partially covers the first conductivity type well region and the second conductivity type well region 2b, and the anode metal layer 11 A passivation layer 13 (for example, a SiO ₂ layer or a Si ₃ N ₄ layer) is formed on the substrate 9 by sputtering or chemical vapor deposition; and on the side of the substrate 9 away from the anode metal layer 11 by evaporation or sputtering The cathode metal layer 10 is formed.

Example 5

This embodiment provides an IGBT and a manufacturing process thereof. As shown in FIG. 6 , the IGBT includes a first conductivity type semiconductor layer 1 having a first conductivity type. For example, the first conductivity type semiconductor layer 1 is composed of a first wide band gap drift layer and a second wide band gap drift layer that are stacked in sequence. , the doping concentration of the first wide band gap drift layer is less than the doping concentration of the second wide band gap drift layer, the first wide band gap drift layer is a lightly doped P ^- type silicon carbide layer, for example, the dopant can be aluminum, Boron, gallium, the second wide band gap drift layer is a doped P-type silicon carbide layer, for example, the dopant can be aluminum, boron, gallium, the second wide band gap drift layer is disposed on the substrate 9, and the substrate 9 can be The heavily doped N ⁺ type silicon carbide layer, for example, the dopant can be phosphorus, nitrogen, the first wide band gap drift layer and the second wide band gap drift layer can be formed by epitaxial growth, ion implantation or oblique ion implantation; Well region component 2, the well region component 2 includes a first conductivity type well region 2a and a second conductivity type well region 2b; the first conductivity type well region 2a has a first conductivity type, for example, the first conductivity type is P-type, and the first conductivity type is P-type. A conductivity type well region 2a may be a p-type silicon carbide p-well, which is disposed in the first conductivity type semiconductor layer 1; the second conductivity type well region 2b has a second conductivity type, for example, the second conductivity type is N type, and the second conductivity type well region 2b has a second conductivity type. The two-conductivity-type well region 2b includes an N-type silicon carbide n-well, and the dopant in the N-type silicon carbide n-well may be phosphorus or nitrogen, which is disposed in the first-conductivity-type well region 2a and is surrounded by the first-conductivity-type well region 2a Completely surrounded; the second conductivity type well region 2b is not divided into well regions in the direction of its depth, and the doping concentration is the same;

Adjacent well region components 2 are provided with wide band gap JFET regions 3 at intervals, the wide band gap JFET region 3 is a P-type silicon carbide JFET region, located on the wide band gap JFET region 3 between adjacent well region components 2 and adjacent well region components 2. The gate oxide layer 4 and the gate electrode 5 on the gate oxide layer 4 and the insulating layer 6 on the gate electrode 5; the wide band gap emitter region, which is located in the second conductivity type well region and has the first conductivity type, and The emitter 7 is connected; for example, the first conductivity type can be P-type, as shown in FIG. 6, the P ⁺ region is close to the wide-bandgap JFET region 3; the wide-bandgap collector region, which has the second conductivity type and is located in the second conductivity type well region; a wide band gap JFET region, which has the first conductivity type and is located between adjacent well region components; a wide band gap collector region, which can be arranged on the side of the substrate 9 away from the wide band gap emitter region, Connected to collector 8.

The preparation process of the above-mentioned IGBT includes the following steps:

(1) sequentially forming a second wide band gap drift layer and a first wide band gap drift layer on the substrate 9 by means of epitaxial growth, ion implantation or oblique ion implantation;

(2) Form a first mask layer (such as silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) on the first wide-bandgap drift layer, by dry method or wet method The etching process etches the first mask layer to form a first opening to expose the first wide band gap drift layer, and implants dopant into the first wide band gap drift layer and the second wide band gap drift layer by means of ion implantation through the first opening Impurity phosphorus or nitrogen is implanted deep into the second wide band gap drift layer to form a second conductive type well region 2b, namely N-N#, the second conductive type well region 2b and the second wide band gap drift layer have an overlapping region; Dopant phosphorus or nitrogen is implanted into the second conductive type well region 2b through a self-alignment process to form a P+ region;

(3) Etch the first mask layer near the first opening in step (2) by a dry or wet etching process, and in the first wide band gap drift layer on which the first mask layer is etched away Dopants of aluminum, boron or gallium are implanted through a self-aligned process to form a first conductive type well region 2a, which completely surrounds the second conductive type well region 2b;

(4) Form a second mask layer (such as silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) on the first wide-bandgap drift layer, by dry method or wet method The etching process etches the second mask layer to form a second opening to expose the second conductive type well region 2b, and implants dopant phosphorus or nitrogen into the second conductive type well region 2b by means of ion implantation through the second opening , to form the N+ region, at this time, the field limiting ring and the gate oxide layer 4 can be formed simultaneously;

(5) Etch the remaining second mask layer on the first wide-bandgap drift layer by dry or wet etching process, then perform annealing and clean the surface in sequence; then form a gate by forming a mask layer and selective etching Electrode 5, insulating layer 7, source electrode 7, drain electrode 8;

(6) The device prepared in step (5) can also be protected from the front, such as epitaxial growth protective layer (marked in FIG. 6 ), backside thinning, ohmic contact and metal deposition, etc., so that the process can be made by existing technology. Get it.

7 is a circuit diagram of a power IGBT according to some embodiments of the present invention, from FIG. 7 it can be seen that the IGBT 500 includes an NPN silicon carbide power BJT 501 having a base 502 , an emitter 503 and a collector 504 . The IGBT 500 also includes a silicon carbide power MOSFET 505 having a gate 506 , a source 507 and a drain 508 . The source 507 of the silicon carbide power MOSFET 505 is electrically connected to the base 502 of the silicon carbide power BJT 501 , and the drain 508 of the silicon carbide power MOSFET 505 is electrically connected to the collector 504 of the silicon carbide power BJT 501 .

The IGBT 500 may operate as follows. An external driver circuit is connected to the gate 506 of the MOSFET 505 to apply a gate bias to the power MOSFET 505 . When the external driver circuit applies sufficient voltage to the gate electrode 506, an inversion layer is formed under the gate electrode 506, which acts as a channel 509 electrically connecting the collector 504 of the BJT 501 to the base 502 of the BJT 501. Holes are conducted from collector region 504 through channel 509 into base 501 . This hole current acts as the base current that drives the BJT 501 . In response to this hole current, electrons are conducted from the emitter 503 of the BJT 501 to the collector 504 of the BJT 501 across the base 502 . Thus, the silicon carbide power MOSFET 505 converts the silicon carbide power BJT 501 from a current-driven device to a voltage-driven device, which may allow for simplified external drive circuitry. The silicon carbide power MOSFET 505 acts as the driver transistor and the silicon carbide power BJT 501 acts as the output transistor of the IGBT 500 .

In addition, according to the above description, the p-type MOSFET device and the n-type MOSFET device can be converted to each other, the p-type IGBT and the n-type IGBT can be converted to each other, the p-type MOSFET device, the n-type MOSFET device, the p-type IGBT and the n-type MOSFET IGBTs are all within the protection scope of the present invention.

Although the above-described embodiments have been described with reference to specific drawings, it is to be understood that some embodiments of the invention may include additional and/or intervening layers, structures or elements, and/or specific layers, structures or elements may be omitted. element. While several exemplary embodiments of this invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the described exemplary embodiments without materially departing from the novel teachings of this invention and advantages. Accordingly, all such modifications are intended to be included within the scope of this invention as defined by the claims. Therefore, it is to be understood that the foregoing is illustrative of the invention and that this invention should not be construed as limited to the specific embodiments disclosed and that modifications to the disclosed and other embodiments are intended to be included in the accompanying drawings. within the scope of the claims. The invention is defined by the following claims, with equivalents of the claims to be included therein.

Claims (23)

1. A power semiconductor device, comprising: a first conductivity type semiconductor layer having a first conductivity type; a well region component, the well region component includes a first conductive type well region and a second conductive type well region; a first conductivity type well region, having the first conductivity type, disposed in the first conductivity type semiconductor layer; The second conductivity type well region, having the second conductivity type, is disposed in the first conductivity type well region and is completely surrounded by the first conductivity type well region; The first conductive type semiconductor layer includes at least two drift layers arranged in sequence, and the first conductive type well region is arranged in the first drift layer closest to the second drift layer and adjacent to the first drift layer The layers are overlapped to form an overlapping region; the doping concentration of the first drift layer is less than that of the second drift layer, and the doping concentration of the second drift layer is greater than the doping concentration of the second drift layer farther away from the first conductivity type well region. Doping concentrations of other drift layers. 2 . The power semiconductor device according to claim 1 , wherein the doping concentration of the first conductive type well region is greater than the doping concentration of the first conductive type semiconductor layer. 3 . 3 . The power semiconductor device according to claim 2 , wherein the doping concentration of the first conductive type well region is 1×10 ¹⁶ cm ⁻³ to 5×10 ¹⁷ cm ⁻³ . The doping concentration of the conductive type semiconductor layer is 1×10 ¹⁴ cm ⁻³ to 5×10 ¹⁷ cm ⁻³ . 4 . The power semiconductor device according to claim 1 , wherein the first drift layer is a first wide band gap drift layer, the second drift layer is a second wide band gap drift layer, and the first conductive The type semiconductor layer is composed of a first wide band gap drift layer and a second wide band gap drift layer that are stacked in sequence, the doping concentration of the first wide band gap drift layer is smaller than that of the second wide band gap drift layer, and the doping concentration of the first wide band gap drift layer is smaller than that of the second wide band gap drift layer. A conductive type well region at least partially overlaps the second wide band gap drift layer to form an overlapping region. 5 . The power semiconductor device according to claim 1 , wherein along the depth direction of the second conductivity type well region, the doping concentration of the second conductivity type well region changes. 6 . Small. 6 . The power semiconductor device according to claim 5 , wherein along the depth direction of the second conductivity type well region, the doping concentration of the second conductivity type well region gradually decreases. 7 . 7 . The power semiconductor device according to claim 5 , wherein, in the direction of the depth of the second conductive type well region, the second conductive type well region comprises a first well region, a The second well section and the third well section, the doping concentration of the first well section is not less than 1×10 ¹⁹ cm ⁻³ , and the doping concentration of the second well section is 1×10 ¹⁷ cm ⁻³ —5×10 ¹⁸ cm ⁻³ , and the doping concentration of the third well region is not less than 1×10 ¹⁶ cm ⁻³ . 8 . The power semiconductor device according to claim 7 , wherein the doping concentration of the third well region is 1×10 ¹⁶ cm ⁻³ to 5×10 ¹⁷ cm ⁻³ . 9 . 9 . The power semiconductor device according to claim 4 , wherein the wall thickness H1 of the first conductive type well region is not greater than 2 μm. 10 . 10 . The power semiconductor device according to claim 4 , wherein the doping concentration of the first wide band gap drift layer is 1×10 ¹⁴ cm ⁻³ to 5×10 ¹⁷ cm ⁻³ ; 10 . The doping concentration of the second wide band gap drift layer is 1×10 ¹⁴ cm ^-3 -5×10 ¹⁷ cm ^-3 ; The depth d of the second conductive type well region is 1-2 μm. 11 . The power semiconductor device according to claim 10 , wherein there are at least two well region components, adjacent well region components are arranged at intervals, and a wide band gap JFET region is formed between adjacent well region components, and the the wide band gap JFET region has a first conductivity type; It also includes a gate oxide layer located on the adjacent well region components and the wide band gap JFET region between the adjacent well region components and a gate electrode located on the gate oxide layer. 12. The power semiconductor device of claim 11, wherein the power semiconductor device comprises a MOSFET, the MOSFET comprising: a wide bandgap source region located in the second conductive type well region and having a first conductive type; A wide bandgap drain region having a second conductivity type. 13. The power semiconductor device of claim 12, wherein the drift layer comprises an n-type silicon carbide drift layer, wherein the first conductivity type well region comprises an n-type silicon carbide n-well, and the second conductivity type well region comprises an n-type silicon carbide n-well. The conductive type well region includes a p-type silicon carbide p-well; the wide band gap source region includes an n-type silicon carbide source region; the wide band gap drain region includes a p-type silicon carbide drain region; The wide band gap JFET region includes an n-type silicon carbide JFET region. 14. The power semiconductor device of claim 11, wherein the power semiconductor device comprises a silicon carbide insulated gate bipolar junction transistor. 15. The power semiconductor device of claim 14, further comprising an n-type silicon carbide substrate and an n ⁺ silicon carbide emitter region formed in the second conductivity type well region, and wherein the The first conductive type semiconductor layer includes a p-type silicon carbide drift layer, wherein the second conductive type well region includes an n-type silicon carbide n-well; Also includes a collector, disposed on the side of the n-type silicon carbide substrate away from the second conductivity type well region, the collector is a p-type silicon carbide collector, and wherein the wide-bandgap JFET region includes p-type silicon carbide JFET region. 16. The power semiconductor device of claim 15, further comprising a p-type silicon carbide current spreading layer, wherein the p-type silicon carbide JFET region is a portion of the p-type silicon carbide current spreading layer. 17. An insulated gate bipolar junction transistor comprising: a semiconductor layer of a first conductivity type having a first conductivity type on a wide band gap substrate having a second conductivity type opposite to the first conductivity type. Two conductivity types; a well region component, the well region component includes a first conductive type well region and a second conductive type well region; the first conductive type well region, having the first conductive type, is disposed in the first conductive type semiconductor layer; A two-conductivity-type well region, having a second conductivity type, is disposed in the first-conductivity-type well region and is completely surrounded by the first-conductivity-type well region; a wide bandgap emitter region located in the second conductive type well region and having a first conductive type; a wide bandgap collector region having the second conductivity type and on the second conductivity type well region; a wide bandgap JFET region having the first conductivity type and located between adjacent well region components; The first conductive type semiconductor layer includes at least two drift layers arranged in sequence, and the first conductive type well region is arranged in the first drift layer closest to the second drift layer and adjacent to the first drift layer The layers are overlapped to form an overlapping region; the doping concentration of the first drift layer is less than that of the second drift layer, and the doping concentration of the second drift layer is greater than the doping concentration of the second drift layer farther away from the first conductivity type well region. Doping concentrations of other drift layers. 18 . The insulated gate bipolar junction transistor of claim 17 , wherein a doping concentration of the first conductive type well region is greater than a doping concentration of the first conductive type semiconductor layer. 19 . 19 . The insulated gate bipolar junction transistor according to claim 18 , wherein the doping concentration of the first conductive type well region is 1×10 ¹⁶ cm ⁻³ to 5×10 ¹⁷ cm ⁻³ . The doping concentration of the first conductive type semiconductor layer is 1×10 ¹⁴ cm ⁻³ to 5×10 ¹⁷ cm ⁻³ . 20. The insulated gate bipolar junction transistor according to claim 18, further comprising a gate oxide layer located on adjacent well region components and a wide band gap JFET region between adjacent well region components and a gate oxide layer located on the a gate electrode on the gate oxide layer; The first conductivity type is p-type and the second conductivity type is n-type. 21. A process for preparing a power semiconductor device, comprising: forming a first conductive type semiconductor layer; forming a first conductive type well region within the first conductive type semiconductor layer; A second conductive type well region is formed in the first conductive type well region, and the second conductive type well region is completely surrounded by the first conductive type well region; The first conductivity type semiconductor layer includes at least two drift layers arranged in sequence, and the first conductivity type well region is arranged in the first drift layer closest to the second drift layer and adjacent to the first drift layer The layers are overlapped to form an overlapping region; the doping concentration of the first drift layer is less than that of the second drift layer, and the doping concentration of the second drift layer is greater than the doping concentration of the second drift layer farther away from the first conductivity type well region. Doping concentrations of other drift layers. 22. The preparation process according to claim 21, wherein forming the first conductive type well region in the first conductive type semiconductor layer comprises: A first mask layer is formed on the first conductive type semiconductor layer, the first mask layer is etched through a dry or wet etching process to form a first opening to expose part of the first conductive type semiconductor layer, and a first opening is formed by etching the first mask layer through a dry or wet etching process. An opening is formed and a dopant having a second conductivity type is implanted into the first conductivity type semiconductor layer by means of ion implantation or oblique ion implantation to form a second conductivity type well region. 23. The preparation process according to claim 22, wherein forming the first conductive type well region in the first conductive type semiconductor layer comprises: A second conductive type well region is formed in the first conductive type well region, including: The first mask layer near the first opening is etched by a dry or wet etching process, and the first conductive type semiconductor layer on which the first mask layer is etched is implanted by a self-alignment process A dopant having a first conductivity type to form a well region of the first conductivity type.

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