CN113129804B - Gate drive circuit - Google Patents

Abstract

The invention discloses a gate drive circuit, which comprises a plurality of shift registers for driving pixels on a gate line, wherein the shift registers respectively comprise a shift register circuit and a far-end pull-up matching circuit. The shift register circuit receives a control signal and a first clock signal to control the voltage of the first output node. The far-end pull-up matching circuit is coupled to the other end of the grid line through a second output node, comprises a pull-up transistor and a pull-down transistor, and controls the voltage of the second output node through the first clock signal, the pull-up node of the preceding stage shift temporary storage circuit and the second clock signal.

Description

Gate drive circuit

technical field

The present invention relates to a gate drive circuit, in particular to a method for reducing the border width of a shift register and increasing the rise/fall time of an output node voltage through the setting of a remote pull-up coordination circuit, thereby avoiding the problem of insufficient charging gate drive circuit.

Background technique

The driving circuit of the existing display panel will drive each pixel in the display area through the gate driving circuit, and then display the picture. However, due to the gradual increase in the size and resolution of display panels, and the increase in panel update frequency, the demand for gate drive circuits has also increased accordingly. However, in response to the design trend of narrow bezels of the display panel, reducing the area of the gate driving circuit around the panel will be an important goal when developing the display.

In various designs for reducing the circuit setup area, the gate drive circuit can be arranged by unilaterally setting the driving circuit or interleaved unilateral driving method, which can reduce the number of required transistors and achieve the goal of reducing the circuit setup area. However, the gate drive circuit driven on one side often has insufficient charging time at the other end of the scan line, resulting in inconsistent display at both ends of the panel, which affects the display quality of the display. If a gate drive circuit driven by both sides is provided, the area for disposing the transistors will be significantly increased, and the border width will be increased, which deviates from the goal of narrow borders.

In view of the above, the design of the existing gate drive circuit still has considerable defects. Therefore, the present invention aims at improving the deficiencies of the prior art by designing a gate drive circuit to solve the problems of the prior art , and then enhance the implementation and utilization of the industry.

Contents of the invention

In view of the above-mentioned problems in the prior art, the object of the present invention is to provide a gate drive circuit, which can reduce the circuit installation area and simultaneously solve the problem of insufficient charging through the arrangement of the remote pull-up coordination circuit.

According to the above purpose, an embodiment of the present invention proposes a gate-level drive circuit, which includes a series circuit of multiple shift registers, and the multiple shift registers are respectively connected to the gate lines of the display to drive the gate lines. For multiple pixels on the grid, multiple shift registers respectively include a shift register circuit and a remote pull-up coordination circuit. Wherein, the shift register circuit includes a first output node and a pull-up node, the first output node is coupled to one end of the gate line, the shift register circuit receives a control signal to pull up the voltage of the pull-up node, and receives the first clock signal to control the voltage of the first output node. The remote pull-up coordination circuit is coupled to the other end of the gate line through the second output node. The remote pull-up coordination circuit includes a pull-up transistor and a pull-down transistor. The first end of the pull-up transistor is coupled to the first clock signal, The second terminal of the pull-up transistor is coupled to the second output node, the control terminal of the pull-up transistor is coupled to the pull-up node of the previous shift register circuit, and the first terminal of the pull-down transistor is coupled to the second output node, The second terminal of the pull-down transistor is coupled to the voltage source, and the control terminal of the pull-down transistor is coupled to the second clock signal.

In an embodiment of the present invention, the shift register circuit may include a first shift register circuit and a second shift register circuit, and the first shift register circuit and the second shift register circuit are respectively arranged on the display two different sides. The remote pull-up coordination circuit may include a first remote pull-up coordination circuit and a second remote pull-up coordination circuit, the first shift register circuit and the first remote pull-up coordination circuit are interleavedly arranged on one side of the display, The second shift register circuit and the second remote pull-up coordination circuit are alternately arranged on the other side of the display.

In an embodiment of the present invention, the first clock signal may be a current-stage clock signal of the shift register, and the second clock signal may be a clock signal of a subsequent-stage shift register circuit.

In an embodiment of the present invention, the first clock signal may be a current-stage clock signal of the shift register, and the second clock signal may be an external clock signal. The phase of the first clock signal is twice the phase of the second clock signal.

In an embodiment of the present invention, the shift register circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, The tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor. Wherein, the first terminal of the first transistor is coupled to the first node, the second terminal of the first transistor is coupled to the anti-trace signal, and the control terminal of the first transistor is coupled to the second-stage driving signal. The first terminal of the second transistor is coupled to the positive scan signal, the second terminal of the second transistor is coupled to the first node, and the control terminal of the second transistor is coupled to the previous secondary driving signal. The first terminal of the third transistor is coupled to the first terminal of the resistor, the second terminal of the third transistor is coupled to the low voltage source, and the control terminal of the third transistor is coupled to the first node. The first terminal of the fourth transistor is coupled to the high voltage source, the second terminal of the fourth transistor is coupled to the second terminal of the resistor, and the control terminal of the fourth transistor is coupled to the second-stage clock signal. The first terminal and the control terminal of the fifth transistor are coupled to the reset signal, and the second terminal of the fifth transistor is coupled to the second node. The first terminal of the sixth transistor is coupled to the pull-up node, the second terminal of the sixth transistor is coupled to the low voltage source, and the control terminal of the sixth transistor is coupled to the second node. The first terminal of the seventh transistor is coupled to the first clock signal, and the control terminal of the seventh transistor is coupled to the third node. The first terminal of the eighth transistor is coupled to the fourth node, the second terminal of the eighth transistor is coupled to the low voltage source, and the control terminal of the eighth transistor is coupled to the second node. The first terminal of the ninth transistor is coupled to the fifth node, the second terminal of the ninth transistor is coupled to the pull-up node, and the control terminal of the ninth transistor is coupled to the high voltage source. The first terminal of the tenth transistor is coupled to the second terminal of the seventh transistor, the second terminal of the tenth transistor is coupled to the first output node, and the control terminal of the tenth transistor is coupled to the control terminal of the seventh transistor. The first terminal and the control terminal of the eleventh transistor are coupled to the fourth node, and the second terminal of the eleventh transistor is coupled to the first terminal of the sixth transistor. The first end of the twelfth transistor is coupled to the first clock signal, the second end of the twelfth transistor is coupled to the current control signal, and the control end of the twelfth transistor is coupled to the fifth node. The first end of the thirteenth transistor is coupled to the current control signal, the second end of the thirteenth transistor is coupled to the low voltage source, and the control end of the thirteenth transistor is coupled to the second node.

Based on the above, according to the gate drive circuit disclosed in the embodiment of the present invention, a gate drive circuit with double-side drive can be set on the display, and the double-side drive can be achieved through the setting of the remote pull-up matching circuit to reduce the voltage rise and fall time The effect is to avoid the problem of insufficient charge caused by the gate drive circuit of unilateral drive. On the other hand, through the arrangement of the shift register circuit and the remote pull-up coordination circuit, the arrangement space of the required transistors can be reduced, the border width of the display can be effectively reduced, and the goal of reducing the frame can be achieved.

Description of drawings

In order to make the technical features, content and advantages of the present invention and the technical effects that can be achieved more obvious, the present invention is hereby combined with the accompanying drawings, and described in detail in the form of embodiments as follows:

FIG. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a shift register circuit according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a shift register according to another embodiment of the present invention.

Explanation of reference signs:

10,20: shift register

11,21: shift register circuit

12,22: Remote pull-up coordination circuit

100: display

D2U: anti-sweep signal

G1, G2, G3, G4, Gn: the first output node

HC1: first clock signal

HC2: Second clock signal

HC3: Third clock signal

HC4: Fourth clock signal

HCn: the clock signal of this level

HCn+1: post-stage clock signal

Hn+2: post-secondary clock signal

N1: the first node

N2: second node

N3: the third node

N4: the fourth node

N5: fifth node

P1, P2, P3, P4: Pull up node signals

P, Pn-1: pull-up node

R: Resistance

R1, R2, R3, R4, Rn: Second output nodes

RPF: external clock signal

RPM1: First remote pull-up coordination circuit

RPM2: Second remote pull-up coordination circuit

RPM3: Third remote pull-up coordination circuit

RPM4: Fourth remote pull-up coordination circuit

RST: reset signal

S1: first scan line

S2: second scan line

S3: The third scan line

S4: the fourth scan line

SR1: the first shift register circuit

SR2: The second shift register circuit

SR3: The third shift register circuit

SR4: The fourth shift register circuit

SRn: nth stage shift register circuit

SROUT: Maximum load node

STn: current level control signal

STn+2: rear secondary drive signal

STn-2: the first two drive signals

T1～T13: first transistor～thirteenth transistor

T21, T23: pull-up transistors

T22, T24: Pull-down transistors

U2D: Forward scan signal

VGH: High Voltage Source

XDONB: Low Voltage Source

Detailed ways

In order to facilitate the understanding of the technical features, content and advantages of the present invention and the technical effects that can be achieved, the present invention is hereby combined with the accompanying drawings, and is described in detail as follows in the form of embodiments, and the accompanying drawings used herein, its gist It is only for the purpose of illustration and auxiliary description, not necessarily the true proportion and precise configuration of the present invention after implementation, so the attached drawings should not be interpreted based on the proportion and configuration relationship of the attached drawings, and the claims that limit the actual implementation of the present invention are complied with. Explain first.

In the drawings, the thickness or width of layers, films, panels, regions, light guides, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connection" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements. In addition, it should be understood that although the terms "first", "second", and "third" may be used herein to describe various elements, components, regions, layers and/or sections, it is used to refer to an element, component , region, layer and/or section from another element, component, region, layer and/or section. Therefore, they are for descriptive purposes only and should not be construed as indicating or implying relative importance or ordering relationship thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

Please refer to FIG. 1 , which is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. As shown in the figure, in the display 100, a plurality of gate lines are respectively connected to a plurality of pixels in the display area, and each pixel is driven by a gate driving circuit connected in series around the periphery, and each pixel is controlled to display its own grayscale brightness. Make the display 100 present the picture to be displayed.

In this embodiment, multiple pixel arrays can be set in the display area, and each column in the array can transmit gate driving signals through scanning lines, such as the first scanning line S1 and the second scanning line S2 shown in the figure , the third scanning line S3 , the fourth scanning line S4 , etc., the number of scanning lines varies according to the resolution of the display. In order to drive each pixel on each scanning line, a driving circuit is provided at both ends of the scanning line, and the driving circuit provides a gate driving signal of each pixel. The gate driving circuit includes a plurality of shift registers, and the shift registers respectively include a shift register circuit and a remote pull-up coordination circuit. As shown in the figure, both ends of the first scan line S1 include a first shift register circuit SR1 and a first remote pull-up coordination circuit RPM1, and both ends of the second scan line S2 include a second shift register circuit SR2 and the second remote pull-up coordination circuit RPM2, the two ends of the third scan line S3 include the third shift temporary storage circuit SR3 and the third remote pull-up coordination circuit RPM3, the two ends of the fourth scan line S4 include the fourth The shift register circuit SR4 and the fourth remote pull-up coordination circuit RPM4, and so on. In this embodiment, the first shift register circuit SR1 and the third shift register circuit SR3 are arranged on the left side of the line, and the second shift register circuit SR2 and the fourth shift register circuit SR4 are arranged on the right side of the line , that is, the current-stage shift register circuit and the next-stage shift register circuit are disposed on two different sides of the display 100 . Correspondingly, the first remote pull-up coordination circuit RPM1 and the third remote pull-up coordination circuit RPM3 are arranged on the right side of the line, and the second remote pull-up coordination circuit RPM2 and the fourth remote pull-up coordination circuit RPM4 are arranged on the line On the left side, the remote pull-up coordination circuit of the current level and the remote pull-up coordination circuit of the next level are also arranged on two different sides of the display 100 , and the remote pull-up coordination circuits and the shift register circuits are arranged alternately.

One end of the first scan line S1 is coupled to the first output node G1 of the first shift register circuit SR1, and the other end of the first scan line S1 is coupled to the second output of the first remote pull-up matching circuit RPM1. The node R1, the first shift register circuit SR1 and the first remote pull-up coordination circuit RPM1 all receive the first clock signal HC1, the first shift register circuit SR1 receives the first control signal, and controls the first output node G1 Voltage, the first remote pull-up coordination circuit RPM1 receives the control signal of the pull-up node of the previous stage shift register and the clock signal of the subsequent stage shift register to control the voltage of the second output node R1. One end of the continued second scan line S2 is coupled to the first output node G2 of the second shift register circuit SR2 , and the other end is coupled to the second output node R2 of the second remote pull-up coordination circuit RPM2 . Different from the first scan line S1, the position of the shift register and the remote pull-up coordination circuit of the second scan line S2 is opposite to that of the first scan line S1. The second shift register circuit SR2 and the second remote pull-up coordination circuit RPM2 receive the second clock signal HC2, the second shift register circuit SR2 receives the second control signal, controls the voltage of the first output node G2, and the second The remote pull-up coordination circuit RPM2 receives the control signal (the first pull-up node signal P1 ) of the preceding shift register and the clock signal (the third clock signal HC3 ) of the subsequent shift register. The third scan line S3 and the fourth scan line S4 are similar to the settings of the first scan line S1 and the second scan line S2, the third shift register circuit SR3 and the third remote pull-up coordination circuit RPM3 receive the third clock The signal HC3, the fourth shift temporary storage circuit SR4 and the fourth remote pull-up cooperation circuit RPM4 receive the fourth clock signal HC4, and cooperate with the third pull-up node signal P3, the fourth pull-up node signal P4, etc. to control the first The voltages of the output nodes G3, G4 and the second output nodes R3, R4. Subsequent scanning circuits are analogously deduced, and the shift register circuit and the remote pull-up coordination circuit are arranged at both ends of the line respectively, and the shift register circuit and the remote pull-up coordination circuit are arranged alternately on the side of the display 100 .

Taking the first scan line S1 as an example, by providing driving signals at both ends of the first scan line S1, the position of the maximum load node SROUT on the scan line can be located at the center of the first scan line S1, compared with a single-side arrangement In the shift temporary storage circuit, the maximum load node SROUT will be formed at the other end of the scan line and requires a larger voltage load. The time for the voltage to rise and fall is too long, and the problem of insufficient charging is likely to occur. This embodiment adopts the double-sided drive The setting can reduce the time required for voltage rise and fall to avoid the problem of insufficient charging. However, to set up the double-sided driving circuit, it is necessary to increase the circuit setting space on both sides of the display 100, which is not conducive to the development trend of the display 100 to reduce the frame. The remote pull-up matching circuit is provided to reduce the space originally required for the shift temporary storage circuit, so that the boundary of the display 100 can be reduced by 20%, and the goal of reducing the space for the boundary circuit is indeed achieved. The shift register in the gate driving circuit, that is, the shift register circuit and the remote pull-up coordination circuit will be described in more detail in the following embodiments.

Please refer to FIG. 2 , which is a schematic diagram of a shift register according to an embodiment of the present invention. As shown in the figure, the gate drive circuit includes n-stage shift registers 10, which respectively include a shift register circuit 11 and a remote pull-up coordination circuit 12. The number of stages of the shift register 10 can be determined according to the display to determine the resolution. In the shift register circuit 11, the nth stage shift register circuit SRn is connected to one end of the scan line through the first output node Gn, and the nth stage shift register circuit SRn is coupled to the high voltage source VGH and the low voltage The source XDONB receives the forward scan signal U2D, the reverse scan signal D2U, the local clock signal HCn, the local control signal STn and the reset signal RST, and controls the voltage of the first output node Gn to drive the pixels on the scan line.

The remote pull-up coordination circuit 12 is connected to the other end of the scan line through the second output node Rn. The remote pull-up coordination circuit 12 includes a pull-up transistor T21 and a pull-down transistor T22. The first end of the pull-up transistor T21 is coupled to the current stage For the clock signal HCn, the second terminal of the pull-up transistor T21 is coupled to the second output node Rn, and the control terminal of the pull-up transistor T21 is coupled to the pull-up node Pn-1 of the previous shift register circuit. The first terminal of the pull-down transistor T22 is coupled to the second output node Rn, the second terminal of the pull-down transistor T22 is coupled to the low voltage source XDONB, and the control terminal of the pull-down transistor T22 is coupled to the rear of the shift register of the next stage Class clock signal HCn+1. Since the remote pull-up cooperation circuit 12 does not need the same number of transistors as the shift register circuit 11, it can effectively save space in the circuit layout space. Compared with the setting of the same shift register circuit on both sides, The installation area can be reduced by 20%.

Through the clock signal HCn of this stage and the signal control of the pull-up node Pn-1 of the previous-stage shift register circuit, the pull-up transistor T21 can increase the voltage rise time of the gate drive circuit 10, and through the low-voltage source XDONB and the subsequent stage clock Controlled by the signal HCn+1, the pull-down transistor T22 can increase the voltage drop time of the gate drive circuit 10 . In the case of the reduction of the above-mentioned installation area, the rising and falling time of the voltage can be increased at the same time, so as to avoid the problem of insufficient charging.

Please refer to FIG. 3 , which is a schematic diagram of a shift register circuit according to an embodiment of the present invention. As shown in the figure, the nth stage shift register circuit SRn is a driving circuit formed by 13 transistors, which includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, The sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13. The first terminal of the first transistor T1 is coupled to the first node N1, the second terminal of the first transistor T2 is coupled to the anti-trace signal D2U, and the control terminal of the first transistor T1 is coupled to the second-stage driving signal STn+2 . The first terminal of the second transistor T2 is coupled to the positive scan signal U2D, the second terminal of the second transistor T2 is coupled to the first node N1, and the control terminal of the second transistor T1 is coupled to the previous secondary driving signal STn-2 . The switch of the first transistor T1 or the second transistor T2 determines the forward scan or reverse scan direction of the shift register circuit.

A first terminal of the third transistor T3 is coupled to the first terminal of the resistor R, a second terminal of the third transistor T3 is coupled to the low voltage source XDONB, and a control terminal of the third transistor T3 is coupled to the first node N1. The first terminal of the fourth transistor T4 is coupled to the high voltage source VGH, the second terminal of the fourth transistor T4 is coupled to the second terminal of the resistor R, and the control terminal of the fourth transistor T4 is coupled to the secondary clock signal HCn +2. The first terminal and the control terminal of the fifth transistor T5 are coupled to the reset signal RST, and the second terminal of the fifth transistor T5 is coupled to the second node N2. A first terminal of the sixth transistor T6 is coupled to the pull-up node P, a second terminal of the sixth transistor T6 is coupled to the low voltage source XDONB, and a control terminal of the sixth transistor T6 is coupled to the second node N2.

A first terminal of the seventh transistor T7 is coupled to the local clock signal HCn, and a control terminal of the seventh transistor T7 is coupled to the third node N3. A first terminal of the eighth transistor T8 is coupled to the fourth node N4, a second terminal of the eighth transistor T8 is coupled to the low voltage source XDONB, and a control terminal of the eighth transistor T8 is coupled to the second node N2. A first terminal of the ninth transistor T9 is coupled to the fifth node N5, a second terminal of the ninth transistor T9 is coupled to the pull-up node P, and a control terminal of the ninth transistor T9 is coupled to the high voltage source VGH. The first terminal of the tenth transistor T10 is coupled to the second terminal of the seventh transistor T7, the second terminal of the tenth transistor T10 is coupled to the first output node Gn, and the control terminal of the tenth transistor T10 is coupled to the seventh transistor The control terminal of T7. The first terminal and the control terminal of the eleventh transistor T11 are coupled to the fourth node N4, and the second terminal of the eleventh transistor T11 is coupled to the first terminal of the sixth transistor T6. The first terminal of the twelfth transistor T12 is coupled to the clock signal HCn of the current stage, the second terminal of the twelfth transistor T12 is coupled to the control signal STn of the current stage, and the control terminal of the twelfth transistor T12 is coupled to the fifth node N5. The first end of the thirteenth transistor T13 is coupled to the control signal STn of the current stage, the second end of the thirteenth transistor T13 is coupled to the low voltage source XDONB, and the control end of the thirteenth transistor T13 is coupled to the second node N2 .

Please refer to FIG. 4 , which is a schematic diagram of a shift register according to another embodiment of the present invention. As shown in the figure, the gate drive circuit includes n-stage shift registers 20, which respectively include a shift register circuit 21 and a remote pull-up coordination circuit 22. The number of stages of the shift register 20 can be determined according to the display to determine the resolution. In the shift register circuit 21, the nth stage shift register circuit SRn is connected to one end of the scan line through the first output node Gn, and the nth stage shift register circuit SRn is coupled to the high voltage source VGH and the low voltage The source XDONB receives the forward scan signal U2D, the reverse scan signal D2U, the local clock signal HCn, the local control signal STn and the reset signal RST, and controls the voltage of the first output node Gn to drive the pixels on the scan line.

In this embodiment, the remote pull-up coordination circuit 22 is connected to the other end of the scan line through the second output node Rn. The remote pull-up coordination circuit 22 includes a pull-up transistor T23 and a pull-down transistor T24. The first pull-up transistor T23 One end is coupled to the clock signal HCn of the current stage, the second end of the pull-up transistor T23 is coupled to the second output node Rn, and the control end of the pull-up transistor T23 is coupled to the pull-up node Pn- 1. The first terminal of the pull-down transistor T24 is coupled to the second output node Rn, the second terminal of the pull-down transistor T22 is coupled to the low voltage source XDONB, and the control terminal of the pull-down transistor T24 is coupled to the external clock signal RPF. The external clock signal RPF can be an independent clock signal source outside the clock signal driven by the shift register, and the phase of the clock signal can be twice the phase of the clock signal HCn of this stage. The pull-down transistor T24 can be controlled by the external clock signal RPF. Increase the voltage drop time more efficiently.

The above descriptions are illustrative only, not restrictive. Any equivalent modification or change without departing from the concept and scope of the present invention shall be included in the claims.

Claims (7)

1. A gate drive circuit, comprising a series circuit of a plurality of shift registers, the plurality of shift registers are respectively connected to a gate line of a display to drive a plurality of shift registers on the gate line pixel, the multiple shift registers respectively include: A shift register circuit, including a first output node and a pull-up node, the first output node is coupled to one end of the gate line, the shift register circuit receives a control signal to pull the pull-up node and receiving a first clock signal to control the voltage of the first output node; and A remote pull-up coordination circuit, coupled to the other end of the gate line through a second output node, the remote pull-up coordination circuit includes a pull-up transistor and a pull-down transistor, the first end of the pull-up transistor coupled to the first clock signal, the second end of the pull-up transistor is coupled to the second output node, the control end of the pull-up transistor is coupled to the pull-up node of the previous shift register circuit, and the pull-down The first terminal of the transistor is coupled to the second output node, the second terminal of the pull-down transistor is coupled to a voltage source, and the control terminal of the pull-down transistor is coupled to a second clock signal. 2. The gate drive circuit according to claim 1, wherein the shift register circuit comprises a first shift register circuit and a second shift register circuit, the first shift register circuit and the The second shift register circuit is respectively arranged on two different sides of the display. 3. The gate drive circuit as claimed in claim 2, wherein the remote pull-up coordination circuit comprises a first remote pull-up coordination circuit and a second remote pull-up coordination circuit, the first shift register The circuit and the first remote pull-up coordination circuit are alternately arranged on one side of the display, and the second shift register circuit and the second remote pull-up coordination circuit are alternately arranged on the other side of the display. 4. The gate driving circuit as claimed in claim 1, wherein the first clock signal is a current clock signal of the shift register, and the second clock signal is a clock signal of a subsequent shift register circuit. 5. The gate driving circuit as claimed in claim 1, wherein the first clock signal is a current clock signal of the shift register, and the second clock signal is an external clock signal. 6. The gate driving circuit as claimed in claim 5, wherein the phase of the first clock signal is twice the phase of the second clock signal. 7. The gate driving circuit as claimed in claim 1, wherein the shift register circuit comprises: A first transistor, the first terminal of the first transistor is coupled to a first node, the second terminal of the first transistor is coupled to a reverse scan signal, and the control terminal of the first transistor is coupled to a rear two stage drive signal; A second transistor, the first terminal of the second transistor is coupled to a positive scan signal, the second terminal of the second transistor is coupled to the first node, and the control terminal of the second transistor is coupled to the first two stage drive signal; A third transistor, the first end of the third transistor is coupled to a first end of a resistor, the second end of the third transistor is coupled to a low voltage source, the control end of the third transistor is coupled to the first node; A fourth transistor, the first end of the fourth transistor is coupled to a high voltage source, the second end of the fourth transistor is coupled to a second end of the resistor, and the control end of the fourth transistor is coupled to A post-secondary clock signal; a fifth transistor, the first terminal and the control terminal of the fifth transistor are coupled to a reset signal, and the second terminal of the fifth transistor is coupled to a second node; A sixth transistor, the first terminal of the sixth transistor is coupled to the pull-up node, the second terminal of the sixth transistor is coupled to the low voltage source, and the control terminal of the sixth transistor is coupled to the second node; a seventh transistor, the first terminal of the seventh transistor is coupled to the first clock signal, and the control terminal of the seventh transistor is coupled to a third node; An eighth transistor, the first end of the eighth transistor is coupled to a fourth node, the second end of the eighth transistor is coupled to the low voltage source, the control end of the eighth transistor is coupled to the second node; A ninth transistor, the first terminal of the ninth transistor is coupled to a fifth node, the second terminal of the ninth transistor is coupled to the pull-up node, and the control terminal of the ninth transistor is coupled to the high voltage source; A tenth transistor, the first terminal of the tenth transistor is coupled to the second terminal of the seventh transistor, the second terminal of the tenth transistor is coupled to the first output node, the control terminal of the tenth transistor is coupled connected to the control terminal of the seventh transistor; an eleventh transistor, the first terminal and the control terminal of the eleventh transistor are coupled to the fourth node, and the second terminal of the eleventh transistor is coupled to the first terminal of the sixth transistor; A twelfth transistor, the first end of the twelfth transistor is coupled to the first clock signal, the second end of the twelfth transistor is coupled to a current level control signal, the control end of the twelfth transistor coupled to the fifth node; and A thirteenth transistor, the first end of the thirteenth transistor is coupled to the current stage control signal, the second end of the thirteenth transistor is coupled to the low voltage source, and the control end of the thirteenth transistor is coupled to at the second node.

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