CN113114262B - Efficient direct function mapping analog-to-digital conversion circuit - Google Patents

Abstract

The invention discloses a high-efficiency direct function mapping analog-to-digital conversion circuit, which mainly comprises: the circuit comprises a sample hold circuit, a comparator circuit, a DAC circuit and a register circuit. The circuit can generate a reference voltage with a special function shape along with clock variation at one end of a comparator through a logic control circuit by directly integrating an LUT circuit into a globally shared DAC circuit. Some special activation function mapping can be directly completed aiming at the simulation deep learning hardware acceleration network. The method greatly reduces the area of the circuit required for realizing the activation function, accelerates the calculation process and greatly improves the energy efficiency of the whole calculation circuit. Meanwhile, the invention optimizes the structure of the dynamic comparator aiming at the problems of parasitic parameters of the current comparator and greatly reduces the coupling effect between input and output. The invention only needs to modify the digital logic control part of the DAC, and has the characteristics of strong practicability, high energy efficiency, low power consumption, simple realization and the like.

Description

An Efficient Direct Function Mapping Analog-to-Digital Conversion Circuit

technical field

The invention relates to the technical field of analog-to-digital converters, in particular to an efficient direct function function mapping analog-to-digital conversion circuit.

Background technique

Traditional computing systems based on the von Neumann architecture are limited by the difficulty of scaling down the size of transistors and the problem of "storage walls", which can no longer meet the demand for computing power in the era of artificial intelligence (AI). The in-memory computing system based on analog computing can provide low-latency and high-efficiency parallel multiply-accumulate operations for AI computing, showing great potential and advantages in accelerating AI computing. Among them, the pulse neural network (SNN) based on "pulse" communication, its analog computing framework is expected to reduce the power consumption of computing while realizing artificial intelligence. In the design of each functional module of the dedicated hardware circuit of SNN, the design of the ADC circuit module plays a key role. High energy efficiency, low power consumption, and simple ADC circuits have good application prospects in the design of memory-computing integrated circuit architectures such as pulse neural networks (SNN) and convolutional neural networks (CNN).

Please refer to FIG. 1 , which shows a schematic diagram of a single-layer deep learning network implemented by a simulated storage-computing integrated computing system. Analog computing is a means to achieve efficient multiply-accumulate calculations. Based on the analog multiplication and accumulation calculation unit, the general operation process is as follows: the DAC digital-to-analog conversion circuit converts the digital input signal into a corresponding analog voltage, and realizes the multiplication operation of the input voltage and weight through the storage circuit unit and converts it into a current, and the current passes through the wire Collected together to complete the accumulation operation, the current-voltage conversion circuit converts the obtained accumulated current into an accumulated voltage, and finally converts the analog weighted voltage into a digital signal through the ADC. The digital signal obtained by the analog calculation unit finally needs to pass through the digital activation function circuit to obtain the final calculation result of the current layer of the neural network and output it to the calculation module of the next layer of the neural network.

See the ADC circuit in Figure 2, which shows an ADC circuit with a shared DAC structure. This structure can greatly reduce the area overhead of the overall ADC circuit in the analog calculation unit while supporting fully parallel multiply-accumulate operations. It works by digitally controlling the globally shared DAC to generate an incremental reference voltage signal, then comparing the reference signal with the analog voltage signal to be converted in turn to generate square wave signals with different widths, and finally converting them into digital signals through a digital counter . When the number of ADC bits is high, this method will have a large conversion delay, so this method is suitable for scenarios with relatively low precision and large-scale analog matrix operations.

Please refer to Figure 3, which shows a schematic diagram of some deep learning activation functions. Common ones include sigmoid, ReLU, Leak-ReLU, etc. In order to implement these activation functions flexibly, LUT (look-up table) circuits are usually used. For the circuit shown in Figure 2, the output of the ADC is used as the input of the LUT circuit to realize the activation function. Since the area overhead of a single LUT circuit is large, this method must reduce the area overhead by multiplexing the mode of the LUT circuit unit, but it also greatly increases the calculation delay of the overall circuit.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a high-efficiency direct function function mapping analog-to-digital conversion circuit, which can reduce the calculation delay of the analog calculation module, and has the advantages of strong practicability, high energy efficiency, low power consumption, and simple implementation.

The purpose of the present invention is achieved through the following technical solutions:

A high-efficiency direct function function mapping analog-to-digital conversion circuit, comprising: a sample-and-hold circuit, a comparator circuit, a DAC circuit, and a register circuit; wherein:

The DAC circuit is a globally shared circuit structure, which includes: a logical control circuit, a LUT circuit, and a DAC capacitor array connected in sequence; the output end of the DAC capacitor array is connected to the inverting input ends of all comparator circuits; the logic control circuit generates incremental The binary data of the LUT circuit is converted into the control signal of the corresponding DAC capacitor array, thereby generating different reference voltages;

The positive input terminal of each comparator circuit is separately connected to a sample-and-hold circuit, the input is the analog voltage signal to be converted output by the sample-and-hold circuit, and the output terminal is separately connected to a register circuit; when the state of the comparator circuit changes, the corresponding The register circuit saves the binary data output by the logic control circuit, and obtains a binary analog-to-digital conversion result.

It can be seen from the technical solution provided by the present invention that, on the one hand, the LUT circuit with the activation function function of the deep neural network is integrated into the shared DAC circuit, which greatly reduces the conversion delay of the activation function circuit; and, in Under the premise of not losing the calculation parallelism, only one LUT circuit can realize the realization of the fully parallel neural network activation function, which reduces the power consumption and area of the neural network accelerator. On the other hand, the logic control circuit in the shared DAC circuit generates the counting signal and directly controls whether it is input to the register storage unit through the output of the comparator, which simplifies the storage scheme of the output signal and reduces unnecessary calculation energy consumption.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings on the premise of not paying creative work.

Fig. 1 is the schematic diagram that utilizes simulation matrix computing system to realize single-layer deep learning network provided by the background technology of the present invention;

Fig. 2 is the existing shared DAC type ADC structural schematic diagram provided by the background technology of the present invention;

FIG. 3 is a schematic diagram of an activation function for deep learning provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of an efficient direct functional function mapping analog-to-digital conversion circuit provided by an embodiment of the present invention;

5 is a schematic structural diagram of a comparator circuit provided by an embodiment of the present invention;

FIG. 6 is a timing waveform diagram provided by an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

An embodiment of the present invention provides a high-efficiency direct function function mapping analog-to-digital conversion circuit, which can realize a fully parallel activation function by using only one LUT circuit unit, and the circuit is applied to a Computing-In-Memory (Computing-In-Memory) architecture Among them, as shown in Figure 4, the circuit mainly includes: sample and hold circuit (S/H circuit), comparator circuit, DAC circuit and register circuit; where:

The DAC circuit is a globally shared circuit structure, which includes: a logical control circuit, a LUT circuit, and a DAC capacitor array connected in sequence; the output end of the DAC capacitor array is connected to the inverting input ends of all comparator circuits; the logic control circuit generates incremental The binary data of the LUT circuit is converted into the control signal of the corresponding DAC capacitor array, thereby generating different reference voltages;

The positive input terminal of each comparator circuit is separately connected to a sample-and-hold circuit, the input is the analog voltage signal to be converted output by the sample-and-hold circuit, and the output terminal is separately connected to a register circuit; when the state of the comparator circuit changes, the corresponding The register circuit saves the binary data (count value) output by the logic control circuit, and obtains the binary analog-to-digital conversion result.

For ease of understanding, the various parts and working principles of the circuit are described in detail below.

1. DAC circuit.

In the embodiment of the present invention, the DAC circuit is a globally shared circuit, which mainly includes three parts: a logic control circuit, a LUT circuit and a DAC capacitor array.

1. Logic control circuit.

As shown in FIG. 4 , the logic control circuit mainly includes: a multi-bit counter (Counter) and a timing control logic circuit (Logic Control).

1) The control terminal of the sequential control logic circuit is connected to each sampling and holding circuit and comparator circuit, and the output generates various stages in the analog-to-digital conversion circuit process (sampling/holding, reference potential generation, comparison of analog voltage and digital output data storage) timing control signal.

2) The multi-bit counter is connected to the LUT circuit and all register circuits.

2. LUT circuit.

The LUT circuit is equivalent to a piece of RAM, and the logic control circuit generates incremental binary data to be input to the LUT circuit as an address signal of the LUT circuit, and the LUT circuit finds out a pre-defined logic result. The LUT circuit is integrated into the globally shared DAC circuit, and the behavior of the capacitor array in the DAC is controlled through the output of the LUT, so that the global reference voltage generated by the DAC does not increase proportionally but changes according to a preset function rule.

The internal working process of the LUT circuit includes: pre-selecting an activation function, in order to make the final data result fit the activation function, after selecting an activation function, calculate the inverse function of the activation function, according to the fitting Combine precision, quantize the inverse function; use the independent variable of the inverse function as the address of the LUT circuit, and the dependent variable as the logic result stored in RAM in the LUT; after receiving the incremental binary data, output the data stored in the lookup table to the DAC in turn The switch circuit of the capacitor array controls the DAC capacitor array to generate different reference voltages.

Taking the sigmoid function as an example, the sigmoid function is: Y=1/(1+e ^−x ). Its inverse function is Y=ln(x/(1-x)), and the arguments of the inverse function are uniformly divided as LUT addresses. When x=k*x ₀ , the number k converted into binary can be used as an address signal, and x ₀ is the minimum quantization precision. At this time, the value stored in the LUT at address k should be Y=ln(k*x ₀ /(1-k*x ₀ )).

3. DAC capacitor array.

The DAC capacitor array includes two input terminals, the first input terminal is connected to the output terminal of the LUT circuit, and the second input terminal inputs the reference voltage signal V _REF .

The DAC capacitor array adopts a segmented capacitor strategy, one end of the capacitor is controlled by a switch to switch to different voltages, and the control signal of the switch comes from the LUT circuit. Specifically, the strategy of segmented capacitors is adopted, and the method of bridging capacitors reduces the ratio between the maximum capacitance value and the minimum capacitance value in the circuit, greatly reducing the total capacitance value of the circuit. This kind of capacitor array can actually be regarded as two sets of capacitor array branches, both of which adopt a common charge distribution structure, one of which converts the high bit of the input digital, and the other converts the low bit of the input digital , the value of the low-level analog output is reduced several times after passing through the voltage-dividing capacitor, and then superimposed with the high-level analog output. Compared with the ordinary charge distribution structure, this capacitance array construction method has a small area, and the capacitance difference is reduced, so higher precision can be obtained. The input signal of the capacitor array includes V _REF , GND, and the output control signal of the LUT, and the output voltage signal V _DAC is directly connected to the negative terminals of all comparators.

Second, the comparator circuit.

In the embodiment of the present invention, all the comparator circuits have the same structure and can be clock-controlled dynamic comparators. The comparators compare the signals at their positive and negative input terminals to generate a 1-digit digital code. As shown in Figure 5, the clock-controlled dynamic comparator includes: two pre-amplification circuits and a latch circuit, and only has dynamic power consumption at the clock edge, and is equivalent to a static latch with only static power consumption at other times. The dynamic comparator in this embodiment is optimized based on the traditional dynamic comparator.

In order to reduce the coupling effect from the output to the input, the two pre-amplification circuits adopt the input strategy of PMOS transistor and NMOS transistor respectively (P2, P3, N4, N5 in Figure 5), and at the same time, cross-coupling is adopted between the two pre-amplification circuits The PMOS and NMOS are connected, which can greatly reduce the coupling effect between input and output (P4, P7, N3, N7 in the figure). Both the load tube and the bias tube of the two pre-amplification circuits are controlled by clock, which can eliminate the static power consumption of the pre-amplification circuit.

The latch circuit uses the cross-coupling structure of the PMOS transistor and the NMOS transistor to save the comparison value (that is, the comparison result of the reference voltage and the analog voltage); when the clock is high, it is a latch state, and when the clock is low, it is a reset state ( Both OP and ON are set to 1). The compare state is entered only when the clock transitions from low to high. Input V+ and V- (V+, V- represent the forward input and reverse input respectively, as mentioned before, V+ is connected to the analog voltage to be converted, and V- is connected to the output reference voltage of the DAC array) through the pre-amplification circuit Controlling P10 and P11 makes OP and ON switch from GND to VDD at different speeds. Since the positive feedback with fast conversion speed will suppress the slow conversion speed, the end with fast conversion speed will be high, and the end with slow conversion speed will be low, so as to obtain the comparison result.

The specific structure is shown in Figure 5. The gate of the PMOS transistor P1 is connected to the CLKN signal, the source is connected to VDD, and the drain is connected to the sources of the PMOS transistors P2 and P3. The CLKN signal is a local clock signal; the gate of the PMOS transistor P2 Input V- signal, the drain is connected to the drain of NMOS transistor N1; the gate of PMOS transistor P3 inputs V+ signal, and the drain is connected to the drain of NMOS transistor N2; the gates of NMOS transistors N1 and N2 are connected and input CLKN signal, the source Both poles are connected to GND; the source of PMOS transistor P4 is connected to VDD, the drain is connected to the drains of PMOS transistor P3 and NMOS transistor N2, and the gate of NMOS transistor N3, and the gate is connected to the drains of NMOS transistors N3 and N4, and The drain of the PMOS transistor P5, and the connection point is marked as node AP; the source of the PMOS transistor P5 is connected to VDD, the gate is connected to the gate of the PMOS transistor P6, and the CLK signal is input; the gate of the NMOS transistor N4 inputs the V- signal, and the source The pole is connected to the source of the NMOS transistor N5 and the drain of the NMOS transistor N6; the gate of the NMOS transistor N6 inputs the CLK signal, and the source is connected to GND; the gate of the NMOS transistor N5 inputs the V+ signal, and the drain is connected to the drain of the PMOS transistor P6 and The gate of the PMOS transistor P7 and the drain of the NMOS transistor N7 are recorded as the node AN; the sources of the PMOS transistors P6 and P7 are connected to the VDD signal, and the drain of the PMOS transistor P7 is connected to the NMOS transistor N7 The gate of NMOS transistor N7 is connected to GND; the gate of NMOS transistor N8 is connected to CLKN signal, the drain is connected to the drain of NMOS transistor N9, the drain of PMOS transistor P10, and the gates of PMOS transistor P9 and NMOS transistor N11 , the sources of the NMOS transistors N8 and N9 are connected to GND; the gate of the NMOS transistor N9 is connected to the gate of the PMOS transistor P8 and connected to the drains of the NMOS transistors N11 and N12 and the PMOS transistor P11 through wires; the NMOS transistors N11 and N12 The source is connected to GND, the gate of NMOS transistor N12 inputs CLKN signal, the gates of PMOS transistor P10 and PMOS transistor P11 are respectively connected to node AN and node AP, and the sources of PMOS transistor P10 and PMOS transistor P11 are respectively connected to PMOS transistors P8 and PMOS transistors The drains of the transistor P9 are connected; the sources of the PMOS transistors P8 and P9 are both connected to VDD.

In addition, when it is detected that the output state of the comparator changes during the data conversion phase, the clock of the corresponding comparator circuit is locked to control the comparator circuit to be in a sleep state, so as to reduce power consumption.

3. Sample and hold circuit.

The sample-and-hold circuit samples the current analog voltage value to be converted, and holds it at the positive input terminal of the comparator circuit during the entire data conversion period. Generally, a sampling capacitor can be used to maintain the analog voltage value. As shown in FIG. 4 , V ₁ -V _n are the analog voltages output from each sample-and-hold circuit to the corresponding comparator circuit, and each analog voltage is independent of each other.

Fourth, the register circuit.

The data register is used to save the final ADC output data, which is different from the previous construction method. Since the reference analog voltage signal generated by the DAC increases step by step, when the output state of the comparator changes, it can be considered that the comparison of the current channel is completed, and the current count value of the counter can be directly transmitted to the data register of the current channel, that is, to obtain Final binary ADC conversion result. At the same time, the clock of the comparator of the current channel can be locked to make the comparator sleep to reduce power consumption.

The working states and characteristics of the analog-to-digital conversion circuit will be described in detail below in conjunction with the timing waveform diagram shown in FIG. 6 . Among them: CLK represents the ADC clock; En_LUT represents the write port of the lookup table circuit, which is active at high level; En_SH represents the enable signal of the sample and hold circuit, which is active at high level; En_DAC represents the enable signal of the DAC array, which is active at high level; CLK_DAC represents the DAC The clock of the array; VSH and VDAC respectively represent the sample-and-hold analog voltage signal and the reference voltage signal generated by the DAC; Out_comp represents the output signal of the comparator; En_comp represents the comparator enable signal, which is active at high level; DAC_counter represents the output of the global counter Signal. Before the analog-to-digital conversion circuit is running, a specific activation function needs to be selected first, and the corresponding data is pre-stored in the RAM in the LUT in the PH1 stage. In the PH2 stage, open the sample and hold circuit, input the analog voltage to be converted to the positive port of the comparator through the sample and hold circuit, and set the count value of the counter to 0 at the same time. The PH2 stage starts to open the dynamic comparator so that the dynamic comparator starts to work. In the PH3 stage, the DAC starts to work. According to the clock of the DAC, the discrete incremental reference analog voltage value is compared with the sample-and-hold voltage collected in the PH2 stage. In the PH3 stage, only when V _DAC >V _S/H is low level. In order to reduce power consumption, when the output of the comparator is low in this stage, the comparator of the corresponding channel is turned off, and at the same time, the value of the current counter is output to the corresponding register to obtain the digital conversion value of the analog voltage of the current channel.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person familiar with the technical field can easily conceive of changes or changes within the technical scope disclosed in the present invention. Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (3)

1. A high-efficiency direct function function mapping analog-to-digital conversion circuit, is characterized in that, comprises: sample and hold circuit, comparator circuit, DAC circuit and register circuit; Wherein: The DAC circuit is a globally shared circuit structure, which includes: a logical control circuit, a LUT circuit, and a DAC capacitor array connected in sequence; the output end of the DAC capacitor array is connected to the inverting input ends of all comparator circuits; the logic control circuit generates incremental The binary data of the LUT circuit is converted into the control signal of the corresponding DAC capacitor array, thereby generating different reference voltages; The positive input terminal of each comparator circuit is separately connected to a sample-and-hold circuit, the input is the analog voltage signal to be converted output by the sample-and-hold circuit, and the output terminal is separately connected to a register circuit; when the state of the comparator circuit changes, the corresponding The register circuit saves the binary data output by the logic control circuit, and obtains the binary analog-to-digital conversion result; The logic control circuit includes: a multi-bit counter and a timing control logic circuit; wherein, the control terminal of the timing control logic circuit is connected to each sample-and-hold circuit and a comparator circuit, and the output generates the signals of each stage in the process of the analog-to-digital conversion circuit. timing control signal; the multi-bit counter connects the LUT circuit and all register circuits; The logic control circuit generates incremental binary data to be input to the LUT circuit, and as the address signal of the LUT circuit, the LUT circuit finds a pre-defined logic result; the internal working process of the LUT circuit includes: after pre-selecting an activation function, calculating Take the inverse function of the activation function, quantify the inverse function according to the fitting accuracy; use the independent variable of the inverse function as the address of the LUT circuit, and the dependent variable as the logical result stored in RAM in the LUT; The data stored in the lookup table is output to the switch circuit of the DAC capacitor array, thereby controlling the DAC capacitor array to generate different reference voltages; The DAC capacitor array includes two input terminals, the first input terminal is connected to the output terminal of the LUT circuit, and the second input terminal inputs a reference voltage signal; the DAC capacitor array adopts a segmented capacitor strategy, and one end of the capacitor is selected by a switch control. To different voltages, the control signal of the switch comes from the LUT circuit. 2. a kind of high-efficiency direct functional function mapping analog-to-digital conversion circuit according to claim 1, is characterized in that, described comparator circuit is the dynamic comparator of clock control, comprises: two preamplification circuits and latch circuit; Among them, the two pre-amplification circuits adopt the input strategy of PMOS tube and NMOS tube respectively. The two pre-amplification circuits are connected by cross-coupled PMOS and NMOS. The load tube and bias tube of the two pre-amplification circuits are controlled by the clock. ;The latch circuit uses the cross-coupling structure of the PMOS transistor and the NMOS transistor to save the comparison value; When a transition of the output state of the comparator is detected during the data conversion phase, the clock that locks the corresponding comparator circuit controls the comparator circuit to be in a dormant state. 3. according to claim 1 and 2 described a kind of efficient direct functional function mapping analog-to-digital conversion circuit, it is characterized in that, the structure of described comparator circuit is: The gate of the PMOS transistor P1 is connected to the CLKN signal, the source is connected to VDD, and the drain is connected to the sources of the PMOS transistors P2 and P3, and the CLKN signal is a local clock signal; The gate of the PMOS transistor P2 inputs the V- signal, and the drain is connected to the drain of the NMOS transistor N1; The gate of the PMOS transistor P3 inputs the V+ signal, and the drain is connected to the drain of the NMOS transistor N2; wherein, the V- signal and the V+ signal respectively represent the reverse input terminal signal and the positive input terminal signal of the comparator circuit; The gates of the NMOS transistors N1 and N2 are connected to input the CLKN signal, and the sources are connected to GND; The source of the PMOS transistor P4 is connected to VDD, the drain is connected to the drains of the PMOS transistor P3 and the NMOS transistor N2, and the gate of the NMOS transistor N3, and the gate is connected to the drains of the NMOS transistors N3 and N4, and the drain of the PMOS transistor P5 , and record the connection point as node AP; The source of the PMOS transistor P5 is connected to VDD, the gate is connected to the gate of the PMOS transistor P6 and a CLK signal is input, and the CLK signal is an ADC clock signal; The gate of the NMOS transistor N4 inputs the V- signal, and the source is connected to the source of the NMOS transistor N5 and the drain of the NMOS transistor N6; The gate of NMOS transistor N6 inputs the CLK signal, and the source is connected to GND; The gate of the NMOS transistor N5 inputs the V+ signal, and the drain is connected to the drain of the PMOS transistor P6, the gate of the PMOS transistor P7, and the drain of the NMOS transistor N7, and the connection point is marked as node AN; The sources of the PMOS transistors P6 and P7 are connected to the VDD signal, the drain of the PMOS transistor P7 is connected to the gate of the NMOS transistor N7, and the source of the NMOS transistor N7 is connected to GND; The gate of the NMOS transistor N8 is connected to the CLKN signal, the drain is connected to the drain of the NMOS transistor N9, the drain of the PMOS transistor P10, and the gates of the PMOS transistor P9 and the NMOS transistor N11, and the sources of the NMOS transistors N8 and N9 are connected to GND; The gate of the NMOS transistor N9 is connected to the gate of the PMOS transistor P8 and connected to the drain of the NMOS transistors N11 and N12 and the PMOS transistor P11 through wires; The sources of NMOS transistors N11 and N12 are connected to GND, the gate of NMOS transistor N12 inputs CLKN signal, the gates of PMOS transistor P10 and PMOS transistor P11 are respectively connected to node AN and node AP, and the sources of PMOS transistor P10 and PMOS transistor P11 are respectively connected to The drains of the PMOS transistor P8 and the PMOS transistor P9 are connected; The sources of the PMOS transistors P8 and P9 are both connected to VDD.

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