CN113113511B - Preparation method of detector for inhibiting side wall leakage current by using passivation layer negative electrification - Google Patents
Preparation method of detector for inhibiting side wall leakage current by using passivation layer negative electrification Download PDFInfo
- Publication number
- CN113113511B CN113113511B CN202110388246.0A CN202110388246A CN113113511B CN 113113511 B CN113113511 B CN 113113511B CN 202110388246 A CN202110388246 A CN 202110388246A CN 113113511 B CN113113511 B CN 113113511B
- Authority
- CN
- China
- Prior art keywords
- mesa
- passivation layer
- infrared material
- mesa structure
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002161 passivation Methods 0.000 title claims abstract description 52
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 230000002401 inhibitory effect Effects 0.000 title claims abstract 5
- 239000000463 material Substances 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 238000001039 wet etching Methods 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 238000004151 rapid thermal annealing Methods 0.000 claims abstract description 7
- 230000008878 coupling Effects 0.000 claims abstract 2
- 238000010168 coupling process Methods 0.000 claims abstract 2
- 238000005859 coupling reaction Methods 0.000 claims abstract 2
- 230000001939 inductive effect Effects 0.000 claims abstract 2
- 239000010408 film Substances 0.000 claims description 29
- 238000005468 ion implantation Methods 0.000 claims description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- 238000009616 inductively coupled plasma Methods 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 11
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 10
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 239000008367 deionised water Substances 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000003486 chemical etching Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 239000000523 sample Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 41
- 238000010586 diagram Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000001629 suppression Effects 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000001659 ion-beam spectroscopy Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
- H10F71/129—Passivating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
- H10F30/10—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices being sensitive to infrared radiation, visible or ultraviolet radiation, and having no potential barriers, e.g. photoresistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/30—Coatings
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
技术领域technical field
本发明涉及半导体技术领域，尤其涉及一种利用钝化层负电化抑制侧壁漏电流的探测器的制备方法。The invention relates to the technical field of semiconductors, in particular to a preparation method of a detector for suppressing sidewall leakage current by using negative electrification of a passivation layer.
背景技术Background technique
探测器的侧壁漏电流是整个器件暗电流的组成部分，尤其是对于窄禁带器件，抑制台面侧壁漏电流成为提升器件阻抗性能的一种重要手段。目前，对于探测器台面侧壁表面漏电流的抑制主要通过降低表面态密度的方式来实现，实现方式有表面原子形成硫化物层，旋涂SU8、聚酰亚胺等特殊光刻胶的保护层，侧壁淀积电介质膜，侧壁宽禁带材料外延生长等。另外结合侧壁外加栅电极，在一定反向偏压下也能提升侧壁漏电流抑制效果。但是每一种工艺抑制表面漏电流的效果都是有限的，因此，开发一种可进一步提升侧壁表面漏电流的抑制效果的探测器是有意义的。The sidewall leakage current of the detector is an integral part of the dark current of the entire device, especially for narrow bandgap devices, suppressing the sidewall leakage current of the mesa has become an important means to improve the impedance performance of the device. At present, the suppression of the surface leakage current of the sidewall of the detector mesa is mainly achieved by reducing the surface density of states, which is achieved by forming a sulfide layer on the surface atoms, and spin-coating a protective layer of special photoresist such as SU8 and polyimide. , deposition of dielectric films on the sidewalls, epitaxial growth of wide-bandgap materials on the sidewalls, etc. In addition, combined with the addition of a gate electrode to the sidewall, the sidewall leakage current suppression effect can also be improved under a certain reverse bias voltage. However, the effect of suppressing the surface leakage current of each process is limited. Therefore, it is meaningful to develop a detector that can further improve the suppressing effect of the sidewall surface leakage current.
发明内容SUMMARY OF THE INVENTION
有鉴于此，为了进一步提升探测器的侧壁表面漏电流的抑制效果，本发明提供一种利用钝化层负电化抑制侧壁漏电流的探测器的制备方法。In view of this, in order to further improve the effect of suppressing the leakage current of the sidewall surface of the detector, the present invention provides a method for preparing a detector for suppressing the leakage current of the sidewall by using the negative electrification of the passivation layer.
本发明提供一种利用钝化层负电化抑制侧壁漏电流的探测器的制备方法，该制备方法包括：提供一红外材料，红外材料上形成有台面掩膜；采用电感耦合等离子体法刻蚀红外材料；采用干法刻蚀或湿法腐蚀去除台面掩膜，以形成带有台面结构的红外材料；在带有台面结构的红外材料上淀积电介质薄膜，以形成带有台面结构的钝化层；根据带有台面结构的钝化层的台面侧壁的厚度，对带有台面结构的钝化层进行元素掺杂；对带有台面结构的钝化层进行元素掺杂后，进行快速热退火处理，得到利用钝化层负电化抑制侧壁漏电流的探测器。The invention provides a method for preparing a detector for suppressing sidewall leakage current by using negative electrification of a passivation layer. The preparation method includes: providing an infrared material on which a mesa mask is formed; and etching by using an inductively coupled plasma method Infrared material; mesa mask is removed by dry etching or wet etching to form infrared material with mesa structure; dielectric film is deposited on infrared material with mesa structure to form passivation with mesa structure According to the thickness of the mesa sidewall of the passivation layer with the mesa structure, element doping is performed on the passivation layer with the mesa structure; after the passivation layer with the mesa structure is elementally doped, a rapid thermal After annealing treatment, a detector capable of suppressing sidewall leakage current by negative electrification of the passivation layer is obtained.
在一些实施例中，台面掩膜包括SiO2台面掩膜。In some embodiments, the mesa mask includes a SiO 2 mesa mask.
在一些实施例中，在采用电感耦合等离子体法刻蚀红外材料后，台面掩膜的剩余厚度为0～400nm。In some embodiments, after the infrared material is etched by the inductively coupled plasma method, the remaining thickness of the mesa mask is 0˜400 nm.
在一些实施例中，干法刻蚀包括电感耦合等离子体刻蚀、反应离子刻蚀；湿法腐蚀为氢氟酸、氟化铵和去离子水配制成的腐蚀液进行化学腐蚀。In some embodiments, the dry etching includes inductively coupled plasma etching and reactive ion etching; and the wet etching is chemical etching with an etching solution prepared from hydrofluoric acid, ammonium fluoride and deionized water.
在一些实施例中，带有台面结构的红外材料的台面侧壁与水平台面所成夹角θ在70°～80°之间。In some embodiments, the angle θ formed between the side wall of the mesa and the water platform of the infrared material with the mesa structure is between 70° and 80°.
在一些实施例中，电介质薄膜的厚度为500～1500nm。In some embodiments, the thickness of the dielectric film is 500-1500 nm.
在一些实施例中，电介质薄膜为SiO2或SixNy。In some embodiments, the dielectric film is SiO 2 or Six N y .
在一些实施例中，元素掺杂是掺杂能替代电介质薄膜中硅元素而形成受主杂质的元素。In some embodiments, the elemental doping is doping with an element capable of replacing silicon in the dielectric film to form acceptor impurities.
在一些实施例中，对带有台面结构的钝化层进行元素掺杂通过离子注入的方式实现，离子注入的注入剂量在5×1010～1014cm-2之间。In some embodiments, element doping is performed on the passivation layer with the mesa structure by means of ion implantation, and the implantation dose of the ion implantation is between 5×10 10 -10 14 cm -2 .
在一些实施例中，快速热退火的条件根据离子注入的注入剂量决定，退火温度小于等于400℃，退火时长小于等于100s。In some embodiments, the conditions of the rapid thermal annealing are determined according to the implantation dose of the ion implantation, the annealing temperature is less than or equal to 400° C., and the annealing time is less than or equal to 100s.
本发明提供一种利用上述的制备方法得到的探测器。The present invention provides a detector obtained by the above-mentioned preparation method.
本发明提供一种利用钝化层负电化抑制侧壁漏电流的探测器的制备方法，在探测器台面侧壁淀积电介质膜，形成钝化层。通过离子注入工艺实现对钝化层不同掺杂条件的掺杂。元素掺杂使淀积电介质膜而形成的钝化层自带负电中心而负电化，能够抑制表面态引起的负电中心所形成的漏电流，进一步可以提升侧壁表面漏电流的抑制效果，提高器件阻抗性能。The invention provides a preparation method of a detector which utilizes negative electrification of a passivation layer to suppress sidewall leakage current. A dielectric film is deposited on the sidewall of a detector mesa to form a passivation layer. Doping with different doping conditions of the passivation layer is realized by ion implantation. Element doping makes the passivation layer formed by depositing the dielectric film self-contained and negatively charged, which can suppress the leakage current formed by the negatively charged center caused by the surface state, which can further improve the suppression effect of the leakage current on the sidewall surface and improve the device. Impedance performance.
附图说明Description of drawings
图1为本发明实施例提供的利用钝化层负电化抑制侧壁漏电流的探测器的制备方法的流程图；FIG. 1 is a flow chart of a method for preparing a detector for suppressing sidewall leakage current by negatively electrifying a passivation layer provided by an embodiment of the present invention;
图2为本发明实施例提供的形成有台面掩膜的红外材料的结构示意图；2 is a schematic structural diagram of an infrared material formed with a mesa mask according to an embodiment of the present invention;
图3为本发明实施例提供的刻蚀红外材料后的结构示意图；3 is a schematic structural diagram of an infrared material after etching provided by an embodiment of the present invention;
图4为本发明实施例提供的去除台面掩膜后的红外材料的结构示意图；4 is a schematic structural diagram of the infrared material after removing the mesa mask according to an embodiment of the present invention;
图5为本发明实施例提供的淀积电介质薄膜形成钝化层后的结构示意图。FIG. 5 is a schematic structural diagram of a passivation layer formed by depositing a dielectric film according to an embodiment of the present invention.
【附图标记说明】[Description of reference numerals]
10-红外材料；20-台面掩膜；30-带有台面结构的红外材料；40-电介质薄膜；θ-台面结构的台面侧壁与水平台面所成夹角；301-上接触层；302-下接触层10-Infrared material; 20-Mesa mask; 30-Infrared material with mesa structure; 40-Dielectric film; θ-The angle formed by the mesa sidewall of the mesa structure and the water platform surface; 301-Upper contact layer; 302- lower contact layer
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
相关技术中，通过在探测器台面侧壁淀积电介质膜来抑制台面侧壁漏电流，但这种方法对台面侧壁漏电流的抑制效果是有限的。本发明提供一种利用钝化层负电化抑制侧壁漏电流的探测器的制备方法，通过元素掺杂的方式使淀积电介质膜而形成的钝化层自带负电中心而负电化，能够抑制表面态引起的负电中心所形成的漏电流，进一步可以提升侧壁表面漏电流的抑制效果。In the related art, the sidewall leakage current of the mesa is suppressed by depositing a dielectric film on the sidewall of the detector mesa, but the effect of suppressing the leakage current on the sidewall of the mesa is limited. The invention provides a method for preparing a detector for suppressing sidewall leakage current by utilizing negative electrification of a passivation layer. The passivation layer formed by depositing a dielectric film by means of element doping has its own negative electrification center and becomes negatively electrified, which can suppress The leakage current formed by the negative electric center caused by the surface state can further improve the suppression effect of the leakage current on the sidewall surface.
本发明提供一种利用钝化层负电化抑制侧壁漏电流的探测器的制备方法，该制备方法包括：提供一红外材料，红外材料上形成有台面掩膜；采用电感耦合等离子体法刻蚀红外材料；采用干法刻蚀或湿法腐蚀去除台面掩膜，以形成带有台面结构的红外材料；在带有台面结构的红外材料上淀积电介质薄膜，以形成带有台面结构的钝化层；根据带有台面结构的钝化层的台面侧壁的厚度，对带有台面结构的钝化层进行元素掺杂；对带有台面结构的钝化层进行元素掺杂后，进行快速热退火处理，得到利用钝化层负电化抑制侧壁漏电流的探测器。The invention provides a method for preparing a detector for suppressing sidewall leakage current by using negative electrification of a passivation layer. The preparation method includes: providing an infrared material on which a mesa mask is formed; and etching by using an inductively coupled plasma method Infrared material; mesa mask is removed by dry etching or wet etching to form infrared material with mesa structure; dielectric film is deposited on infrared material with mesa structure to form passivation with mesa structure According to the thickness of the mesa sidewall of the passivation layer with the mesa structure, element doping is performed on the passivation layer with the mesa structure; after the passivation layer with the mesa structure is elementally doped, a rapid thermal After annealing treatment, a detector capable of suppressing sidewall leakage current by negative electrification of the passivation layer is obtained.
图1为本发明实施例提供的利用钝化层负电化抑制侧壁漏电流的探测器的制备方法的流程图。如图1所示，该制备方法包括操作S101～S106。FIG. 1 is a flowchart of a method for fabricating a detector for suppressing sidewall leakage current by using negative electrification of a passivation layer according to an embodiment of the present invention. As shown in FIG. 1 , the preparation method includes operations S101 to S106.
图2为本发明实施例提供的形成有台面掩膜的红外材料的结构示意图。FIG. 2 is a schematic structural diagram of an infrared material formed with a mesa mask according to an embodiment of the present invention.
在操作S101，提供一红外材料，红外材料上形成有台面掩膜。In operation S101, an infrared material is provided on which a mesa mask is formed.
如图2所示，红外材料(10)上形成有台面掩膜(20)。As shown in Fig. 2, a mesa mask (20) is formed on the infrared material (10).
根据本发明的实施例，红外材料(10)可以为以下之一：短波红外材料、中波红外材料、长波红外材料、甚长波红外材料。According to an embodiment of the present invention, the infrared material (10) may be one of the following: a short-wave infrared material, a medium-wave infrared material, a long-wave infrared material, and a very long-wave infrared material.
根据本发明的实施例，台面掩膜(20)可以为SiO2台面掩膜。According to an embodiment of the present invention, the mesa mask (20) may be a SiO2 mesa mask.
图3为本发明实施例提供的刻蚀红外材料后的结构示意图。FIG. 3 is a schematic structural diagram of an infrared material after etching according to an embodiment of the present invention.
在操作S102，采用电感耦合等离子体法刻蚀红外材料，得到如图3所示的结构。In operation S102, the infrared material is etched by an inductively coupled plasma method to obtain the structure shown in FIG. 3 .
由图3可以看出，采用电感耦合等离子体法刻蚀红外材料后，形成带有台面结构的红外材料(30)，带有台面结构的红外材料(30)上有台面掩膜(20)。It can be seen from FIG. 3 that after the infrared material is etched by the inductively coupled plasma method, an infrared material (30) with a mesa structure is formed, and a mesa mask (20) is formed on the infrared material (30) with a mesa structure.
根据本发明的实施例，在采用电感耦合等离子体法刻蚀红外材料(10)后，台面掩膜(20)的剩余厚度为0～400nm。According to the embodiment of the present invention, after the infrared material (10) is etched by the inductively coupled plasma method, the remaining thickness of the mesa mask (20) is 0˜400 nm.
根据本发明的实施例，采用电感耦合等离子体法刻蚀红外材料(10)的刻蚀深度达到红外材料(10)的下接触层302。According to an embodiment of the present invention, the inductively coupled plasma method is used to etch the infrared material (10) to an etching depth that reaches the
图4为本发明实施例提供的去除台面掩膜后的红外材料的结构示意图。FIG. 4 is a schematic structural diagram of the infrared material after removing the mesa mask according to an embodiment of the present invention.
在操作S103，采用干法刻蚀或湿法腐蚀去除台面掩膜(20)，以形成带有台面结构的红外材料(30)。In operation S103, the mesa mask (20) is removed by dry etching or wet etching to form an infrared material (30) with a mesa structure.
如图4所示，形成带有凸台结构的红外材料(30)，台面结构的红外材料(30)的台面侧壁与水平台面所成夹角为θ。As shown in FIG. 4 , an infrared material (30) with a boss structure is formed, and the angle formed between the side wall of the mesa and the water platform surface of the infrared material (30) with a mesa structure is θ.
根据本发明的实施例，干法刻蚀包括电感耦合等离子体刻蚀、反应离子刻蚀。According to an embodiment of the present invention, dry etching includes inductively coupled plasma etching and reactive ion etching.
根据本发明的实施例，湿法腐蚀为氢氟酸、氟化铵和去离子水配制成的腐蚀液进行化学腐蚀。According to an embodiment of the present invention, the wet etching is chemical etching performed by an etching solution prepared from hydrofluoric acid, ammonium fluoride and deionized water.
根据本发明的实施例，湿法腐蚀的腐蚀液中，氢氟酸、氟化铵、去离子水的配比可以为1:4:5，其中，所用氢氟酸为分析纯(含量不少于40％)，氟化铵溶液MOS级(含量为40％±1％)。According to the embodiment of the present invention, in the etching solution of wet etching, the ratio of hydrofluoric acid, ammonium fluoride and deionized water can be 1:4:5, wherein, the hydrofluoric acid used is of analytical grade at 40%), ammonium fluoride solution MOS grade (content is 40%±1%).
根据本发明的实施例，带有台面结构的红外材料(30)的台面侧壁与水平台面所成夹角θ在70°～80°之间，例如，可以为70°、72°、75°、78°、80°。According to the embodiment of the present invention, the angle θ formed by the side wall of the infrared material (30) with the mesa structure and the water platform is between 70° and 80°, for example, it can be 70°, 72°, 75° , 78°, 80°.
图5为本发明实施例提供的淀积电介质薄膜形成钝化层后的结构示意图。在操作S104，在带有台面结构的红外材料(30)上淀积电介质薄膜(40)，以形成带有台面结构的钝化层。FIG. 5 is a schematic structural diagram of a passivation layer formed by depositing a dielectric film according to an embodiment of the present invention. In operation S104, a dielectric film (40) is deposited on the infrared material (30) with the mesa structure to form a passivation layer with the mesa structure.
如图5所示，在带有凸台结构的红外材料(30)的台面侧壁和水平台面上淀积电介质薄膜(40)。As shown in FIG. 5, a dielectric film (40) is deposited on the mesa sidewalls and the water mesa of the infrared material (30) with the boss structure.
根据本发明的实施例，电介质薄膜(40)的厚度可以为500～1500nm，例如，可以为500nm、700nm、1000nm、1200nm、1500nm。According to an embodiment of the present invention, the thickness of the dielectric thin film (40) may be 500-1500 nm, for example, may be 500 nm, 700 nm, 1000 nm, 1200 nm, 1500 nm.
根据本发明的实施例，电介质薄膜(40)可以为SiO2或SixNy。According to an embodiment of the present invention, the dielectric thin film (40) may be SiO 2 or Six N y .
根据本发明的实施例，在带有台面结构的红外材料(30)上淀积电介质薄膜(40)的淀积方式可以为以下之一：离子体增强化学的气相沉积法、离子束溅射、电子束蒸发。According to an embodiment of the present invention, the deposition method for depositing the dielectric film (40) on the infrared material (30) with the mesa structure may be one of the following: plasma enhanced chemical vapor deposition, ion beam sputtering, E-beam evaporation.
在操作S105，根据带有台面结构的钝化层的台面侧壁的厚度，对带有台面结构的钝化层进行元素掺杂。In operation S105, element doping is performed on the passivation layer with the mesa structure according to the thickness of the sidewall of the mesa of the passivation layer with the mesa structure.
根据本发明的实施例，台面侧壁上电介质薄膜(40)的厚度通过取样后在扫描电子显微镜下测定。According to an embodiment of the present invention, the thickness of the dielectric film (40) on the sidewalls of the mesa is measured under a scanning electron microscope after sampling.
根据本发明的实施例，元素掺杂是掺杂能替代电介质薄膜(40)中硅元素而形成受主杂质的元素，例如，可以为硼元素、铝元素、镓元素、铟元素。According to an embodiment of the present invention, element doping is doping an element that can replace silicon element in the dielectric film (40) to form an acceptor impurity, such as boron element, aluminum element, gallium element, and indium element.
根据本发明的实施例，对带有台面结构的钝化层进行元素掺杂通过离子注入的方式实现。According to an embodiment of the present invention, the element doping of the passivation layer with the mesa structure is implemented by means of ion implantation.
根据本发明的实施例，离子注入的注入剂量在5×1010～1014cm-2之间，例如，可以为5×1010cm-2、1011cm-2、1012cm-2、1013cm-2、1014cm-2。According to an embodiment of the present invention, the implantation dose of ion implantation is between 5×10 10 -10 14 cm -2 , for example, 5×10 10 cm -2 , 10 11 cm -2 , 10 12 cm -2 , 10 13 cm -2 , 10 14 cm -2 .
根据本发明的实施例，电介质薄膜(40)的淀积厚度d由目标掺杂条件下离子注入参数投影射程Rp和射程标准偏差ΔRp决定，d＝Rp+4.3ΔRp。According to the embodiment of the present invention, the deposition thickness d of the dielectric film (40) is determined by the projected range Rp and the range standard deviation ΔRp of the ion implantation parameters under the target doping condition, d = Rp + 4.3ΔRp .
在操作S106，对带有台面结构的钝化层进行元素掺杂后，进行快速热退火处理，得到利用钝化层负电化抑制侧壁漏电流的探测器。In operation S106 , after element doping is performed on the passivation layer with the mesa structure, rapid thermal annealing is performed to obtain a detector that utilizes negative electrification of the passivation layer to suppress sidewall leakage current.
根据本发明的实施例，快速热退火的条件根据离子注入的注入剂量决定，退火温度小于等于400℃，例如，可以为200℃、250℃、300℃、350℃、400℃；退火时长小于等于100s，例如，可以为40s、60s、80s、90s、100s。According to an embodiment of the present invention, the conditions of the rapid thermal annealing are determined according to the implantation dose of the ion implantation, and the annealing temperature is less than or equal to 400°C, for example, 200°C, 250°C, 300°C, 350°C, 400°C; the annealing time is less than or equal to 100s, for example, can be 40s, 60s, 80s, 90s, 100s.
本发明提供一种利用上述制备方法得到的探测器。The present invention provides a detector obtained by the above preparation method.
为了更清楚地阐述本发明的实施特点，将结合一种利用钝化层负电化抑制侧壁漏电流的探测器的制备方法的实施例对本发明作进一步说明。In order to illustrate the implementation features of the present invention more clearly, the present invention will be further described with reference to an embodiment of a method for fabricating a detector for suppressing sidewall leakage current by using negative electrification of a passivation layer.
实施例1Example 1
取一形成有SiO2台面掩膜(20)图形的红外材料(10)，采用电感耦合等离子体法刻蚀红外材料(10)，刻蚀深度达到红外材料的下接触层。取用比例为1:4:5的氢氟酸、氟化铵和去离子水，配置成BOE腐蚀溶液。采用BOE腐蚀溶液去除残余SiO2台面掩膜(20)，形成带有台面结构的红外材料(30)。通过等离子体增强化学的气相沉积法在带有台面结构的红外材料(30)上淀积电介质薄膜(40)，其中，电介质薄膜(40)为SiO2。对淀积得到的电介质薄膜(40)取样，并通过扫描电子显微镜测定台面侧壁上电介质薄膜(40)的厚度为600nm。淀积电介质薄膜(40)后，通过离子注入进行元素掺杂。根据测量得到的台面侧壁上电介质薄膜(40)的厚度，确定离子注入的注入剂量为5×1010cm-2，掺杂能量为120KeV。对带有台面结构的钝化层进行元素掺杂后，进行快速热退火处理，退火温度为400℃，退火时长为90s。退火结束后，可得到利用钝化层负电化抑制侧壁漏电流的探测器。An infrared material (10) formed with a SiO2 mesa mask (20) pattern is taken, and the infrared material (10) is etched by an inductively coupled plasma method, and the etching depth reaches the lower contact layer of the infrared material. Take hydrofluoric acid, ammonium fluoride and deionized water in a ratio of 1:4:5 to configure a BOE etching solution. The residual SiO2 mesa mask (20) is removed by using a BOE etching solution to form an infrared material (30) with a mesa structure. A dielectric film (40) is deposited on the infrared material (30) with a mesa structure by a plasma-enhanced chemical vapor deposition method, wherein the dielectric film (40) is SiO 2 . The deposited dielectric film (40) was sampled, and the thickness of the dielectric film (40) on the sidewall of the mesa was determined to be 600 nm by scanning electron microscopy. After deposition of the dielectric film (40), element doping is performed by ion implantation. According to the measured thickness of the dielectric film (40) on the sidewall of the mesa, the implantation dose of ion implantation is determined to be 5×10 10 cm -2 , and the doping energy is 120 KeV. After the passivation layer with the mesa structure is doped with elements, rapid thermal annealing is performed, the annealing temperature is 400 °C, and the annealing time is 90 s. After the annealing, a detector capable of suppressing sidewall leakage current by the negative electrification of the passivation layer can be obtained.
本发明的实施例提供一种利用钝化层负电化抑制侧壁漏电流的探测器的制备方法，在探测器台面侧壁淀积电介质膜，形成钝化层。通过离子注入工艺实现对钝化层不同掺杂条件的掺杂。元素掺杂使淀积电介质膜而形成的钝化层自带负电中心而负电化，能够抑制表面态引起的负电中心所形成的漏电流，进一步可以提升侧壁表面漏电流的抑制效果，提高器件阻抗性能。An embodiment of the present invention provides a method for preparing a detector for suppressing sidewall leakage current by using negative electrification of a passivation layer. A dielectric film is deposited on the sidewall of a detector mesa to form a passivation layer. Doping with different doping conditions of the passivation layer is realized by ion implantation. Element doping makes the passivation layer formed by depositing the dielectric film self-contained and negatively charged, which can suppress the leakage current formed by the negatively charged center caused by the surface state, which can further improve the suppression effect of the leakage current on the sidewall surface and improve the device. Impedance performance.
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above-mentioned specific embodiments are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principle of the present invention, any modifications, equivalent replacements, improvements, etc. made should be included within the protection scope of the present invention.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110388246.0A CN113113511B (en) | 2021-04-12 | 2021-04-12 | Preparation method of detector for inhibiting side wall leakage current by using passivation layer negative electrification |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110388246.0A CN113113511B (en) | 2021-04-12 | 2021-04-12 | Preparation method of detector for inhibiting side wall leakage current by using passivation layer negative electrification |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113113511A CN113113511A (en) | 2021-07-13 |
| CN113113511B true CN113113511B (en) | 2022-07-26 |
Family
ID=76715907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110388246.0A Active CN113113511B (en) | 2021-04-12 | 2021-04-12 | Preparation method of detector for inhibiting side wall leakage current by using passivation layer negative electrification |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113113511B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821585A (en) * | 1993-09-29 | 1998-10-13 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor and manufacturing method thereof |
| CN109285913A (en) * | 2018-11-14 | 2019-01-29 | 中国电子科技集团公司第四十四研究所 | Low surface leakage current mesa-type photodetector and method of making the same |
| CN110176507A (en) * | 2019-05-31 | 2019-08-27 | 厦门市三安集成电路有限公司 | Passivating structure and photodiode of a kind of table top PIN and preparation method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4755854B2 (en) * | 2005-06-02 | 2011-08-24 | 富士通株式会社 | Semiconductor light receiving device and manufacturing method thereof |
| US8178863B2 (en) * | 2009-06-01 | 2012-05-15 | Teledyne Scientific & Imaging, Llc | Lateral collection architecture for SLS detectors |
| IL238368B (en) * | 2015-04-19 | 2019-08-29 | Semi Conductor Devices An Elbit Systems Rafael Partnership | Photo-detector device |
| JP7283148B2 (en) * | 2019-03-14 | 2023-05-30 | 富士通株式会社 | Infrared detector, imaging device using the same, and method for manufacturing infrared detector |
-
2021
- 2021-04-12 CN CN202110388246.0A patent/CN113113511B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821585A (en) * | 1993-09-29 | 1998-10-13 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor and manufacturing method thereof |
| CN109285913A (en) * | 2018-11-14 | 2019-01-29 | 中国电子科技集团公司第四十四研究所 | Low surface leakage current mesa-type photodetector and method of making the same |
| CN110176507A (en) * | 2019-05-31 | 2019-08-27 | 厦门市三安集成电路有限公司 | Passivating structure and photodiode of a kind of table top PIN and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113113511A (en) | 2021-07-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11257935B2 (en) | Gan rectifier suitable for operating under 35GHZ alternating-current frequency, and preparation method therefor | |
| CN104993009B (en) | Counter doping stops impurity band terahertz detector chip and preparation method thereof | |
| CN111863807B (en) | Single-chip heterogeneous integrated Casode structure field effect transistor based on source field plate and manufacturing method | |
| CN204243084U (en) | Hall Bar Micro Devices | |
| TW201438110A (en) | Method for adjusting threshold voltage of low temperature polycrystalline germanium transistor | |
| CN104282764B (en) | 4H SiC metal-semiconductor field effect transistors and preparation method with domatic grid | |
| CN106920847A (en) | A kind of top-gated graphene field effect transistor and preparation method thereof | |
| Courtin et al. | A low Schottky barrier height and transport mechanism in gold–graphene–silicon (001) heterojunctions | |
| CN113113511B (en) | Preparation method of detector for inhibiting side wall leakage current by using passivation layer negative electrification | |
| CN104576832B (en) | Blocking impurity band detector manufacturing method based on SOI | |
| CN110504297B (en) | Two-dimensional material transistor, fabrication method and application based on two-dimensional electron gas control back gate | |
| CN113035781B (en) | Wafer-level two-dimensional material transfer method and device preparation method | |
| CN104681618B (en) | A kind of 4H SiC metal-semiconductor field effect transistors with dual recess cushion | |
| CN105225952B (en) | The production method and VDMOS device of a kind of VDMOS device | |
| CN112466930B (en) | A metal contact structure of a two-dimensional semiconductor material and a preparation method thereof | |
| CN111463273A (en) | Long-off HEMT device based on gallium nitride heterojunction epitaxy and preparation method thereof | |
| CN103187249B (en) | A kind of preparation method of semiconductor nano material device | |
| CN102751179B (en) | A kind of method preparing graphene device | |
| CN109285941B (en) | Induction type superconducting edge detector and preparation method thereof | |
| CN213782022U (en) | A metal contact structure of a two-dimensional semiconductor material | |
| CN104900701B (en) | Silicon carbide UMOSFET devices and production method with two-region floating junction | |
| CN105845616A (en) | Manufacturing method for wafer level uniaxial strain GeOI based on silicon nitride stress membrane and scale effect | |
| CN105161531A (en) | 4h-sic metal semiconductor field effect transistor and manufacturing method thereof | |
| CN107706242B (en) | Transistor and method of making the same | |
| CN110085673B (en) | Impurity atom array transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |