CN113113070B - Shifting register, grid driving circuit and display device - Google Patents
Shifting register, grid driving circuit and display device Download PDFInfo
- Publication number
- CN113113070B CN113113070B CN202110390685.5A CN202110390685A CN113113070B CN 113113070 B CN113113070 B CN 113113070B CN 202110390685 A CN202110390685 A CN 202110390685A CN 113113070 B CN113113070 B CN 113113070B
- Authority
- CN
- China
- Prior art keywords
- node
- pull
- circuit
- potential
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000004044 response Effects 0.000 claims description 28
- 230000009467 reduction Effects 0.000 claims description 16
- 238000001514 detection method Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 230000002159 abnormal effect Effects 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 230000002238 attenuated effect Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a shift register, a grid driving circuit and a display device, and relates to the technical field of display. The shift register includes: an input circuit including a first transistor connected in series; a reset circuit including a second transistor connected in series; the pull-up circuit is connected with a first node between the first transistors, a pull-down node, a first power supply end, a second node between the second transistors and a reset signal end and is used for responding to the potential of the pull-down node and a first power supply signal, controlling the potential of the first node and responding to a reset signal of the reset signal end and controlling the potential of the second node; a pull-down circuit; and an output circuit. In the invention, when the pull-up node is at a high level, the pull-up circuit can control the first node and the second node to be at the high level, so that the electric leakage of the pull-up node through the input and reset circuits is avoided. In addition, by connecting two transistors in series in the input and reset circuits, the leakage of the pull-up node through the input and reset circuits can be reduced when the pull-up node is at a high level.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit, and a display device.
Background
Currently, there are two Touch operation modes of Touch and Display Driver Integration (TDDI) products, in which one mode is to insert Touch detection within a frame time of display, so in a shift register of a gate driving circuit, when the shift register is in a display driving stage, a high potential state of a pull-up node is maintained relatively short, when the shift register is in a Touch detection stage, the shift register can stop operation, and the pull-up node is kept in a high potential state throughout the Touch detection stage until Touch detection is completed, at this time, the pull-up node is always in a floating (floating) state. The output end of the shift register realizes grid drive output through the high level of the pull-up node, but in a long-time floating state, the pull-up node leaks electricity through the input circuit and the reset circuit in the touch detection stage, so that output signals of the shift register in the first rows after the touch detection stage are attenuated, abnormal grid drive is caused, and the display device has transverse stripes.
Disclosure of Invention
The invention provides a shift register, a grid driving circuit and a display device, which are used for solving the problems that a pull-up node in the existing shift register leaks electricity through an input circuit and a reset circuit in a touch detection stage, so that an output signal of the shift register is attenuated after the touch detection stage, the grid driving is abnormal, and a transverse stripe occurs in the display device.
In order to solve the above problems, the present invention discloses a shift register comprising:
The input circuit is respectively connected with an input end and a pull-up node, and comprises two first transistors connected in series, and the input circuit is used for responding to an input signal of the input end and controlling the potential of the pull-up node;
The reset circuit is respectively connected with a reset signal end, the pull-up node and a first power end, and comprises two second transistors connected in series, and is used for responding to the reset signal of the reset signal end and inputting the first power signal of the first power end to the pull-up node;
A pull-up circuit connected to a first node between the first transistors, a pull-down node, the first power supply terminal, a second node between the second transistors, and a reset signal terminal, respectively, the pull-up circuit being configured to control a potential of the first node in response to a potential of the pull-down node and the first power supply signal, and to control a potential of the second node in response to a reset signal of the reset signal terminal;
A pull-down circuit connected to the pull-up node, the pull-down node, and an output terminal, respectively, the pull-down circuit being configured to control a potential of the pull-down node based on a potential of the pull-up node, and pull down the potential of the output terminal in response to the potential of the pull-down node;
And the output circuit is respectively connected with the clock signal end, the pull-up node and the output end and is used for responding to the potential of the pull-up node and outputting the clock signal of the clock signal end to the output end.
Optionally, the shift register further includes:
the noise reduction circuit is respectively connected with the pull-down node, the pull-up node and the first power supply end, and comprises two third transistors connected in series, and the noise reduction circuit is used for responding to the potential of the pull-down node and inputting the first power supply signal to the pull-up node;
The pull-up circuit is also connected with a third node between the third transistors, and is further used for responding to the reset signal of the reset signal end to control the potential of the third node.
Optionally, the pull-up circuit includes:
a fourth transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the first node, and a second pole of which is connected to the first power supply terminal, the fourth transistor being configured to control a potential of the first node in response to a potential of the pull-down node and a first power supply signal of the first power supply terminal;
And a fifth transistor, wherein a gate and a first pole of the fifth transistor are connected with the reset signal terminal, a second pole of the fifth transistor is connected with the second node, and the fifth transistor is used for responding to a reset signal of the reset signal terminal and controlling the potential of the second node.
Optionally, the second pole of the fifth transistor is further connected to the third node, and the fifth transistor is further configured to control the potential of the third node in response to the reset signal of the reset signal terminal.
Optionally, in the two third transistors connected in series, a first pole of the first third transistor is connected to the pull-up node, a gate is connected to the pull-down node, and a second pole is connected to the third node;
In the two third transistors connected in series, a first pole of a second third transistor is connected with the third node, a gate is connected with the pull-down node, and a second pole is connected with the first power supply terminal.
Optionally, in the two first transistors connected in series, a gate and a first pole of the first transistor are connected to the input terminal, and a second pole is connected to the first node;
In the two first transistors connected in series, a first pole of a second first transistor is connected with the first node, a gate is connected with the input terminal, and a second pole is connected with the pull-up node.
Optionally, in the two second transistors connected in series, a first pole of a first one of the second transistors is connected to the pull-up node, a gate is connected to the reset signal terminal, and a second pole is connected to the second node;
and in the two second transistors connected in series, a first pole of a second transistor is connected with the second node, a grid electrode is connected with the reset signal end, and a second pole is connected with the first power supply end.
Optionally, the output terminal includes a first output terminal and a second output terminal, and the output circuit includes:
The first output sub-circuit is respectively connected with a clock signal end, the pull-up node and the first output end, and is used for responding to the potential of the pull-up node and outputting a clock signal of the clock signal end to the first output end as a grid driving signal of a row where the shift register is located;
and the second output sub-circuit is respectively connected with the clock signal end, the pull-up node and the second output end, and is used for responding to the potential of the pull-up node and outputting the clock signal of the clock signal end to the second output end as a reset signal of the next row of the row where the shift register is located.
Optionally, the pull-down circuit is further connected to the first power supply terminal, and the pull-down circuit includes:
The first pull-down subcircuit is respectively connected with the pull-down node, the first power supply end and the first output end, and is used for responding to the potential of the pull-down node and pulling down the potential of the first output end through a first power supply signal of the first power supply end;
and the second pull-down sub-circuit is respectively connected with the pull-down node, the first power supply end and the second output end, and is used for responding to the potential of the pull-down node and pulling down the potential of the second output end through the first power supply signal of the first power supply end.
Optionally, the pull-down circuit is further connected to the first power supply terminal and the second power supply terminal, respectively, and the pull-down circuit includes:
The third pull-down sub-circuit is respectively connected with the second power supply end, the pull-up node, the pull-down node and the first power supply end, and is used for responding to the potential of the pull-up node, inputting a second power supply signal of the second power supply end to the pull-down node and responding to the potential of the pull-up node, and inputting the first power supply signal of the first power supply end to the pull-down node.
Optionally, the shift register further includes:
The frame reset circuit is respectively connected with the frame reset signal end, the first power end, the pull-up node and the output end; the frame reset circuit is used for responding to the frame reset signal of the frame reset signal end and respectively carrying out frame reset on the pull-up node and the output end through the first power signal of the first power end.
In order to solve the above problems, the present invention also discloses a gate driving circuit, which includes a plurality of cascaded shift registers, wherein the shift registers include the shift registers.
In order to solve the above problems, the invention also discloses a display device comprising the gate driving circuit.
Compared with the prior art, the invention has the following advantages:
in the embodiment of the invention, the pull-up circuit is connected with the first node between the first transistors, when the pull-up node is at a high level, the pull-down node is at a low level, and at the moment, the pull-up circuit can control the first node to keep at the high level. The pull-up circuit is also connected with a second node between the second transistors, and can pull up and hold the potential of the second node when the reset signal of the reset signal end is at a high level, so that the pull-up circuit can control the second node to keep at the high level when the pull-up node is at the high level later. Because the pull-up circuit can control the first node of the input circuit and the second node of the reset circuit to be at the high level when the pull-up node is at the high level, the leakage of the pull-up node through the input circuit and the reset circuit is avoided. In addition, by connecting two transistors in series in the input circuit and providing two transistors in series in the reset circuit, when the pull-up node is at a high level, leakage of the pull-up node through the input circuit and the reset circuit can be further reduced.
Drawings
FIG. 1 is a schematic diagram showing a conventional shift register;
FIG. 2 is a schematic diagram showing the potential of a pull-up node of a conventional display driving stage;
FIG. 3 is a schematic diagram showing the potential of a pull-up node in a conventional touch detection stage;
fig. 4 shows a schematic structural diagram of a shift register according to a first embodiment of the present invention;
Fig. 5 shows a specific structure of a shift register according to a first embodiment of the present invention;
fig. 6 shows a signal-side timing diagram of a shift register according to a first embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Before describing embodiments of the present invention in detail, an existing shift register will be described.
Fig. 1 shows a schematic diagram of a conventional shift register, and referring to fig. 1, the shift register includes an input circuit 10, a reset circuit 20, a pull-down circuit 40, an output circuit 50, a noise reduction circuit 60, and a frame reset circuit 70, wherein the input circuit 10 includes a transistor M1, and the reset circuit 20 includes a transistor M2.
In practical application, the potential of the pull-up node PU will leak through the transistors M1 and M2, referring to fig. 2, when in the display driving stage, the high state of the pull-up node PU is maintained for a short time t1, and the leakage time is short, so that the output is not affected; however, referring to fig. 3, when the Touch detection stage (Touch pit) is performed, the high level state of the pull-up node PU is maintained for a longer time t2, and in the case of floating for a long time, the pull-up node PU leaks electricity through the transistor M1 and the transistor M2, so that the potential of the pull-up node PU decreases, that is, the difference between the voltage V1 outside the pit and the voltage V2 behind the pit of the pull-up node PU is large, so that when the display driving is started after the Touch detection stage, the signals output by the output terminals Out of the first rows behind the pit are attenuated, resulting in abnormal gate driving, and the display device has a cross-stripe problem.
In summary, for the existing shift register, the gate driving circuit and the display device in the embodiment of the invention are provided, so as to solve the problems that the pull-up node in the existing shift register leaks electricity through the input circuit and the reset circuit in the touch detection stage, so that the output signal of the shift register is attenuated, the gate driving is abnormal and the display device has cross stripes after the touch detection stage.
Example 1
Fig. 4 is a schematic diagram of a shift register according to a first embodiment of the present invention, and referring to fig. 4, the shift register includes an input circuit 10, a reset circuit 20, a pull-up circuit 30, a pull-down circuit 40, and an output circuit 50.
The Input circuit 10 is respectively connected with an Input end Input and a pull-up node PU, the Input circuit 10 comprises two first transistors M1A and M1B connected in series, and the Input circuit 10 is used for responding to an Input signal of the Input end Input and controlling the potential of the pull-up node PU;
The Reset circuit 20 is respectively connected with a Reset signal end Reset, a pull-up node PU and a first power supply end VGL, the Reset circuit 20 comprises two second transistors M2A and M2B connected in series, and the Reset circuit 20 is used for responding to the Reset signal of the Reset signal end Reset and inputting the first power supply signal of the first power supply end VGL to the pull-up node PU;
The pull-up circuit 30 is connected to a first node Q between the first transistors M1A and M1B, a pull-down node PD, a first power supply terminal VGL, a second node N between the second transistors M2A and M2B, and a reset signal terminal Cout N-1, respectively, the pull-up circuit 30 being configured to control the potential of the first node Q in response to the potential of the pull-down node PD and the first power supply signal, and to control the potential of the second node N in response to the reset signal of the reset signal terminal Cout N-1;
The pull-down circuit 40 is respectively connected with the pull-up node PU, the pull-down node PD and the output terminal Out, and the pull-down circuit 40 is used for controlling the potential of the pull-down node PD based on the potential of the pull-up node PU and pulling down the potential of the output terminal Out in response to the potential of the pull-down node PD;
the output circuit 50 is connected to the clock signal terminal CLK, the pull-up node PU and the output terminal Out, respectively, and the output circuit 50 is configured to output the clock signal of the clock signal terminal CLK to the output terminal Out in response to the potential of the pull-up node PU.
In the embodiment of the present invention, first, the pull-up circuit 30 is connected to the first node Q between the first transistors M1A and M1B, and when the pull-up node PU is at the high level, the pull-down node PD is at the low level, and at this time, the pull-up circuit 30 may control the first node Q to maintain the high level. The pull-up circuit 30 is further connected to the second node N between the second transistors M2A and M2B, and when the reset signal of the reset signal terminal Cout N-1 is at a high level, the potential of the second node N may be pulled up and maintained, so that the pull-up circuit 30 may control the second node N to maintain a high level when the pull-up node PU is at a high level later. Since the pull-up circuit 30 can control the first node Q of the input circuit 10 and the second node N of the reset circuit 20 to be at a high level when the pull-up node PU is at a high level, the leakage of the pull-up node PU through the input circuit 10 and the reset circuit 20 is avoided.
Next, by connecting two first transistors M1A and M1B in series in the input circuit 10, it is possible to further avoid leakage of the pull-up node PU through the input circuit 10 when the pull-up node PU is at a high level.
Further, by connecting two second transistors M2A and M2B in series in the reset circuit 20, it is possible to further avoid leakage of the pull-up node PU through the reset circuit 20 when the pull-up node PU is at a high level.
In the embodiment of the invention, the pull-up node PU is prevented from leaking electricity through the input circuit 10 and the reset circuit 20, so that the grid driving circuit can be ensured to normally output the grid driving signal, the stability of the grid driving circuit is improved, the phenomenon of product transverse lines caused by abnormal output of the grid driving circuit is avoided, the yield loss is reduced, and the reliability of products is improved.
Further, referring to fig. 1, the noise reduction circuit 60 of the conventional shift register includes a transistor M9, and in practical applications, the pull-up node PU is still leaked through the transistor M9 when floating for a long time.
Accordingly, fig. 5 shows a schematic diagram of a specific structure of a shift register according to the first embodiment of the present invention, and referring to fig. 5, optionally, the shift register further includes:
The noise reduction circuit 60 is connected to the pull-down node PD, the pull-up node PU and the first power supply terminal VGL, respectively, the noise reduction circuit 60 includes two third transistors M9A and M9B connected in series, and the noise reduction circuit 60 is configured to input the first power supply signal to the pull-up node PU in response to the potential of the pull-down node PD.
Accordingly, the pull-up circuit 30 is further connected to the third node P between the third transistors M9A and M9B, and the pull-up circuit 30 is further configured to control the potential of the third node P in response to the reset signal at the reset signal terminal Cout N-1.
In the embodiment of the present invention, the pull-up circuit 30 is further connected to the third node P between the third transistors M9A and M9B, and when the reset signal of the reset signal terminal Cout N-1 is at a high level, the potential of the third node P can be pulled up and maintained, so that the pull-up circuit 30 can control the third node P to maintain a high level when the pull-up node PU is at a high level later, thereby avoiding the power leakage of the pull-up node PU through the noise reduction circuit 60.
Further, by connecting the two third transistors M9A and M9B in series in the noise reduction circuit 60, it is possible to further avoid leakage of the pull-up node PU through the noise reduction circuit 60 when the pull-up node PU is at a high level.
Alternatively, referring to fig. 5, the pull-up circuit 30 may specifically include:
the gate of the fourth transistor MT1 is connected to the pull-down node PD, the first pole of the fourth transistor MT1 is connected to the first node Q, the second pole of the fourth transistor MT1 is connected to the first power supply terminal VGL, and the fourth transistor MT1 is configured to control the potential of the first node Q in response to the potential of the pull-down node PD and the first power supply signal of the first power supply terminal VGL.
The gate and the first pole of the fifth transistor MT2 are connected to the reset signal terminal Cout N-1, the second pole of the fifth transistor MT2 is connected to the second node N, and the fifth transistor MT2 is configured to control the potential of the second node N in response to the reset signal of the reset signal terminal Cout N-1.
The potential of the first node Q is pulled high when the Input signal of the Input terminal Input is at a high level, and the potential of the pull-up node PU is also pulled high at the same time, at this time, the pull-down node PD is at a low level, the fourth transistor MT1 is turned off, and the potential of the first node Q remains at a high level. When the reset signal of the reset signal terminal Cout N-1 is at a high level, the fifth transistor MT2 is turned on, and the potential of the second node N is pulled up.
In a specific application, the Input signal of the Input terminal Input and the reset signal of the reset signal terminal Cout N-1 are both output signals of the shift register of the previous stage, so that the timing sequences of the Input signal and the reset signal are the same, and when the Input signal is at a high level, the reset signal is also at a high level, so that the potential of the first node Q and the potential of the second node N are simultaneously pulled up under the condition that the pull-up node PU is at a high level, and the leakage of the pull-up node PU through the Input circuit 10 and the reset circuit 20 is avoided.
Optionally, referring to fig. 5, the second pole of the fifth transistor MT2 is further connected to the third node P, and the fifth transistor MT2 is further configured to control the potential of the third node P in response to the reset signal of the reset signal terminal Cout N-1.
Since the second pole of the fifth transistor MT2 is further connected to the third node P, when the reset signal of the reset signal terminal Cout N-1 is at a high level, the fifth transistor MT2 is turned on, and the potential of the third node P is pulled high, so that the power leakage of the pull-up node PU through the noise reduction circuit 60 is avoided.
As a further alternative to the noise reduction circuit 60, referring to fig. 5, of the two third transistors M9A and M9B connected in series, a first pole of the first third transistor M9A is connected to the pull-up node PU, a gate is connected to the pull-down node PD, and a second pole is connected to the third node P; of the two third transistors M9A and M9B connected in series, the first pole of the second third transistor M9B is connected to the third node P, the gate is connected to the pull-down node PD, and the second pole is connected to the first power supply terminal VGL.
As a further alternative to the Input circuit 10, of the two first transistors M1A and M1B in series, the gate and the first pole of the first transistor M1A are connected to the Input terminal Input, and the second pole is connected to the first node Q; of the two first transistors M1A and M1B connected in series, the first pole of the second first transistor M1B is connected to the first node Q, the gate is connected to the Input terminal Input, and the second pole is connected to the pull-up node PU.
As a further alternative to the Reset circuit 20, of the two second transistors M2A and M2B connected in series, a first pole of the first second transistor M2A is connected to the pull-up node PU, a gate is connected to the Reset signal terminal Reset, and a second pole is connected to the second node N; of the two second transistors M2A and M2B connected in series, the first pole of the second transistor M2B is connected to the second node N, the gate is connected to the Reset signal terminal Reset, and the second pole is connected to the first power supply terminal VGL.
Still alternatively, referring to fig. 5, the output terminal Out includes a first output terminal Gn and a second output terminal Cout N, and the output circuit 50 includes:
The first output sub-circuit 501 is respectively connected with the clock signal terminal CLK, the pull-up node PU and the first output terminal Gn, and the first output sub-circuit 501 is configured to output the clock signal of the clock signal terminal CLK to the first output terminal Gn as a gate driving signal where the shift register is located in response to the potential of the pull-up node PU;
The second output sub-circuit 502 is connected to the clock signal terminal CLK, the pull-up node PU and the second output terminal Cout N, respectively, and the second output sub-circuit 502 is configured to output the clock signal of the clock signal terminal CLK to the second output terminal Cout N as a reset signal of a next row of the shift register in response to the potential of the pull-up node PU.
Specifically, referring to fig. 5, the first output sub-circuit 501 may include a sixth transistor M8A, and the second output sub-circuit 502 may include a seventh transistor M8B. When the sixth transistor M8A is turned on, the clock signal of the clock signal terminal CLK can be output to the first output terminal Gn, and then the clock signal is input to the gate of the row where the shift register is located, so as to perform gate driving. When the seventh transistor M8B is turned on, the clock signal of the clock signal terminal CLK can be outputted to the second output terminal Cout N, and then the clock signal is inputted to the reset signal terminal Cout N-1 of the next row of the shift register, so as to control the pull-up circuit 30 of the next stage of the shift register.
In the embodiment of the present invention, the output signal of the first output terminal Gn of the previous stage shift register may be Input to the Input terminal Input of the next stage shift register as the Input signal of the next stage shift register, and the output signal of the second output terminal Cout N of the previous stage shift register may be Input to the reset signal terminal Cout N-1 of the next stage shift register as the reset signal of the next stage shift register.
Still alternatively, the pull-down circuit 40 is further connected to the first power supply terminal VGL, and the pull-down circuit includes:
a first pull-down sub-circuit 401 connected to the pull-down node PD, the first power supply terminal VGL, and the first output terminal Gn, respectively, the first pull-down sub-circuit 401 being configured to pull down the potential of the first output terminal Gn by a first power supply signal of the first power supply terminal VGL in response to the potential of the pull-down node PD;
The second pull-down sub-circuit 402 is connected to the pull-down node PD, the first power supply terminal VGL, and the second output terminal Cout N, respectively, and the second pull-down sub-circuit 402 is configured to pull down the potential of the second output terminal Cout N through the first power supply signal of the first power supply terminal VGL in response to the potential of the pull-down node PD.
Specifically, referring to fig. 5, the first pull-down sub-circuit 401 may include an eighth transistor M3A, and the second pull-down sub-circuit 402 may include a ninth transistor M3B. When the eighth transistor M3A is turned on, the first power signal may be input to the first output terminal Gn, so that the potential of the first output terminal Gn may be pulled down to complete the reset of the first output terminal Gn. When the ninth transistor M3B is turned on, the first power signal may be input to the second output terminal Cout N, so that the potential of the second output terminal Cout N may be pulled down to complete the reset of the second output terminal Cout N.
In the embodiment of the present invention, since the reset signal is used to control the pull-up circuit 30 of the shift register of this stage, if two paths of outputs are further divided after the output end, one path of outputs is output to the gate of this row, the other path of outputs is output to the reset signal end of the next row, when the fifth transistor MT2 of the shift register of this stage is controlled by the reset signal, the output signal of this stage is affected by the output signal of this stage to the gate of this row, therefore, before the output end, the output circuit 50 may be divided into the first output sub-circuit 501 and the second output sub-circuit 502, and correspondingly, the output end may be also divided into the first output end Gn and the second output end Cout N, and accordingly, the clock signal may be divided into two paths, one path of outputs to the gate of this row through the first output end Gn, and the other path of outputs to the reset signal end of the next stage shift register through the second output end Cout N, so that the influence of the fifth transistor MT2 of the shift register of this stage on the line gate signal is avoided.
Further alternatively, the pull-down circuit 40 is further connected to the first power supply terminal VGL and the second power supply terminal VGH, respectively, and the pull-down circuit 40 includes:
The third pull-down sub-circuit 403 is connected to the second power supply terminal VGH, the pull-up node PU, the pull-down node PD, and the first power supply terminal VGL, respectively, and the third pull-down sub-circuit 403 is configured to input the second power supply signal of the second power supply terminal VGH to the pull-down node PD in response to the potential of the pull-up node PU, and input the first power supply signal of the first power supply terminal VGL to the pull-down node PD in response to the potential of the pull-up node PU.
Specifically, referring to fig. 5, the third pull-down sub-circuit 403 may include a tenth transistor M4, an eleventh transistor M5, a twelfth transistor M6, and a thirteenth transistor M7. Wherein the gate and the first pole of the tenth transistor M4 are connected to the second power supply terminal VGH, and the second pole is connected to the first pole of the thirteenth transistor M7; the gate of the eleventh transistor M5 is connected to the second pole of the tenth transistor M4, the first pole is connected to the second power supply terminal VGH, and the second pole is connected to the pull-down node PD; the twelfth transistor M6 has a first pole connected to the pull-down node PD, a gate connected to the pull-up node PU, and a second pole connected to the first power supply terminal VGL; the thirteenth transistor M7 has a first pole connected to the second pole of the tenth transistor M4, a gate connected to the pull-up node PU, and a second pole connected to the first power supply terminal VGL.
Still optionally, the shift register may further include:
the frame reset circuit 70 is respectively connected with the frame reset signal terminal Trst, the first power supply terminal VGL, the pull-up node PU and the output terminal Out; the frame reset circuit 70 is configured to respond to the frame reset signal of the frame reset signal terminal Trst to perform frame reset on the pull-up node PU and the output terminal Out by the first power signal of the first power terminal VGL, respectively.
Referring to fig. 5, the frame reset circuit 70 may include:
The first frame reset sub-circuit 701 is connected to the first output terminal Gn, the frame reset signal terminal Trst, and the first power supply terminal VGL, and the first frame reset sub-circuit 701 is configured to input a first power supply signal of the first power supply terminal VGL to the first output terminal Gn in response to a frame reset signal of the frame reset signal terminal Trst, so as to perform frame reset on the first output terminal Gn by the first power supply signal;
The second frame reset sub-circuit 702 is respectively connected to the second output terminal Cout N, the frame reset signal terminal Trst and the first power supply terminal VGL, and the second frame reset sub-circuit 702 is configured to input the first power supply signal of the first power supply terminal VGL to the second output terminal Cout N in response to the frame reset signal of the frame reset signal terminal Trst, so as to perform frame reset on the second output terminal Cout N by the first power supply signal;
The third frame reset sub-circuit 703 is connected to the pull-up node PU, the frame reset signal terminal Trst, and the first power supply terminal VGL, and the third frame reset sub-circuit 703 is configured to input a first power supply signal of the first power supply terminal VGL to the pull-up node PU in response to a frame reset signal of the frame reset signal terminal Trst, so as to perform frame reset on the pull-up node PU through the first power supply signal.
Specifically, referring to fig. 5, the first frame reset sub-circuit 701 may include a fourteenth transistor M10A, the second frame reset sub-circuit 702 may include a fifteenth transistor M10B, and the third frame reset sub-circuit 703 may include a sixteenth transistor M11. When the display of a frame is finished, the frame reset signal of the frame reset signal terminal Trst is at a high level, and at this time, the fourteenth transistor M10A, the fifteenth transistor M10B and the sixteenth transistor M11 are all turned on, so that the first power signal of the first power terminal VGL can be respectively input into the first output terminal Gn, the second output terminal Cout N and the pull-up node PU, and the frame reset of the first output terminal Gn, the second output terminal Cout N and the pull-up node PU is realized.
Fig. 6 shows a signal-side timing diagram of a shift register according to a first embodiment of the present invention, and referring to fig. 6, the shift register specifically operates as follows:
S1,: the Input terminal Input inputs a high level, the pull-up node PU is precharged through the first transistors M1A and M1B, the potential of the pull-up node PU is pulled high, VGL is changed to VGH, and simultaneously, the reset signal Input high potential of the reset signal terminal Cout N-1 (the reset signal of the initial row is the STV signal) turns on the fifth transistor MT2, and VGH is charged at the second node N and the third node P.
S2, stage: the Input signal of the Input terminal is changed from VGH to VGL, the reset signal is changed from VGH to VGL, the first node Q, the second node N and the third node P are all in a floating state, and the high level state is kept until the next frame. Because the potentials of the first node Q, the second node N, and the third node P are VGH, the VGH voltage of the pull-up node PU cannot leak through the input circuit 10, the reset circuit 20, and the noise reduction circuit 60, so that a higher voltage can be maintained in the Touch pit until the potential of the clock signal is changed from VGL to VGH, the pull-up node PU completes bootstrap through the capacitor C1, and the sixth transistor M8A and the seventh transistor M8B are turned on to complete output.
S3, stage: the potential of the clock signal is changed from VGH to VGL, at this time, the sixth transistor M8A and the seventh transistor M8B are still in the on state, the first output terminal Gn and the second output terminal Cout N are pulled down to VGL from VGH, the Reset signal of the Reset signal terminal Reset turns on the second transistors M2A and M2B through the high level, the potential of the pull-up node PU is pulled down, and the potential of the pull-down node PD is pulled up.
S4, stage: the pull-down node PD maintains a high level, and noise is reduced by the noise reduction circuit 60, and the potentials of the first output terminal Gn and the second output terminal Cout N maintain a low level.
Finally, it should be noted that the transistors used in all embodiments of the present invention may be thin film transistors, field effect transistors, or other devices with the same characteristics, and according to the function in the circuit, the transistors used in the embodiments of the present invention are mainly switching transistors. Since the source and drain of the switching transistor used herein are symmetrical, the source and drain are interchangeable. In the embodiment of the invention, the source electrode is called a first pole, the drain electrode is called a second pole, or the drain electrode is called a first pole, and the source electrode is called a second pole.
In the embodiment of the invention, the pull-up circuit is connected with the first node between the first transistors, when the pull-up node is at a high level, the pull-down node is at a low level, and at the moment, the pull-up circuit can control the first node to keep at the high level. The pull-up circuit is also connected with a second node between the second transistors, and can pull up and hold the potential of the second node when the reset signal of the reset signal end is at a high level, so that the pull-up circuit can control the second node to keep at the high level when the pull-up node is at the high level later. Because the pull-up circuit can control the first node of the input circuit and the second node of the reset circuit to be at the high level when the pull-up node is at the high level, the leakage of the pull-up node through the input circuit and the reset circuit is avoided. In addition, by connecting two transistors in series in the input circuit and providing two transistors in series in the reset circuit, when the pull-up node is at a high level, leakage of the pull-up node through the input circuit and the reset circuit can be further reduced.
Example two
The embodiment of the invention also discloses a grid driving circuit which comprises a plurality of cascaded shift registers, wherein the shift registers comprise the shift registers.
In the embodiment of the invention, the pull-up circuit is connected with the first node between the first transistors, when the pull-up node is at a high level, the pull-down node is at a low level, and at the moment, the pull-up circuit can control the first node to keep at the high level. The pull-up circuit is also connected with a second node between the second transistors, and can pull up and hold the potential of the second node when the reset signal of the reset signal end is at a high level, so that the pull-up circuit can control the second node to keep at the high level when the pull-up node is at the high level later. Because the pull-up circuit can control the first node of the input circuit and the second node of the reset circuit to be at the high level when the pull-up node is at the high level, the leakage of the pull-up node through the input circuit and the reset circuit is avoided. In addition, by connecting two transistors in series in the input circuit and providing two transistors in series in the reset circuit, when the pull-up node is at a high level, leakage of the pull-up node through the input circuit and the reset circuit can be further reduced.
Example III
The embodiment of the invention also discloses a display device which comprises the grid driving circuit.
In the embodiment of the invention, the pull-up circuit is connected with the first node between the first transistors, when the pull-up node is at a high level, the pull-down node is at a low level, and at the moment, the pull-up circuit can control the first node to keep at the high level. The pull-up circuit is also connected with a second node between the second transistors, and can pull up and hold the potential of the second node when the reset signal of the reset signal end is at a high level, so that the pull-up circuit can control the second node to keep at the high level when the pull-up node is at the high level later. Because the pull-up circuit can control the first node of the input circuit and the second node of the reset circuit to be at the high level when the pull-up node is at the high level, the leakage of the pull-up node through the input circuit and the reset circuit is avoided. In addition, by connecting two transistors in series in the input circuit and providing two transistors in series in the reset circuit, when the pull-up node is at a high level, leakage of the pull-up node through the input circuit and the reset circuit can be further reduced.
For the foregoing method embodiments, for simplicity of explanation, the methodologies are shown as a series of acts, but one of ordinary skill in the art will appreciate that the present invention is not limited by the order of acts, as some steps may, in accordance with the present invention, occur in other orders or concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present invention.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The shift register, the gate driving circuit and the display device provided by the invention are described in detail, and specific examples are applied to illustrate the principles and the implementation of the invention, and the description of the above examples is only used for helping to understand the method and the core idea of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (11)
1. A shift register, comprising:
The input circuit is respectively connected with an input end and a pull-up node, and comprises two first transistors connected in series, and the input circuit is used for responding to an input signal of the input end and controlling the potential of the pull-up node;
The reset circuit is respectively connected with a reset signal end, the pull-up node and a first power end, and comprises two second transistors connected in series, and is used for responding to the reset signal of the reset signal end and inputting the first power signal of the first power end to the pull-up node;
A pull-up circuit connected to a first node between the first transistors, a pull-down node, the first power supply terminal, a second node between the second transistors, and a reset signal terminal, respectively, the pull-up circuit being configured to control a potential of the first node in response to a potential of the pull-down node and the first power supply signal, and to control a potential of the second node in response to a reset signal of the reset signal terminal;
A pull-down circuit connected to the pull-up node, the pull-down node, and an output terminal, respectively, the pull-down circuit being configured to control a potential of the pull-down node based on a potential of the pull-up node, and pull down the potential of the output terminal in response to the potential of the pull-down node;
The output circuit is respectively connected with a clock signal end, the pull-up node and the output end and is used for responding to the potential of the pull-up node and outputting a clock signal of the clock signal end to the output end;
The shift register further includes:
the noise reduction circuit is respectively connected with the pull-down node, the pull-up node and the first power supply end, and comprises two third transistors connected in series, and the noise reduction circuit is used for responding to the potential of the pull-down node and inputting the first power supply signal to the pull-up node;
the pull-up circuit is also connected with a third node between the third transistors, and is also used for responding to the reset signal of the reset signal end to control the potential of the third node;
The pull-up circuit includes:
a fourth transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the first node, and a second pole of which is connected to the first power supply terminal, the fourth transistor being configured to control a potential of the first node in response to a potential of the pull-down node and a first power supply signal of the first power supply terminal;
And a fifth transistor, wherein a gate and a first pole of the fifth transistor are connected with the reset signal terminal, a second pole of the fifth transistor is connected with the second node, and the fifth transistor is used for responding to a reset signal of the reset signal terminal and controlling the potential of the second node.
2. The shift register of claim 1, wherein a second pole of the fifth transistor is further coupled to the third node, the fifth transistor further configured to control a potential of the third node in response to a reset signal at the reset signal terminal.
3. The shift register of claim 1, wherein of the two third transistors in series, a first pole of a first one of the third transistors is connected to the pull-up node, a gate is connected to the pull-down node, and a second pole is connected to the third node;
In the two third transistors connected in series, a first pole of a second third transistor is connected with the third node, a gate is connected with the pull-down node, and a second pole is connected with the first power supply terminal.
4. The shift register of claim 1, wherein of the two first transistors in series, a gate and a first pole of a first one of the first transistors are connected to the input terminal, and a second pole is connected to the first node;
In the two first transistors connected in series, a first pole of a second first transistor is connected with the first node, a gate is connected with the input terminal, and a second pole is connected with the pull-up node.
5. The shift register of claim 1, wherein among the two second transistors connected in series, a first pole of a first one of the second transistors is connected to the pull-up node, a gate is connected to the reset signal terminal, and a second pole is connected to the second node;
and in the two second transistors connected in series, a first pole of a second transistor is connected with the second node, a grid electrode is connected with the reset signal end, and a second pole is connected with the first power supply end.
6. The shift register of claim 1, wherein the output comprises a first output and a second output, the output circuit comprising:
The first output sub-circuit is respectively connected with a clock signal end, the pull-up node and the first output end, and is used for responding to the potential of the pull-up node and outputting a clock signal of the clock signal end to the first output end as a grid driving signal of a row where the shift register is located;
and the second output sub-circuit is respectively connected with the clock signal end, the pull-up node and the second output end, and is used for responding to the potential of the pull-up node and outputting the clock signal of the clock signal end to the second output end as a reset signal of the next row of the row where the shift register is located.
7. The shift register of claim 6, wherein the pull-down circuit is further coupled to the first power supply terminal, the pull-down circuit comprising:
The first pull-down subcircuit is respectively connected with the pull-down node, the first power supply end and the first output end, and is used for responding to the potential of the pull-down node and pulling down the potential of the first output end through a first power supply signal of the first power supply end;
and the second pull-down sub-circuit is respectively connected with the pull-down node, the first power supply end and the second output end, and is used for responding to the potential of the pull-down node and pulling down the potential of the second output end through the first power supply signal of the first power supply end.
8. The shift register of claim 1, wherein the pull-down circuit is further coupled to the first power supply terminal and the second power supply terminal, respectively, the pull-down circuit comprising:
The third pull-down sub-circuit is respectively connected with the second power supply end, the pull-up node, the pull-down node and the first power supply end, and is used for responding to the potential of the pull-up node, inputting a second power supply signal of the second power supply end to the pull-down node and responding to the potential of the pull-up node, and inputting the first power supply signal of the first power supply end to the pull-down node.
9. The shift register of claim 1, wherein the shift register further comprises:
The frame reset circuit is respectively connected with the frame reset signal end, the first power end, the pull-up node and the output end; the frame reset circuit is used for responding to the frame reset signal of the frame reset signal end and respectively carrying out frame reset on the pull-up node and the output end through the first power signal of the first power end.
10. A gate drive circuit comprising a plurality of cascaded shift registers, the shift registers comprising the shift register of any of claims 1-9.
11. A display device comprising the gate driver circuit according to claim 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110390685.5A CN113113070B (en) | 2021-04-12 | 2021-04-12 | Shifting register, grid driving circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110390685.5A CN113113070B (en) | 2021-04-12 | 2021-04-12 | Shifting register, grid driving circuit and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113113070A CN113113070A (en) | 2021-07-13 |
| CN113113070B true CN113113070B (en) | 2024-08-13 |
Family
ID=76715961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110390685.5A Active CN113113070B (en) | 2021-04-12 | 2021-04-12 | Shifting register, grid driving circuit and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113113070B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023097477A1 (en) * | 2021-11-30 | 2023-06-08 | 京东方科技集团股份有限公司 | Shift register unit, gate driving circuit and display apparatus |
| CN114913805A (en) * | 2022-06-20 | 2022-08-16 | 京东方科技集团股份有限公司 | Shifting register unit and control method thereof, grid drive circuit and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103996370A (en) * | 2014-05-30 | 2014-08-20 | 京东方科技集团股份有限公司 | Shifting register unit, grid drive circuit, display device and drive method |
| CN105118417A (en) * | 2015-09-25 | 2015-12-02 | 京东方科技集团股份有限公司 | Shifting register and driving method thereof as well as gate drive circuit and display device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107845403B (en) * | 2017-11-07 | 2021-04-23 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN107657983B (en) * | 2017-11-09 | 2024-03-26 | 京东方科技集团股份有限公司 | Shift register unit, driving method, grid driving circuit and display device |
| CN108281124B (en) * | 2018-03-30 | 2020-11-24 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN110808015B (en) * | 2018-03-30 | 2021-10-22 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, display device and drive method |
| CN109935185B (en) * | 2018-07-18 | 2022-07-01 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN110111720A (en) * | 2019-05-20 | 2019-08-09 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, display panel and display device |
| CN110648638B (en) * | 2019-09-25 | 2022-03-25 | 合肥京东方卓印科技有限公司 | Gate drive circuit, pixel circuit, display panel and display device |
-
2021
- 2021-04-12 CN CN202110390685.5A patent/CN113113070B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103996370A (en) * | 2014-05-30 | 2014-08-20 | 京东方科技集团股份有限公司 | Shifting register unit, grid drive circuit, display device and drive method |
| CN105118417A (en) * | 2015-09-25 | 2015-12-02 | 京东方科技集团股份有限公司 | Shifting register and driving method thereof as well as gate drive circuit and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113113070A (en) | 2021-07-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3611720B1 (en) | Shift register unit, gate driving circuit, and driving method | |
| US11688326B2 (en) | Shift register, gate driving circuit, display apparatus and driving method | |
| CN108932933B (en) | Shift register, grid drive circuit and display device | |
| US10269282B2 (en) | Shift register, gate driving circuit, display panel and driving method | |
| US11037502B2 (en) | Shift register and driving method thereof, gate driving circuit, array substrate, and display device | |
| CN105976787B (en) | Gate driving circuit and its driving method and display device | |
| US10283030B2 (en) | Shift register, gate driver, display panel and driving method | |
| EP3712880B1 (en) | Gate driver circuit, display device and driving method therefor | |
| EP3477646A1 (en) | Shift register unit, driving method, gate driving circuit and display apparatus | |
| CN111081180B (en) | Array substrate, detection method thereof and display device | |
| CN109710113B (en) | Gate driving unit, gate driving circuit and driving method thereof, and display device | |
| CN105405387B (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| US20170287388A1 (en) | Shift register, method for driving same, gate driving circuit | |
| US20140104152A1 (en) | Shift register, gate driving apparatus of liquid crystal display and liquid crystal display | |
| CN110264937B (en) | Gate drive circuit, test method thereof and display device | |
| CN107093414B (en) | A kind of shift register, its driving method, gate driving circuit and display device | |
| CN110880304B (en) | Shift register unit, grid driving circuit, display device and driving method | |
| US10490156B2 (en) | Shift register, gate driving circuit and display panel | |
| CN107068033B (en) | Shift register unit, gate drive circuit, test method and display device | |
| CN109448656B (en) | Shift register and gate drive circuit | |
| CN104091574A (en) | Shifting register, array substrate, display device and driving method of display device | |
| JP2016517607A (en) | Shift register, display device, gate drive circuit, and drive method | |
| US10943517B2 (en) | Shift register, method for driving the same, gate drive circuit and display device | |
| CN113113070B (en) | Shifting register, grid driving circuit and display device | |
| KR20140119690A (en) | Shift register, gate driving circuit, array substrate and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |