CN113097087B - Semiconductor device and testing method thereof - Google Patents

Abstract

The invention discloses a semiconductor device and a test method thereof, wherein the semiconductor device comprises a first semiconductor structure, a second semiconductor structure and a plurality of bonding connection structures arranged between the first semiconductor structure and the second semiconductor structure, and the plurality of bonding connection structures are provided with bonding surfaces. The first semiconductor structure comprises a plurality of doped regions, the second semiconductor structure comprises a doped substrate and a plurality of conductive pads located on the back surface of the doped substrate, and the plurality of bonding connection structures are connected in series to form a chain structure through the plurality of doped regions and the plurality of conductive pads. Because the chain structure is formed by connecting the plurality of doped regions in series, the interaction influence of the doped regions and the bonding surface can be checked by performing an electrical test on the chain structure, so that the health condition of the bonding surface is comprehensively checked, and the quality of a product is improved.

Description

Semiconductor device and testing method thereof

Technical Field

The present invention relates generally to electronic devices, and more particularly, to a semiconductor device and a method of testing the same.

Background

In a semiconductor manufacturing process, Test Keys (TKs) are usually disposed at certain fixed positions on a Wafer, so that in the semiconductor manufacturing process, Wafer Acceptance Tests (WATs) are performed on the Test keys to obtain WAT Test electrical parameters, and whether the manufacturing process of each part in the semiconductor manufacturing process meets corresponding requirements is monitored according to the electrical parameters obtained in the WAT Test.

In the existing architecture, the interconnection layers of different chips are connected by bonding through the bonding surface, and after the interconnection layers of different chips are bonded, various quality problems often occur on the bonding surface. The traditional detection structure can detect some problems of disconnection or short circuit, but the quality inspection capability on the bonding surface is limited, the detection result is normal sometimes, but the quality problem still occurs on the bonding surface, and the detection object or the detection mode is not comprehensive.

Disclosure of Invention

The invention aims to provide a semiconductor device and a test method thereof, aiming at testing the influence of a doped region on a bonding surface so as to comprehensively check the health condition of the bonding surface.

In one aspect, the present invention provides a semiconductor device comprising:

a first semiconductor structure comprising a plurality of doped regions;

a second semiconductor structure comprising a doped substrate and a plurality of conductive pads located on a back side of the doped substrate away from the first semiconductor structure;

a plurality of bonding connection structures disposed between the first semiconductor structure and the second semiconductor structure, the plurality of bonding connection structures being connected in series through the doped region and the plurality of conductive pads to form a chain structure;

wherein the plurality of bonding connection structures have bonding surfaces.

Further preferably, the chain structure includes a plurality of chains arranged in parallel.

Further preferably, the doped regions and the conductive pads are staggered in a vertical direction, and each doped region and each conductive pad are alternately connected in series through the bonding connection structure.

Further preferably, the first semiconductor structure is a CMOS, the plurality of doped regions include N-type doped regions and P-type doped regions, and the N-type doped regions and the P-type doped regions are alternately connected in series in the chain structure.

Further preferably, the second semiconductor structure is a NAND, and the doped substrate includes a P-type doped region and a high-voltage P-type well region.

Further preferably, the second semiconductor structure is a DRAM, and the doped substrate includes a P-type doped region and an N-type doped region.

Further preferably, the bonding connection structure has a first bonding contact and a second bonding contact on the bonding surface, and the material of the first bonding contact and the material of the second bonding contact are copper.

Further preferably, the bonding connection structure further includes a through-silicon contact electrically connected to the first bonding contact, and the through-silicon contact is connected to the conductive pad through the doped substrate.

Further preferably, the first semiconductor structure further includes a substrate, the substrate has a plurality of N-type well regions and P-type well regions, a P-type doped region in the doped region is located in the N-type well region of the substrate, and an N-type doped region in the doped region is located in the P-type well region of the substrate.

Further preferably, the chain structure is disposed around an edge of the semiconductor device.

In another aspect, the present invention provides a method of testing a semiconductor device, the method comprising:

providing a semiconductor device as recited in any of the above, the chain structure comprising a first end and a second end;

inputting a preset electric signal to a first end of the chain structure;

and collecting the output electric signal at the second end of the chain structure so as to perform electrical test on the chain structure.

Further preferably, the chain structure is two parallel chains, and the testing method further comprises:

inputting a preset voltage signal to the first end of one of the chain structures;

and collecting an output current signal at the second end of the other chain structure so as to test the insulation performance between the two chain structures.

The invention has the beneficial effects that: the invention provides a semiconductor device and a test method thereof, comprising a first semiconductor structure, a second semiconductor structure and a plurality of bonding connection structures arranged between the first semiconductor structure and the second semiconductor structure, wherein the plurality of bonding connection structures are provided with bonding surfaces. The first semiconductor structure comprises a plurality of doped regions, the second semiconductor structure comprises a doped substrate and a plurality of conductive pads positioned on the back surface of the doped substrate, and the plurality of bonding connection structures are connected in series to form a chain structure through the plurality of doped regions and the plurality of conductive pads. Because the chain structure connects a plurality of doped regions in series, the interaction influence between the doped regions and the bonding surface can be checked by performing electrical test on the chain structure, so that the health condition of the bonding surface is comprehensively checked, and the quality of a product is improved.

Drawings

The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.

Fig. 1 is a schematic cross-sectional structure diagram of a semiconductor device according to a first embodiment of the present invention;

fig. 2 is a schematic cross-sectional view of a chain structure in a semiconductor device according to a first embodiment of the present invention;

fig. 3 is a schematic top view of a first semiconductor structure in a semiconductor device according to a first embodiment of the present invention;

fig. 4 is a schematic top view of a first semiconductor structure in a semiconductor device according to a second embodiment of the present invention;

fig. 5 is a schematic top view of a second semiconductor structure in a semiconductor device according to a second embodiment of the present invention;

fig. 6 is a schematic top view of a semiconductor device according to a second embodiment of the present invention;

fig. 7 is a flowchart illustrating a method for testing a semiconductor device according to a third embodiment of the present invention;

fig. 8 is a flowchart illustrating a method for testing a semiconductor device according to a fourth embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.

It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along the tapered surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers above, and/or below it. The layer may comprise a plurality of layers. For example, the interconnect layers may include one or more conductive layers and contact layers (in which contacts, interconnect lines, and one or more dielectric layers are formed).

As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate. Directions are expressed herein in cartesian coordinates, with reference to the substrate, the term "vertical direction" refers to a direction perpendicular to the substrate, denoted by "Z"; the directions perpendicular to "Z" are denoted by "X" and "Y" in the drawings.

It should be noted that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the invention. The semiconductor device 100 includes a first semiconductor structure 10, a second semiconductor structure 11, and a plurality of bonding connection structures 12 disposed between the first semiconductor structure 10 and the second semiconductor structure 11. The first semiconductor structure 10 includes a plurality of doped regions 101, and each doped region 101 may be an N-type doped region or a P-type doped region. Optionally, the first Semiconductor structure 10 may be a Complementary Metal Oxide Semiconductor (CMOS) controller chip, in which case the doped region 101 in the first Semiconductor structure 10 serves as a source and a drain of the CMOS, and the first Semiconductor structure 10 further includes a substrate (not shown in the figure) and other circuit structures.

The second semiconductor structure 11 includes a doped substrate 111 and a plurality of conductive pads 112 located on a back surface of the doped substrate 111 away from the first semiconductor structure 10 (the side of the doped substrate 111 away from the first semiconductor structure 10 is referred to as the back surface). Alternatively, the second semiconductor structure 11 may be a memory chip, and then the second semiconductor structure 11 further includes a memory array. The doping type of the doped substrate 111 may be provided according to the type of the second semiconductor structure 11, specifically, the second semiconductor structure 11 may be a NAND memory structure, and then the doped substrate 111 may be a High Voltage P Well (HVPW), a P-type doped region, or a combination of the HVPW and the P-type doped region, in this embodiment, the doped substrate 111 is a combination of the HVPW and the P-type doped region, and is thus represented by different patterns. The second semiconductor structure 11 may also be a DRAM, and the doped substrate 111 may be a P-type doped region or an N-type doped region or a combination of both.

A plurality of bonding connection structures 12 are disposed between the first semiconductor structure 10 and the second semiconductor structure 11 to form a metal interconnection structure, and have a bonding surface 121 therebetween. The bonding surface 121 divides the plurality of bonding connection structures 12 into a first bonding connection structure 122 connected to the first semiconductor structure 10 and a second bonding connection structure 123 connected to the second semiconductor structure 11. When the first semiconductor structure 10 is a CMOS control chip, the first bonding connection structure 122 is a peripheral interconnection layer connected to a CMOS; when the second semiconductor structure 11 is a NAND or a DRAM, the second bonding connection structure 123 is an array interconnection layer connected to the NAND or the DRAM. The bond connection structure 12 is formed by a plurality of via structures and conductive contacts, both of which are conductive materials. It should be noted that, although the bonding connection structure 12 in fig. 1 extends in the vertical direction (Z) and the via structures are aligned in the vertical direction (Z), the position of the via structures in the X direction is not limited in the embodiment of the present invention, that is, the via structures may be offset in the vertical direction (Z) according to the circuit design requirement.

Specifically, the bonding connection structure 12 has a first bonding contact 1221 and a second bonding contact 1231 at the bonding surface 121, the first bonding contact 1221 belongs to the first bonding connection structure 122, and the second bonding contact 1231 belongs to the second bonding connection structure 123, so that the first bonding connection structure 122 and the second bonding connection structure 123 are aligned and bonded through the first bonding contact 1221 and the second bonding contact 1231. It is understood that fig. 1 should also include a dielectric layer (not shown), i.e., bonding connection 12 in fig. 1 is formed in the dielectric layer, and the bonding connections 12 are insulated from each other by the dielectric layer.

The material of the first and second bonding contacts 1221 and 1231 at the bonding surface 121 is typically copper. Optionally, the first and second bonding contacts 1221, 1231 and other conductive contacts may be tungsten, aluminum or other conductive material. The inventor researches and discovers that, because some chemical reactions may occur in processes such as chemical mechanical polishing and binding in the bonding process to generate copper ions, after bonding, the doped region 101 may affect the distribution of the electric potential, thereby affecting the distribution of the copper ions on the bonding surface 121, and possibly causing the unevenness of the first bonding contact 1221 and the second bonding contact 1231. The two first bonding contacts 1221 and the two second bonding contacts 1231 are disconnected due to the depression, the bonding surface 121 is separated from the top by the protrusion due to the protrusion, and the unevenness may cause some problems such as very small bubbles and copper diffusion.

In the present embodiment, the plurality of bonding connection structures 12 are connected in series to form a chain structure through the plurality of doped regions 101 and the plurality of conductive pads 112. Referring to fig. 2, fig. 2 is a schematic cross-sectional view of a chain structure in a semiconductor device according to a first embodiment of the present invention. The chain structure 110 includes a plurality of doped regions 101, a plurality of bonding connection structures 12 and a plurality of conductive pads 112, and the chain structure 110 connects the plurality of doped regions 101 in series for subsequent checking whether the doped regions 101 affect the exposed metal of the bonding surface 121. Once the doped region 101 has caused a defect in the metal of the bonding surface 121, it can be inspected by some electrical tests of the chain structure 110.

Preferably, the doped regions 101 and the conductive pads 112 are arranged alternately in the Z direction, and in the chain structure 110, the doped regions 101 and the conductive pads 112 are alternately connected in series. More specifically, every two adjacent bonding connection structures 12 are connected to one conductive pad 112, and the two bonding connection structures 12 connected to one conductive pad 112 are respectively connected to two adjacent doped regions 101.

On the other hand, the doped substrate 111 in the second semiconductor structure 11 may also affect the metal located at the bonding surface 121. The bonding connection structure 12 may further include a Through Silicon Contact (TSC) 1232 electrically connected to the second bonding Contact 1231, the Through Silicon Contact 1232 being connected to the conductive pad 112 Through the doped substrate 111 to the backside. Since the through-silicon contact 1232 penetrates through the doped substrate 111 and the conductive pad 112 is connected to the doped substrate 111, the doped substrate 111 interacts with the metal at the bonding surface 121, and a subsequent electrical test through the chain structure 110 can also check whether the doped substrate 111 causes a defect in the metal of the bonding surface 121.

Referring to fig. 3, fig. 3 is a schematic top view of a first semiconductor structure in a semiconductor device according to a first embodiment of the present invention. It should be noted that the top view of the first semiconductor structure 10 is seen from the bonding surface 121 towards the doped region 101. It should be noted that when the area of the first bonding contact 1221 is larger than that of the wire contacts of other layers in the XY plane, only the first bonding contact 1221 may be shown in the top view, but the size of each conductive contact and the number of conductive contacts are not limited by the embodiment of the present invention. When the conductive contacts of the other layers are larger than the size of the first bonding contact 1221, the other conductive contacts can also be seen in the top view.

When the first semiconductor structure 10 is a CMOS, the first semiconductor structure 10 further includes a substrate 102 and a plurality of doped regions 101 located in the substrate 102, and the substrate 102 has a plurality of N-type well regions 1021 and a plurality of P-type well regions 1022. The doped region 101 also includes an N-type doped region and a P-type doped region, and the doped region 101 is formed in the substrate 102 by ion implantation (implantation). Doped regions also need to be formed in the substrate region corresponding to each doped region 101, and the doping type of the substrate 102 is different from that of the doped region 101 formed therein. Specifically, the P-type doped region in the doped region 101 is located in an N-type well 1021 of the substrate 102, and the N-type doped region in the doped region 101 is located in a P-type well 1022 of the substrate 102.

In the present embodiment, the number of the chain structures 110 is 1. Preferably, the plurality of doped regions 101 are connected in series to form a chain structure 110, and the N-type doped regions and the P-type doped regions are alternately arranged.

In the semiconductor device 100 according to the first embodiment of the present invention, the plurality of doped regions 101 in the first semiconductor structure 10, the bonding connection structure 12 and the conductive pad 112 are connected in series to form a chain structure 110, and the bonding connection structure 12 further passes through the doped substrate 111, so that the chain structure 110 is electrically tested to check whether the doped regions 101 and the doped substrate 111 cause quality defects on the bonding surface 121. Compared with the conventional test structure, the chain structure 110 provided by the first embodiment of the invention can be inspected more comprehensively during the electrical test, so that the process adjustment can be made in time until the test is passed, thereby improving the product quality.

Referring to fig. 4, fig. 4 is a schematic top view of a first semiconductor structure in a semiconductor device according to a second embodiment of the present invention. For ease of understanding, the same structures in the second embodiment as in the first embodiment are continued using the same reference numerals as in fig. 1 to 3, and the cross-sectional structure at a-a1 in fig. 4 is the same as in fig. 1. It is to be noted that the top view of the first semiconductor structure 10 is seen from the bonding surface 121 towards the doped region 101.

As in the first embodiment, first semiconductor structure 10 includes a substrate 102, and substrate 102 also includes N-type well region 1021 and P-type well region 1022. Preferably, the doping types of the doped regions 101 are alternately arranged, and the doped regions 101 located in the N-type well 1021 are P-type, and the doped regions 101 located in the P-type well 1022 are N-type. Wherein, the two N-well regions 1021 in relatively close proximity may or may not be connected, which is related to the distance between the two chain structures 110 and the actual process.

In the second embodiment, the plurality of doped regions 101 in the first semiconductor structure 10 form two chain structures 110 as shown in fig. 2. Specifically, the plurality of doped regions 101 are arranged in two rows along the X-direction, the first row of doped regions 101 are connected in series to form a chain structure 110, the second row of doped regions 101 are connected in series to form a chain structure 110, and the two chain structures 110 are not electrically connected and are arranged in parallel. In some embodiments, the number of chain structures 110 may be greater than 2.

Referring to fig. 5, fig. 5 is a schematic top view illustrating a second semiconductor structure in a semiconductor device according to a second embodiment of the present invention. It is to be noted that the top view of the second semiconductor structure 11 is seen from the bonding surface 121 towards the doped substrate 111. The second semiconductor structure 11 includes a doped substrate 111. The second bonding contacts 1231 in the second semiconductor structure 11 are arranged in the same manner as the first bonding contacts 1221 in the first semiconductor structure 10 in fig. 4, corresponding to the structure of the two-chain structure. These second bonding contacts 1231 are connected to conductive pads 112 below the doped substrate 111.

Referring to fig. 6, fig. 6 is a schematic top view of a semiconductor device according to a second embodiment of the present invention. The top view of the semiconductor device 100 is intended to show the location of the link structure 110 relative to the semiconductor device 100, and so other structures are omitted from the illustration. In the second embodiment, the chain structure 110 is disposed around the edge of the semiconductor device 100 (the doped substrate 111 is used to represent the extent of the entire semiconductor device 100 in the XY plane in the figure), and the purpose is to test the defect at the edge of the semiconductor device 100, because the probability of generating the defect at the edge is generally high. In some embodiments, the chain structure 110 may be located at other positions of the semiconductor device 100 according to actual test requirements.

In the second embodiment, compared with the one-bar chain structure 110 in the first embodiment, in addition to the advantages of the first embodiment, the two-bar chain structure 110 has the advantage that the insulation performance of each one-bar chain structure 110 and other structures can be checked through electrical tests, and a specific detection method will be described below.

Referring to fig. 7, fig. 7 is a flowchart illustrating a method for testing a semiconductor device according to a third embodiment of the present invention. The test method of the semiconductor device is used to test the performance of the semiconductor device 100, and therefore the third embodiment of the present invention continues to use the reference numerals of the semiconductor device 100 (fig. 1 to 3). Referring to FIG. 6, the testing method includes the following steps S1-S3.

Step S1: there is provided a semiconductor device 100 as claimed in any one of the above solutions, said chain structure 110 comprising a first end 1101 and a second end 1102.

Step S2: a predetermined electrical signal is input to the first end 1101 of the chain structure 110.

Step S3: the output electrical signal is collected at the second end 1102 of the chain structure 110 for electrical testing of the chain structure 110.

In a third embodiment, when the preset electrical signal is a voltage signal, the output current signal can be collected, and by setting different voltage signal values, the breakdown voltage can be tested according to the collected current signal result. When the preset electric signal is a current signal, the output voltage signal can be collected, and the leakage current can be tested according to the collected voltage signal result by setting different current signal values. The chain structure 110 may also be endurance tested by setting different predetermined electrical signals. Most importantly, the testing method puts the influencing factors of the doped region into the test, can comprehensively check the health condition of the bonding surface 121 through the electrical test, avoids that the bonding surface defects caused by the doped region cannot be checked, and further can improve the quality of the product.

Referring to fig. 8, fig. 8 is a flowchart illustrating a testing method of a semiconductor device according to a fourth embodiment of the invention. The testing method of the semiconductor device is used to test the performance of the semiconductor device 100, and therefore the fourth embodiment of the present invention continues to use the reference numerals of the semiconductor device 100 (fig. 1-2). Referring to fig. 4-6, the testing method includes the following steps S100-S500. The test method includes the following steps S100 to S500.

Step S100: there is provided a semiconductor device 100 as claimed in any one of the above solutions, said chain structure 110 comprising a first end 1101 and a second end 1102.

Step S200: a predetermined electrical signal is input to the first end 1101 of the chain structure 110.

Step S300: the output electrical signal is collected at the second end 1102 of the chain structure 110 for electrical testing of the chain structure 110.

Step S400: inputting a predetermined voltage signal to the first terminal 1101 of one of the chain structures 110;

step S500: the output current signal is collected at the second end 1102 of another one of the chain structures 110 to test the insulation performance between the two chain structures 110.

In the fourth embodiment, steps S100 to S300 are the same as steps S1 to S3 in the third embodiment, and detailed operations and advantageous effects thereof are not repeated herein. The steps S400 and S500 are for testing the insulation performance between the two chain structures 110. Wherein the two link structures 110 are aligned from the respective first end 1101 to the second end 1102. Specifically, a preset voltage signal is input to the first end 1101 of the first chain structure 110, and the output current signal is collected at the second end 1102 of the second chain structure 110, so that if the two chain structures 110 are connected at a certain position, the measured current signal is obviously different from the result measured under the condition of complete insulation, and the parameter of the test result can be compared with the standard experiment result for analysis to determine whether the insulation performance between the two chain structures 110 is good. In fact, this can also be used to determine whether one link structure 110 is connected to another structure, i.e. whether the insulation between itself and another structure is good, and the purpose of providing two link structures 110 is here to indicate that one link structure 110 may not have good insulation between itself and another structure nearby if the insulation between two link structures 110 is not good.

The above embodiments are only described to help understand the technical solution of the present invention and the core idea thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (12)

1. A semiconductor device, comprising:

a first semiconductor structure comprising a plurality of doped regions, the doped regions comprising a source and a drain;

a second semiconductor structure comprising a doped substrate and a plurality of conductive pads located on a back side of the doped substrate away from the first semiconductor structure;

a plurality of bonding connection structures disposed between the first semiconductor structure and the second semiconductor structure, the plurality of bonding connection structures being connected in series through the doped region and the plurality of conductive pads to form a chain structure;

wherein the plurality of bonding connection structures have bonding surfaces, and the chain structure is used for testing the influence of the source and the drain of the first semiconductor structure on the bonding surfaces.

2. The semiconductor device of claim 1, wherein the chain structure comprises a plurality of chains arranged in parallel.

3. The semiconductor device of claim 1, wherein the doped regions and the conductive pads are staggered in a vertical direction, and wherein the doped regions and the conductive pads are alternately connected in series by the bonding connection structure.

4. The semiconductor device of claim 1, wherein the first semiconductor structure is a CMOS, the plurality of doped regions comprises N-type doped regions and P-type doped regions, and the N-type doped regions and the P-type doped regions are alternately connected in series in the chain structure.

5. The semiconductor device of claim 1, wherein the second semiconductor structure is a NAND and the doped substrate comprises a P-type doped region and a hvpwell region.

6. The semiconductor device of claim 1, wherein the second semiconductor structure is a DRAM, and wherein the doped substrate comprises a P-type doped region and an N-type doped region.

7. The semiconductor device of claim 1, wherein the bonding connection structure has a first bonding contact and a second bonding contact at the bonding face, the first bonding contact and the second bonding contact being copper.

8. The semiconductor device of claim 7, wherein the bonding connection structure further comprises a through-silicon contact electrically connected to the first bonding contact, the through-silicon contact being connected to the conductive pad through the doped substrate.

9. The semiconductor device of claim 4, wherein the first semiconductor structure further comprises a substrate having a plurality of N-well regions and P-well regions, wherein the P-doped regions of the doped regions are located in the N-well regions of the substrate, and wherein the N-doped regions of the doped regions are located in the P-well regions of the substrate.

10. The semiconductor device of claim 1, wherein the chain structure is disposed around an edge of the semiconductor device.

11. A method of testing a semiconductor device, the method comprising:

providing a semiconductor device according to any of claims 1 to 10, said chain structure comprising a first end and a second end;

inputting a preset electric signal to a first end of the chain structure;

and collecting the output electric signal at the second end of the chain structure so as to perform electrical test on the chain structure.

12. The method for testing a semiconductor device according to claim 11, wherein the chain structure is two arranged in parallel, the method further comprising:

Inputting a preset voltage signal to the first end of one of the chain structures;

and collecting an output current signal at the second end of the other chain structure so as to test the insulation performance between the two chain structures.

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