CN113078257A - Resistive random access memory and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 35
- 238000002955 isolation Methods 0.000 claims description 28
- 230000008569 process Effects 0.000 claims description 24
- 239000007772 electrode material Substances 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910004166 TaN Inorganic materials 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 2
- 229910008599 TiW Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910004143 HfON Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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Abstract
本发明提供一种电阻式随机存取存储器及其制造方法。所述电阻式随机存取存储器包括第一电极、第二电极、第三电极、可变电阻层、选择层、第一位线以及第二位线。所述第一电极设置于衬底上。所述第二电极与所述第三电极设置于所述第一电极上，其中所述第二电极与所述第三电极彼此分隔开，且各自与所述第一电极的侧壁与顶面重叠。所述可变电阻层设置于所述第一电极与所述第二电极之间以及所述第一电极与所述第三电极之间。所述选择层设置于所述可变电阻层与所述第一电极之间。所述第一位线设置于所述第二电极上，且经由第一触点而与所述第二电极电性连接。所述第二位线设置于所述第三电极上，且经由第二触点而与所述第三电极电性连接。
The present invention provides a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a first electrode, a second electrode, a third electrode, a variable resistance layer, a selection layer, a first bit line and a second bit line. The first electrode is disposed on the substrate. The second electrode and the third electrode are disposed on the first electrode, wherein the second electrode and the third electrode are separated from each other, and are respectively connected to the sidewalls and the top of the first electrode. faces overlap. The variable resistance layer is disposed between the first electrode and the second electrode and between the first electrode and the third electrode. The selection layer is disposed between the variable resistance layer and the first electrode. The first bit line is disposed on the second electrode, and is electrically connected to the second electrode through a first contact. The second bit line is disposed on the third electrode, and is electrically connected to the third electrode through a second contact.
Description
Technical Field
The present invention relates to a memory and a method for manufacturing the same, and more particularly, to a Resistive Random Access Memory (RRAM) and a method for manufacturing the same.
Background
The resistive random access memory has advantages of high operation speed, low power consumption, and the like, and thus is a nonvolatile memory which has been widely studied in recent years. Generally, a resistance random access memory includes an upper electrode, a lower electrode, and a variable resistance layer between the upper electrode and the lower electrode. When a voltage is applied to the upper and lower electrodes, a conductive path (generally referred to as a conductive wire (CF)) may be formed in the variable resistance layer to perform a set operation or may be broken to perform a reset operation, thereby providing a related memory function.
In order to achieve high storage capacity in the same area, a structure (1TnR) in which a single transistor is connected to a plurality of memory cells at the same time is developed. For such a high density resistance random access memory, a problem of sneak current leakage (sneak current leakage) is encountered, which may cause adjacent memory cells to affect each other during operation, resulting in a decrease in reliability.
Disclosure of Invention
The present invention is directed to a resistive random access memory in which a second electrode and a third electrode, which are disposed on a first electrode and spaced apart from each other, are electrically connected to different bit lines, respectively.
The present invention is directed to a method for manufacturing a resistive random access memory, which is used to manufacture the resistive random access memory.
According to an embodiment of the present invention, a resistance random access memory includes a first electrode, a second electrode, a third electrode, a variable resistance layer, a selection layer, a first bit line, and a second bit line. The first electrode is disposed on a substrate. The second electrode and the third electrode are disposed on the first electrode, wherein the second electrode and the third electrode are spaced apart from each other and each overlap with a sidewall and a top surface of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode and between the first electrode and the third electrode. The selection layer is disposed between the variable resistance layer and the first electrode. The first bit line is disposed on the second electrode and electrically connected to the second electrode through a first contact. The second bit line is disposed on the third electrode and electrically connected to the third electrode through a second contact.
According to an embodiment of the invention, a method for manufacturing a resistive random access memory comprises the following steps: forming a first electrode on a substrate; forming a selection layer on the first electrode; forming a variable resistance layer on the selection layer; forming a second electrode and a third electrode spaced apart from each other on the variable resistance layer, wherein the second electrode and the third electrode each overlap with a sidewall and a top surface of the first electrode; forming a first contact on the second electrode; forming a second contact on the third electrode; forming a first bit line at the first contact; a second bit line is formed over the second contact.
In view of the above, in the resistance random access memory of the present invention, the second electrode and the third electrode disposed on the first electrode are electrically connected to different bit lines, so that the memory cells on two sides of the first electrode can be operated independently. In addition, because the two adjacent memory cells respectively positioned at the two sides of the first electrode are respectively and electrically connected with different bit lines, the two adjacent memory cells can not influence each other in the operation process.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
Fig. 1A to fig. 1D are schematic cross-sectional views illustrating a manufacturing process of a resistance random access memory according to a first embodiment of the invention.
FIG. 2 is a top view of the RRAM according to the first embodiment of the present invention, wherein FIG. 1D is a cross-sectional view taken along line A-A in FIG. 2.
Fig. 3A to fig. 3B are schematic cross-sectional views illustrating a manufacturing process of a resistance random access memory according to a second embodiment of the invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Referring to fig. 1A, a substrate 100 is provided. In addition, a contact (not shown) to be connected to an electrode of the resistance random access memory is formed in the substrate 100. Next, a first electrode 102 is formed over the substrate 100. The first electrode 102 is connected to the contact described above. The first electrode 102 serves as a bottom electrode of the rram. The first electrode 102 is formed, for example, by forming an electrode material layer on the substrate 100 and then performing a patterning process on the electrode material layer. In the present embodiment, the first electrode 102 is a stripe electrode, which extends in a first direction (a direction perpendicular to the direction entering fig. 1A) on the substrate 100. In the present embodiment, the material of the first electrode 102 is, for example, Ti, Ta, TiN, TaN, TiAlN, TiW, Pt, Ir, W, Ru, graphite, or a combination thereof. Next, a dielectric layer 104 is formed on the substrate 100. A dielectric layer 104 covers the first electrode 102. In the present embodiment, the dielectric layer 104 is, for example, a silicon oxide layer.
Referring to fig. 1B, a patterning process is performed on the dielectric layer 104 to remove a portion of the dielectric layer 104, so as to form an isolation layer 106a on the top surface of the first electrode 102 and expose the sidewall and a portion of the top surface of the first electrode 102. The isolation layer 106a is used to separate a second electrode and a third electrode which are formed on the first electrode 102. In addition, after the patterning process is performed, besides forming the isolation layer 106a on the top surface of the first electrode 102, an isolation layer 106b may also be formed on the substrate 100 between two adjacent first electrodes 102 to separate the two adjacent first electrodes 102. In this embodiment, the top surface of the isolation layer 106a and the top surface of the isolation layer 106b are coplanar.
Then, a selection layer 108 is formed on the first electrode 102. In the present embodiment, the selection layer 108 is conformally formed on the substrate 100, covering the substrate 100, the first electrode 102, the isolation layer 106a and the isolation layer 106 b. The selective layer 108 is formed, for example, by a chemical vapor deposition process. In the present embodiment, the material of the selective layer 108 is, for example, Al2O3. Next, a variable resistance layer 110 is formed on the selection layer 108. The variable resistance layer 110 is formed by, for example, performing a chemical vapor deposition process. In the present embodiment, the material of the variable resistance layer 110 is, for example, HfO2、ZrO2HfZrO, HfAlO, HfON, HfSiO, HfSrO, HfYO, or combinations thereof. Then, an electrode material layer 112 is formed on the variable resistance layer 110. The electrode material layer 112 is formed by, for example, performing a chemical vapor deposition process. In the present embodiment, the material of the electrode material layer 112 is, for example, Ti, Ta, TiN, TaN, TiAlN, TiW, Pt, Ir, W, Ru, graphite, or a combination thereof.
Referring to fig. 1C, a planarization process is performed to remove a portion of the electrode material layer 112 until the variable resistance layer 110 on the isolation layer 106a and the isolation layer 106b is exposed, so as to form a second electrode 114 and a third electrode 116. The planarization process is, for example, a chemical mechanical polishing process. In detail, after the planarization process is performed, the second electrode 114 and the third electrode 116 are formed on two sides of the isolation layer 106a, and the second electrode 114 and the third electrode 116 are respectively overlapped with the sidewall and the top surface of the first electrode 102. As shown in fig. 1C, the second electrode 114 on the left side of the isolation layer 106a covers a portion of the left sidewall and the top surface of the first electrode 102, and the second electrode 116 on the right side of the isolation layer 106a covers a portion of the right sidewall and the top surface of the first electrode 102. In this way, the first memory cell 10 is configured by the first electrode 102 (lower electrode), the second electrode 114 (upper electrode), and the selection layer 108 and the variable resistance layer 110 interposed therebetween on the left side and the upper side of the first electrode 102, and the second memory cell 20 is configured by the first electrode 102 (lower electrode), the third electrode 116 (upper electrode), and the selection layer 108 and the variable resistance layer 110 interposed therebetween on the right side and the upper side of the first electrode 102.
In the embodiment, after the planarization process is performed, the variable resistance layer 110 on the isolation layer 106a and the isolation layer 106b is exposed, i.e. the planarization process uses the variable resistance layer 110 as a stop layer, but the invention is not limited thereto. In another embodiment, during the planarization process, in addition to removing a portion of the electrode material layer 112, a portion of the variable resistance layer 110 and the selection layer 108 may be removed until the top surfaces of the isolation layer 106a and the isolation layer 106b are exposed, i.e., the planarization process uses the isolation layer 106a and the isolation layer 106b as a stop layer.
In addition, in the present embodiment, the variable resistance layer 110 is used as a stop layer, so that the planarization process is more easily controlled. When the varistor layer 110 is used as a stop layer, even if the varistor layer 110 is slightly removed, the device performance is not affected because the varistor layer 110 is not a main operation region. That is, the process window (process window) of the planarization process can be increased by using the variable resistance layer 110 as a stop layer.
Then, a dielectric layer 118 is formed on the second electrode 114 and the third electrode 116. The dielectric layer 118 is formed by, for example, performing a chemical vapor deposition process. In the present embodiment, the dielectric layer 118 is, for example, a silicon oxide layer. In addition, in order to prevent oxygen atoms in the dielectric layer 118 from diffusing into the variable resistance layer 110 and affecting the operation of the memory, an oxygen barrier layer 120 may be optionally formed on the second electrode 114 and the third electrode 116 before the dielectric layer 118 is formed. The oxygen barrier layer 120 is formed by, for example, performing a chemical vapor deposition process. In the present embodiment, the material of the oxygen barrier layer 120 is, for example, Al2O3。
Referring to fig. 1D, a first contact 122a connected to the second electrode 114 and a second contact 122b connected to the third electrode 116 are formed in the dielectric layer 118. It is important that the first contact 122a and the second contact 122b are staggered, i.e., the position of the first contact 122a and the position of the second contact 122b are not aligned with each other, as shown in fig. 2. In fig. 2, for clarity, only the substrate 100, the first electrode 102, the second electrode 114, the third electrode 116, the first contact 122a, the second contact 122b, and the bit lines formed subsequently are shown.
Then, a first bit line 124a connected to the first contact 122a and a second bit line 124b connected to the second contact 122b are formed on the dielectric layer 118 to form the resistance random access memory of the present embodiment. The formation methods of the first bit line 124a and the second bit line 124b are well known to those skilled in the art and will not be described herein. In the present embodiment, since the first contact 122a and the second contact 122b are alternately disposed, the first bit line 124a and the second bit line 124b may be disposed parallel to each other in a second direction perpendicular to the first direction.
In the resistance random access memory of the present embodiment, the second electrode 114 and the third electrode 116 are electrically connected to different bit lines, so that the first memory cell 10 and the second memory cell 20 can be operated independently. In addition, since the adjacent first memory cell 10 and the adjacent second memory cell 20 are electrically connected to different bit lines, the adjacent memory cells do not affect each other during the operation.
In the present embodiment, since the second electrode 114 and the third electrode 116 are respectively overlapped with the sidewall and the top surface of the first electrode 102, conductive paths (conductive wires) can be intensively formed at the upper left corner and the upper right corner of the first electrode 102. In other words, when the memory cell of the present embodiment is operated, the formation position of the conductive path (conductive filament) can be more well controlled.
In the present embodiment, the second electrode 114 and the third electrode 116 disposed on the first electrode 102 are separated from each other by the isolation layer 106a, but the present invention is not limited thereto. In another embodiment, the isolation layer 106a may also be omitted, as will be further described below.
Fig. 3A to fig. 3B are schematic cross-sectional views illustrating a manufacturing process of a resistance random access memory according to a second embodiment of the invention. In the present embodiment, the same components as those of the first embodiment will be denoted by the same reference numerals, and a description thereof will not be given.
Referring to fig. 3A, when the patterning process of fig. 1B is performed, only the isolation layer 106B is formed, but the isolation layer 106a is not formed on the top surface of the first electrode 102. Then, a selection layer 108, a variable resistance layer 110 and an electrode material layer 112 are sequentially formed.
Referring to fig. 3B, a patterning process is performed to remove a portion of the electrode material layer 112, a portion of the variable resistance layer 110, and a portion of the selection layer 108, so as to expose a portion of the top surface of the first electrode 102. In this way, the second electrode 114 and the third electrode 116 are formed on two opposite sides of the first electrode 102. Then, an oxygen barrier layer 120 and a dielectric layer 118 are sequentially formed, and the process as described in fig. 1D is performed to form the rram of the present embodiment.
In the above embodiments, the selection layer 108 is located between the variable resistance layer 110 and the first electrode 102, that is, the selection layer is located between the variable resistance layer 110 and the lower electrode, but the invention is not limited thereto. In other embodiments, the selection layer 108 may be located between the variable resistance layer 110 and the second electrode 114 and the third electrode 116, that is, the selection layer may be located between the variable resistance layer 110 and the upper electrode. In this case, the selection layer may be formed on the variable resistance layer 110 after the variable resistance layer 110 is formed. Alternatively, in other embodiments, the selection layer may be disposed between the variable resistance layer 110 and the lower electrode and between the variable resistance layer 110 and the upper electrode. The location and formation of such selective layers are well known to those skilled in the art and will not be described in detail herein.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A resistive random access memory, comprising:
a first electrode disposed on the substrate;
a second electrode and a third electrode disposed on the first electrode, wherein the second electrode and the third electrode are spaced apart from each other and each overlap a sidewall and a top surface of the first electrode;
a variable resistance layer provided between the first electrode and the second electrode and between the first electrode and the third electrode;
a selection layer provided between the variable resistance layer and the first electrode and/or between the variable resistance layer and the second electrode and the third electrode;
a first bit line disposed on the second electrode and electrically connected to the second electrode through a first contact; and
and the second bit line is arranged on the third electrode and is electrically connected with the third electrode through a second contact.
2. The resistive random access memory according to claim 1, further comprising an isolation layer disposed on a top surface of the first electrode and between the second electrode and the third electrode.
3. The resistive random access memory according to claim 2, wherein the variable resistance layer covers the isolation layer, and the selection layer is disposed between the variable resistance layer and the isolation layer.
4. The resistive random access memory according to claim 1, further comprising a dielectric layer disposed between the second electrode and the first bit line and between the third electrode and the second bit line, and wherein the first contact and the second contact are in the dielectric layer.
5. The resistive random access memory according to claim 4, further comprising an oxygen barrier layer disposed between the dielectric layer and the variable resistance layer.
6. A method for manufacturing a resistive random access memory, comprising:
forming a first electrode on a substrate;
forming a selection layer on the first electrode;
forming a variable resistance layer on the selection layer;
forming a second electrode and a third electrode spaced apart from each other on the variable resistance layer, wherein the second electrode and the third electrode each overlap with a sidewall and a top surface of the first electrode;
forming a first contact on the second electrode;
forming a second contact on the third electrode;
forming a first bit line at the first contact; and
a second bit line is formed over the second contact.
7. The method of claim 6, further comprising forming an isolation layer on a top surface of the first electrode after forming the first electrode and before forming the selection layer.
8. The method as claimed in claim 7, wherein the method for forming the second electrode and the third electrode comprises:
forming an electrode material layer on the variable resistance layer; and
and carrying out a planarization process, and removing part of the electrode material layer until the variable resistance layer on the isolation layer is exposed.
9. The method of claim 6, further comprising forming a dielectric layer over the second and third electrodes and the first and second contacts are formed in the dielectric layer after forming the second and third electrodes and before forming the first and second contacts.
10. The method of claim 9, further comprising forming an oxygen barrier layer on the variable resistance layer after forming the second and third electrodes and before forming the dielectric layer.
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