CN113078182B

CN113078182B - Three-dimensional resistive memory device

Info

Publication number: CN113078182B
Application number: CN202010727739.8A
Authority: CN
Inventors: 韩在贤
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2020-01-03
Filing date: 2020-07-23
Publication date: 2024-08-02
Anticipated expiration: 2040-07-23
Also published as: CN113078182A

Abstract

A three-dimensional resistive memory device comprising: a vertical word line pillar, a plurality of resistive layers, a plurality of insulating layers, a gate insulating layer, and a channel layer. Vertical word line pillars are formed on a semiconductor substrate. The resistor layers are sequentially laminated on both sides of the vertical word line pillar. The insulating layers and the resistive layers are alternately laminated. The gate insulating layer is interposed between the vertical word line pillar and the resistive layer. The channel layer is disposed between the gate insulating layer and the resistive layer.

Description

Three-dimensional resistive memory device

Technical Field

Various embodiments may relate generally to a non-volatile memory device, and more particularly, to a three-dimensional resistive memory device (RESISTIVE MEMORY DEVICE).

Background

In order to achieve good performance at low cost, it may be necessary to increase the integration level of the semiconductor memory device. Since the integration of a semiconductor memory device may be an important factor in determining the price of an electronic device, it may be necessary to increase the integration.

In a two-dimensional or planar semiconductor memory device, the degree of integration of the two-dimensional or planar semiconductor memory device may be determined according to the occupied area of a unit memory cell, so that the degree of integration may be greatly affected by the level of technology for forming a fine pattern. However, since fine patterns may be to be formed using a semiconductor manufacturing apparatus having high cost, the integration of the two-dimensional semiconductor memory device may be limited.

To overcome this limitation, a three-dimensional semiconductor memory device including memory cells arranged in three dimensions may be proposed.

Recently, the number of memory transistors in a string of nonvolatile memory devices may increase significantly, and thus the height of a three-dimensional stacked memory device may also increase significantly. And when the height of the three-dimensional stacked memory device may increase, it may be difficult to form the channel layer and the slit.

Disclosure of Invention

In an exemplary embodiment of the present disclosure, a three-dimensional resistive memory device may include: a vertical word line pillar, a plurality of resistive layers, an insulating layer, a gate insulating layer, and a channel layer. Vertical word line pillars may be formed on a semiconductor substrate. The resistive layers may be sequentially stacked on both sides of the vertical word line pillar. The insulating layers may be alternately laminated with the resistive layers. A gate insulating layer may be interposed between the vertical word line pillar and the resistive layer. The channel layer may be disposed between the gate insulating layer and the resistive layer.

In an exemplary embodiment of the present disclosure, a three-dimensional resistive memory device may include: a semiconductor substrate, a single word line pillar, a gate insulating layer, a plurality of resistive layers, a channel layer, and a plurality of bit lines. The semiconductor substrate may include a plurality of memory group regions in a row direction and a column direction. A single word line pillar may extend vertically from the upper surface of the semiconductor substrate in each memory group region. The gate insulating layer may be configured to surround sidewalls of the word line pillar. The resistive layer may be vertically stacked on both sides of the word line pillar. The channel layer may be interposed between the resistive layer and the gate insulating layer. The bit line may be electrically connected to the resistive layer.

In an exemplary embodiment of the present disclosure, a three-dimensional resistive memory device may include: memory banks arranged in a row direction and a column direction. Each memory group may include one word line, a plurality of bit lines intersecting the word line, and a plurality of memory cells connected between the word line and the bit lines. Each memory cell may include a switching element configured to be turned on in response to a voltage of a word line and a variable resistor connected in parallel with the switching element.

In an exemplary embodiment of the present disclosure, a three-dimensional resistive memory device may include: a pair of bit line structures, a plurality of word lines, and a memory cell. The bit line structure may extend in the column direction. The word lines may be spaced apart from each other by a uniform gap. The word lines may extend in a vertical direction to intersect the bit line structure. The memory cells may be arranged at the intersections between the word lines and the bit line structures. Each memory cell may include a switching element configured to turn on in response to a voltage of a word line, and a variable resistor connected in parallel with the switching element and electrically connected with the bit line structure.

According to an exemplary embodiment, the resistive layer may be stacked instead of the word line, and the word line may be vertically formed. Unlike a word line having a larger thickness to have wiring resistance, a resistance layer having a smaller thickness may have a variable resistor, so that a three-dimensional resistive memory device may have a lower height.

Drawings

The foregoing and other aspects, features, and advantages of the presently disclosed subject matter will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a perspective view illustrating a three-dimensional resistive memory device according to an exemplary embodiment;

fig. 2A and 2B are circuit diagrams illustrating a memory bank of a three-dimensional resistive memory device according to an example embodiment;

fig. 3 is a circuit diagram illustrating a unit memory cell of a three-dimensional resistive memory device according to an exemplary embodiment;

FIG. 4 is a plan view illustrating a memory bank according to an example embodiment;

Fig. 5A to 5E are cross-sectional views illustrating a method of manufacturing a three-dimensional resistive memory device according to an exemplary embodiment;

fig. 6A to 6E are perspective views illustrating a method of manufacturing a three-dimensional resistive memory device according to an exemplary embodiment;

Fig. 7 and 8 are circuit diagrams illustrating a programming operation of a three-dimensional resistive memory device according to an exemplary embodiment;

FIG. 9 is a diagram illustrating an example according to an embodiment three-dimensional of the illustrative embodiments a circuit diagram of a read operation of the resistive memory device;

FIG. 10A is a plan view illustrating a three-dimensional resistive memory device having word lines with a first width according to an example embodiment;

FIG. 10B is a plan view illustrating a three-dimensional resistive memory device having word lines with a second width according to an example embodiment;

Fig. 11 is a graph illustrating current-voltage of the three-dimensional resistive memory device in fig. 10A and 10B.

FIG. 12 is a diagram illustrating a data processing system including a Solid State Drive (SSD) according to an exemplary embodiment;

FIG. 13 is a diagram illustrating a data processing system including a memory system in accordance with an illustrative embodiment;

FIG. 14 is a diagram illustrating a data processing system including a memory system in accordance with an illustrative embodiment;

FIG. 15 is a diagram illustrating a network system including a memory system in accordance with an example embodiment; and

Fig. 16 is a block diagram illustrating a memory storage in a memory system according to an exemplary embodiment.

Detailed Description

Various embodiments of the present teachings will be described in more detail with reference to the accompanying drawings. The drawings are schematic representations of various embodiments (and intermediate structures). As such, variations in the configuration and shape of the illustrations may be expected due to, for example, manufacturing techniques and/or tolerances. Therefore, the described embodiments should not be construed as limited to the particular configurations and shapes illustrated herein but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present teachings, as defined in the appended claims.

The present teachings are described herein with reference to cross-sectional illustrations and/or plan illustrations of idealized embodiments of the present teachings. However, embodiments of the present teachings should not be construed as limiting the inventive concept. Although a few embodiments of the present teachings will be shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the present teachings.

Fig. 1 is a perspective view illustrating a three-dimensional resistive memory device according to an exemplary embodiment.

Referring to fig. 1, a three-dimensional resistive memory device 10 of an exemplary embodiment may include a memory cell array CA and a control circuit block CB. For example, the memory cell array CA may be stacked on the control circuit block CB.

The memory cell array CA may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. The memory cell arrays CA may be classified into memory groups GR11 to GRmn based on word lines. Each of the memory groups GR11 to GRmn may be electrically connected to a control circuit block CB. The memory groups GR 11-GRmn can be operated independently. As used herein, the waves "-" denote the scope of the assembly. For example, "GR 11-GRmn" represents the memory groups GR11, GR12, … …, GRmn-1, and GRmn shown in FIG. 1.

Although not described in detail in the drawings, the control circuit block CB may include control logic configured to drive the memory groups GR11 to GRmn, a voltage generating circuit, a read/write circuit, and a decoding circuit.

Fig. 2A and 2B are circuit diagrams illustrating a memory group of a three-dimensional resistive memory device according to an exemplary embodiment. For convenience of explanation, the first memory group GR11 and the second memory group GR12 among the memory groups GR11 to GRmn may be shown.

Referring to fig. 2A and 2B, each of the first and second memory groups GR11 and GR12 may include word lines WL1 and WL2, a plurality of bit lines BL1 to BLm, and a plurality of memory cells m1_1 to m1_m and m2_1 to m2_m

Word lines WL1 and WL2 may be assigned to memory groups GR11 and GR12, respectively. The word lines WL1 and WL2 may extend in the z-direction of fig. 2A and 2B (i.e., a direction substantially perpendicular to the surface of the semiconductor substrate). Each of the word lines WL1 and WL2 may be connected to a decoding circuit DC of the control circuit block CB to be selectively enabled. The bit lines BL1 to BLm may be stacked in units of two bit lines. The memory cells m1_1 to m1_m and m2_1 to m2_m may be stacked in the z direction and connected to word lines in the memory groups GR11 and GR12. For example, the memory cells m1_1 to m1_m and m2_1 to m2_m in any one of the memory groups GR11 and GR12 may form pairs of memory cells based on word lines. Pairs of memory cells m1_1 to m1_m and m2_1 to m2_m may be stacked.

For example, in the first memory group GR11, the first memory cell m1_1 connected to the first bit line BL1 and the second memory cell m1_2 connected to the second bit line BL2 may be connected to the first word line WL1, respectively. The first memory cell m1_1 and the second memory cell m1_2 may be connected to each other to form a first stack 1 ^st _st.

In the first memory group GR11, the third memory cell m1_3 connected to the third bit line BL3 and the fourth memory cell m1_4 connected to the fourth bit line BL4 may be connected to the first word line WL1, respectively. The third memory cell m1_3 and the fourth memory cell m1_4 may be connected to each other to form the second stack ^nd _st on the first stack 1 ^st _st. The number of stacks may be set in consideration of the number of memory cells in the above manner.

In an exemplary embodiment, the memory cells m1_1 to m1_m and m2_1 to m2_m in each of the memory groups GR11 and GR12 may be commonly connected to the word lines WL1 and WL2, respectively. Thus, the memory groups GR11 and GR12 of the exemplary embodiment can be understood as vertical pages (VERTICAL PAGE).

Further, a pair of memory cells constituting a stack in each of the memory groups GR11 and GR12 may be connected to different bit lines BL1 to BLm, respectively. Bit lines BL 1-BLm may intersect word lines WL1 and WL 2. Bit lines BL 1-BLm may be connected to stacked memory cells Mc1_1-Mc1_m and Mc2_1-Mc2_m. For example, the bit lines BL 1-BLm may extend in the y-direction (i.e., column direction).

For example, the first bit line BL1 and the second bit line BL2 may extend in parallel on the first stack 1 ^st _st. The first bit line BL1 and the second bit line BL2 may be connected to the first memory cell mc1_1 and the second memory cell mc1_2, respectively. The third bit line BL3 and the fourth bit line BL4 may extend in parallel on the second stack ^nd _st. The third bit line BL3 and the fourth bit line BL4 may be connected to the third memory cell mc1_3 and the fourth memory cell mc1_4, respectively.

Each of the bit lines BL1 to BLm may be electrically connected to memory cells located on the same column and the same layer (i.e., the same stack). For example, the first memory cells m1_1 to mcn_1 of the memory groups GR11 to GR1n on the first column may be commonly connected to the first bit line BL1.

Fig. 3 is a circuit diagram illustrating a unit memory cell of a three-dimensional resistive memory cell according to an exemplary embodiment.

Referring to fig. 3, the memory cell MC may include a switching element SW and a variable resistor VR.

For example, the switching element SW may include a vertical transistor having a vertical channel. For example, the switching element SW may include a TFT (thin film transistor). The switching element SW may be turned on according to a voltage level of the word line WL to switch a voltage of the bit line BL.

The variable resistor VR may be connected in parallel with the switching element SW. For example, the variable resistor VR may be connected in parallel between the source and drain of the switching element SW, i.e., in parallel with the channel layer of the switching element SW. The variable resistor VR may be turned on when a voltage difference between one terminal of the variable resistor VR and the other terminal of the variable resistor VR may be a threshold voltage or higher. When the variable resistor is on, the resistance of the variable resistor VR is lower than the off resistance of the switching element SW and higher than the on resistance of the switching element SW.

The switching element SW and the variable resistor VR may be commonly connected between the bit line BL and ground (or source).

When a write voltage (or write current) is applied to the bit line BL and the word line WL is enabled, the switching element SW may be turned on by a voltage difference between a voltage level of the word line WL and a voltage level of the bit line BL. Accordingly, a write voltage (or write current) applied to the bit line BL can be transferred to the memory cells on the next group through the channel layer of the switching element SW.

The switching element SW may be turned off when the word line WL is disabled with a write voltage (or write current) applied to the bit line BL. However, by the threshold voltage of the variable resistor VR, a voltage difference may be generated between one terminal of the variable resistor VR and the other terminal of the variable resistor VR. Thus, the variable resistor VR may be turned on. And then, a write voltage (or write current) may be supplied to the turned-on variable resistor VR. The resistance of the on variable resistor VR may be changed according to a write voltage (or write current) to be lower than the off resistance of the switching element SW.

The voltage or current applied to the bit line BL can be transferred to the memory cells on the next group through the variable resistor VR connected in parallel with the switching element SW without passing through the switching element SW. During the transfer of current or voltage, data may be stored (or written or programmed) in the variable resistor VR.

Fig. 4 is a plan view illustrating a memory bank according to an exemplary embodiment. For example, fig. 4 shows one stack of memory banks.

Referring to fig. 4, the memory groups GR11 to GR12 may be arranged in a matrix shape.

Word lines WL11 to WL23 may be arranged in each of the memory groups GR11 to GR 23.

The resistive layer 120 may be disposed at both ends of the word lines WL11 to WL23 in the x-direction. Each of the resistive layers 120 may extend in the y-direction (column direction) without breaking. For example, the resistive layer 120 may correspond to the variable resistor VR of fig. 2A and 2B.

The gate insulating layer 140 and the channel layer 130 may be interposed between the word lines WL11 to WL23 and the resistive layer 120. For example, the gate insulating layer 140 may be formed between the word lines WL11 to WL23 and the channel layer 130. The channel layer 130 may be formed between the gate insulating layer 140 and the resistive layer 120.

Similar to the resistive layer 120, the channel layer 130 may extend in the y-direction (column direction) without breaking.

The word lines WL11 to WL23 on the same column may be electrically isolated from each other by the interlayer insulating layer 135.

The resistive layer 120 and the channel layer 130 may be electrically connected to the bit lines bls_even and bls_odd. For example, the resistive layer 120 and the channel layer 130 located at the left side (or one side) of the word lines WL11 to WL23 may be connected to one of the even bit lines bls_even. The resistive layer 120 and the channel layer 130 located at the right side (or the other side) of the word lines WL11 to WL23 may be connected to one of the odd bit lines bls_odd.

In an exemplary embodiment, the memory cells MC, which may be located in the same column and connected to the same bit line, may correspond to memory strings of a general NAND flash memory.

For example, when it is possible to perform a memory operation of a selected memory cell among memory cells MC of a memory string, a word line connected to the selected memory cell may be disabled, and the remaining word lines may be enabled. A write voltage and/or write current for a memory operation may then be applied to the bit line connected to the selected memory cell. Thus, the switching elements of the remaining memory cells other than the selected memory cell may be turned on, and only the switching elements of the selected memory cell may be turned off.

Accordingly, a write voltage (and/or write current) of the bit line may be transmitted to the switching element SW of the unselected memory cell and the resistive layer 120 (i.e., the variable resistor) of the selected memory cell, so that a memory operation may be performed on the resistive layer 120 (i.e., the variable resistor) of the selected memory cell.

Fig. 5A to 5E are sectional views illustrating a method of manufacturing a three-dimensional resistive memory device according to an exemplary embodiment, and fig. 6A to 6E are perspective views illustrating a method of manufacturing a three-dimensional resistive memory device according to an exemplary embodiment. For example, fig. 5A to 5E and 6A to 6E show two adjacent memory banks located in the same row. Further, fig. 5A to 5E are sectional views taken along the line V-V' in fig. 4.

Referring to fig. 5A and 6A, a semiconductor substrate 100 having a device layer may be provided. For example, the semiconductor substrate 100 may include an impurity region. The device layer may include control circuitry for driving the memory device, such as a layer in which transistors including decoding circuitry may be integrated.

The insulating layers 110 and the resistive layers 120 may be alternately stacked on the semiconductor substrate 100 to form a stacked structure S. For example, the insulating layer 110 may include a silicon oxide layer, a silicon nitride layer, etc., but is not limited to a specific insulating material. The resistive layer 120 may have a resistance value that varies according to various electrical conditions. The resistive layer 120 may correspond to the variable resistor VR in fig. 3. The resistive layer 120 of the exemplary embodiment may include a chalcogenide (chalcogenide compound), a transition metal compound, a ferroelectric, a ferromagnetic substance, etc., but is not limited to a specific material. For example, the resistive layer 120 may include a metal oxide. The metal oxide may include transition metal oxides (e.g., nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, tungsten oxide, cobalt oxide, etc.), perovskite materials (e.g., STO (SrTiO), PCMO (PrCaMnO)), etc.

Further, the resistive layer 120 may include a phase change material. The phase change material may include a chalcogenide material (chalcogenide material), such as Ge-Sb-Te (GST). The resistive layer 120 may be stabilized to either a crystalline or amorphous state by heating to exhibit switching characteristics between different resistive states.

The resistive layer 120 may include a structure having a tunneling barrier layer (tunnel barrier layer) interposed between two magnetic layers. The magnetic layer may include NiFeCo, coFe, and the like. The tunneling barrier layer may include Al ₂O₃ or the like. The resistive layer 120 may have switching characteristics between different resistive states depending on the magnetization direction of the magnetic layer. For example, when the magnetization directions of the two magnetic layers are parallel to each other, the resistive layer 120 may have a low resistance state. In contrast, when the magnetization directions of the two magnetic layers are antiparallel (anti-parallel) to each other, the resistive layer 120 may have a high resistance state.

The resistive layer 120 may have a thickness for performing a resistance change operation. For example, the resistive layer 120 may have a minimum thickness for performing a resistance change operation. The insulating layer 110 may have a thickness for electrically isolating the resistive layer 120.

The height of the stacked structure S may be lower than that of a NAND flash memory structure having substantially the same number of layers as the stacked structure S, which may include stacked word lines.

As described above, the NAND flash memory may include stacked word lines. To provide signal transfer characteristics (i.e., wiring resistance) to the word line, the word line may have a large thickness. Therefore, the height of the NAND flash memory structure may be limited without reducing the number of stacks of word lines.

In contrast, the resistive layer 120 may have a minimum thickness (e.g., about several nanometers) to perform a resistance change operation differently from the word line, so that the thickness of the resistive layer 120 may be less than the thickness of the word line.

As a result, when the number of stacked layers of the stacked structure S and the NAND flash memory may be the same, the height of the stacked structure S may be lower than that of the NAND flash memory.

In an exemplary embodiment, the insulating layers 110 and the resistive layers 120 may be alternately stacked on the semiconductor substrate 110 to form a stacked structure S. The insulating layer 110 may be laminated on the uppermost surface of the laminated structure S. Alternatively, when the insulating layer is formed on the device layer, the resistive layer 120 and the insulating layer 110 may be alternately stacked to form a stacked structure.

Referring to fig. 4, 5B, and 6B, the stacked structure S may be etched to form a first hole H1. The first hole H1 may have a linear shape configured to expose the semiconductor substrate 110. The first hole H1 may extend in the column direction of fig. 4. The first hole H1 may be formed by anisotropically etching the insulating layer 110 and the resistive layer 120. In the etching process of forming the first hole H1, an etchant that over-etches the resistive layer 120 compared to the insulating layer 110 may be used. Accordingly, the resistive layer 120 may be over-etched as compared to the insulating layer 110 to form a channel groove Hc in a region where the resistive layer 120 may be formed.

In an exemplary embodiment, after the first hole H1 is formed, the resistive layer 120 exposed through the first hole H1 may be additionally etched to form a channel groove Hc at a region where the resistive layer 120 may be formed.

Referring to fig. 5C and 6C, a channel layer 130 may be formed in the channel groove Hc. The channel layer 130 may include at least one of a doped polysilicon layer, a silicon oxide layer, a carbon nanotube layer, a graphene layer, a transition metal dichalcogenide monolayer (transition metal dichalcogenide monolayer), and a MoS ₂ layer. For example, the channel layer 130 may include a material (e.g., an amorphous silicon layer) that serves as a channel of the TFT. In addition, the channel layer 130 may include a material (i.e., IGZO) having indium, gallium, zinc, and oxygen, which is a channel of the oxide TFT. For example, the channel layer 130 may have a uniform thickness. The channel layer 130 may be formed on a surface of the stacked structure having the first hole H1. The uniform thickness of the channel layer 130 may correspond to the buried channel groove Hc. The channel layer 130 may be anisotropically etched such that the channel layer 130 fills the channel trench Hc. Accordingly, the channel layer 130 may be configured to contact each of the resistive layers 120 of the stacked structure S. The channel layer 130 may extend in the y-direction.

Referring to fig. 5D and 6D, the first hole H1 may be filled with the interlayer insulating layer 135. The interlayer insulating layer 135 in the first hole H1 may be etched to form a plurality of second holes H2. The second hole H2 may have a pattern shape.

A gate insulating layer 140 may be formed on an inner surface of the second hole H2. For example, the gate insulating layer 140 may be anisotropically processed to expose the semiconductor substrate 100 on the bottom surface of the second hole H2.

In an exemplary embodiment, the gate insulating layer 140 may include a silicon oxide layer, but is not limited to a specific insulating material.

Referring to fig. 5E and 6E, the second hole H2 may be filled with a conductive layer to form the word line pillar 150. The conductive layer of the word line pillars 150 may include a metal layer (e.g., a tungsten layer with good gap-fill characteristics). The word line pillars 150 may correspond to word lines located in one of the memory banks in fig. 2A and 2B and fig. 4.

Although not shown in the drawings, the word line pillars 150 may be connected to control circuit blocks in the device layer of the semiconductor substrate 100 to receive an enable voltage. In addition, the wordline pillars 150 may receive an enable voltage through additional contact lines. The word line WL may have an upper surface configured to contact the voltage line.

Fig. 7 and 8 are circuit diagrams illustrating a programming operation of a three-dimensional resistive memory device according to an exemplary embodiment. Fig. 7 is an equivalent circuit diagram showing a memory cell in a page cell connected to one word line. Fig. 8 is an equivalent circuit diagram showing a memory cell in a string unit connected to a pair of bit lines.

For ease of explanation, one page may include 8 memory cells, and one string may include 5 memory cells.

In addition, a memory operation (i.e., a program operation, a read operation, and an erase operation of the memory cell) for the memory cell m2_1 between the second word line WL2 and the first bit line BL1 may be illustrated.

Referring to fig. 7 and 8, an enable voltage may be applied to the remaining word lines WL1 and WL3 to WL5 (hereinafter referred to as unselected word lines) in addition to the second word line WL2 (hereinafter referred to as selected word line) connected to the memory cell MC2_1 to be selected.

A write (or program) voltage and a write current Ip may be applied to a first bit line BL1 (hereinafter referred to as a selected bit line) connected to the memory cell MC2_1 to be selected.

The write voltage and the write current Ip may have levels for changing the variable resistor VR (i.e., the characteristics of the resistive layer 120).

An enable voltage is applied to unselected word lines WL1 and WL 3-WL 5. The switching elements SW of the memory cells connected to the unselected word lines WL1 and WL3 to WL5 may be turned on by an enable voltage. For example, the enable voltage may have a level not less than a level of the threshold voltage of the switching element in the memory cell mc2_1. The memory cells m2_1 to m2_8 connected to the selected word line WL2 may be turned off.

Accordingly, the write current Ip transferred through the selected bit line BL1 can flow through the channel layers of the switching elements SW of the memory cells mc5_1, mc4_1, and mc3_1 connected between the selected bit line BL1 and the unselected word lines WL3 to WL 5. In contrast, since the selected word line WL2 is disabled, the switching element SW of the memory cell mc2_1 connected between the selected bit line BL1 and the selected word line WL2 may be turned off. At this time, one terminal of the variable resistor VR connected to the memory cell m3_1 has a level of the write voltage, and the other terminal of the variable resistor VR connected to the memory cell m1_1 has a level of the ground voltage. Thus, the variable resistor VR is turned on by a voltage difference between one terminal thereof and the other terminal thereof.

The variable resistor VR that is turned on includes a resistance lower than the off resistance of the switching element SW. However, the resistance of the on variable resistor VR is higher than the on resistance of the switching element SW. Since the switching element SW of the memory cell mc2_1 has an off resistance, the write voltage and/or the write current Ip may flow through the on variable resistor VR having a resistance lower than the off resistance of the switching element SW. In the above-described process, the resistance state of the variable resistor VR may be changed by the write voltage and/or the write current Ip to perform a write (program) operation. Thus, the data is stored in the variable resistor VR. The resistance state (or level) of the variable resistor VR can be changed by a write voltage and a write current application method.

In an exemplary embodiment, the write current may flow through a variable resistor connected in parallel to the disabled switching element, and the variable resistor is written (programmed). The write voltage and write current may change the characteristics of the variable resistor (i.e., the resistive layer) to form a filament (fileent) connected in parallel with the switching element.

A current having an opposite polarity to the write current may be applied to the selected memory cell m2_1 to erase the data in the memory cell m2_1.

Fig. 9 is a circuit diagram illustrating a read operation of a three-dimensional resistive memory device according to an exemplary embodiment. A read operation to read data from the programmed memory cell m2_1 may be shown.

Referring to fig. 9, a second word line WL2 (hereinafter referred to as a selected word line) connected to the memory cell mc2_1 to be read may be disabled. An enable voltage may be applied to the remaining word lines WL1 and WL3 to WL5 (hereinafter referred to as unselected word lines). A read voltage and a read current Ir may be applied to a selected bit line BL1 connected to the memory cell mc2_1 to be read. The read current Ir does not change the resistance of the variable resistor VR.

The switching elements SW of the memory cells connected to the unselected word lines WL1 and WL3 to WL5 may be turned on by an enable voltage. However, the memory cells m2_1 to m2_8 connected to the selected word line WL2 may be turned off.

Similar to the write operation, the read voltage and the read current Ir are transmitted through the switching elements SW of the memory cells mc5_1, mc4_1, and mc3_1 connected between the selected bit line BL1 and the unselected word lines WL3 to WL 5. Meanwhile, since the switching element SW of the memory cell m2_1 connected between the selected bit line BL1 and the selected word line WL2 may be turned off, the read current Ir may flow through the variable resistor VR having a resistance lower than the turn-off resistance of the switching element SW.

The current level of the read current Ir may change when the read current Ir flows through the programmed (or written) variable resistor VR. The read current Ir' flowing through the programmed (or written) variable resistor VR may be transferred to the sense amplifier of the control circuit block. The sense amplifier may determine the resistance state of the variable resistor VR from the read current Ir'.

Fig. 10A is a plan view illustrating a three-dimensional resistive memory device having a word line with a first width according to an exemplary embodiment, fig. 10B is a plan view illustrating a three-dimensional resistive memory device having a word line with a second width according to an exemplary embodiment, and fig. 11 is a graph illustrating current-voltage of the three-dimensional resistive memory device in fig. 10A and 10B.

Referring to fig. 10A and 10B, the threshold voltage Δv for turning on the variable resistor VR can be changed by the widths W1 and W2 of the word lines WL1 to WL 3.

When the widths W1 and W2 of the word lines WL1 to WL3 can be increased, the length of the channel layer 130 in the switching element SW can also be extended. Further, the length of the resistive layer 120 (i.e., the length of the variable resistor VR) connected in parallel to the channel layer 130 of the switching element SW may also be lengthened.

As shown in fig. 11, when the length of the variable resistor VR can be changed, the threshold voltage Δv can also be changed. That is, the threshold voltage Δv of the variable resistor VR may increase in proportion to the length of the variable resistor VR. In fig. 11, case 1 may represent the threshold voltage Δv1 of the variable resistor VR in fig. 10A, and case 2 may represent the threshold voltage Δv2 of the variable resistor VR in fig. 10B.

As a result, the threshold voltage Δv of the variable resistor VR can be determined by controlling the widths W1 and W2 of the word lines WL1 to WL 3. Further, the widths W1 and W2 of the word lines WL1 to WL3 may be determined in consideration of the threshold voltage Δv.

According to an exemplary embodiment, a resistive layer instead of a word line may be stacked. The word lines may be formed vertically. Unlike a word line having a larger thickness to have wiring resistance, a resistance layer having a smaller thickness may have a variable resistor, so that a three-dimensional resistive memory device may have a lower height.

Fig. 12 is a diagram illustrating a data processing system including a Solid State Drive (SSD) according to an example embodiment.

Referring to fig. 12, a data processing system 1000 may include a host device 1100 and a Solid State Drive (SSD) 1200.

SSD 1200 can include controller 1210, buffer memory device 1220, storage memories 1231-123 n, power source 1240, signal connector 1250, and power source connector 1260.

The controller 1210 may be configured to control the operation of the SSD 1200. The controller 1210 may include a host interface unit 1211, a control unit 1212, a random access memory 1213, an Error Correction Code (ECC) unit 1214, and a memory interface unit 1215.

The host interface unit 1211 may transmit/receive a signal SGL to/from the host apparatus 1100 through the signal connector 1250. The signal SGL may include commands, addresses, data, etc. The host interface unit 1211 may be configured to interface the host device 1100 and the SSD 1200 with each other according to a protocol of the host device. For example, the host interface unit 1211 may interface with the host device 1100 through any of standard interface protocols, such as Advanced Technology Attachment (ATA), serial ATA (SATA), external SATA (E-SATA), small computer system small interface (SCSI), serial Attached SCSI (SAS), peripheral Component Interconnect (PCI), PCI express (PCI-E), IEEE1394, universal Serial Bus (USB), secure Digital (SD) card, multimedia card (MMC), embedded multimedia card (eMMC), compact Flash (CF) card, and the like.

The control unit 1212 may be configured to analyze and process a signal SGL input from the host device 1100. The control unit 1212 may be configured to control the background function blocks according to firmware or software for driving the SSD 1200. The random access memory 1213 may be used as an operation memory for driving firmware or software.

The ECC unit 1214 can be configured to generate parity data for the data transferred to the memory memories 1231-123 n. The generated parity data and data may be stored in the memory stores 1231 to 123 n. The ECC unit 1214 may detect errors of the data read from the storage memories 1231 to 123n based on the parity data. When the detected error may be within a correctable range, the ECC unit 1214 may correct the detected error.

The memory interface unit 1215 may provide control signals such as commands, addresses, and the like to the memory memories 1231 to 123n according to the control of the control unit 1212. The memory interface unit 1215 may transmit data to and receive data from the memory memories 1231 to 123n according to the control of the control unit 1212. For example, the memory interface unit 1215 may provide data stored in the buffer memory device 1220 to the storage memories 1231 to 123n, or provide data read from the storage memories 1231 to 123n to the buffer memory device 1220.

The buffer memory device 1220 may be configured to temporarily store data to be stored in the memory stores 1231 to 123n. Further, the buffer memory device 1220 may be configured to temporarily store data read from the storage memories 1231 to 123n. The data temporarily stored in the buffer memory device 1220 may be transferred to the host device 1100 or the storage memories 1231 to 123n according to the control of the controller 1210.

The storage memories 1231 to 123n may be used as storage media of the SSD 1200. Each of the storage memories 1231 to 123n may be connected to the controller 1210 through a plurality of channels CH1 to CHn. One channel may be connected to at least one memory storage. The at least one memory storage may be connected to the same signal bus and the same data bus.

The power source 1240 may be configured to provide power PWR input through the power connector 1260 to the background of the SSD 1200. The power source 1240 may include an auxiliary power supply 1241. When a sudden power down may occur, the auxiliary power supply 1241 may supply power PWR to normally stop the SSD 1200. The auxiliary power supply 1241 may include a bulk capacitor.

The signal connector 1250 may include various connectors according to the type of interface between the host device 1100 and the SSD 1200.

The power connector 1260 may include various connectors according to the power type of the host device 1100.

FIG. 13 is a diagram illustrating a data processing system including a memory system in accordance with an illustrative embodiment.

Referring to fig. 13, a data processing system 2000 may include a host device 2100 and a memory system 2200.

The host device 2100 may include a board such as a Printed Circuit Board (PCB). Although not shown in the drawings, the host apparatus 2100 may include a background function block for performing the functions of the host apparatus 2100.

The host device 2100 may include connection terminals 2110, such as sockets, slots, connectors, and the like. The memory system 2200 may be mounted on the connection terminal 2110.

The memory system 2200 may include a substrate such as a PCB. Memory system 2200 can be referred to as a memory module or a memory card. Memory system 2200 may include a controller 2210, a buffer memory device 2220, storage memories 2231-2232, such as a non-volatile memory device, a Power Management Integrated Circuit (PMIC) 2240, and a connection terminal 2250.

The controller 2210 may be configured to control the operation of the memory system 2200. The controller 2210 may have substantially the same configuration as the controller 1210 in fig. 12.

The buffer memory device 2220 can be configured to temporarily store data to be stored in the memory stores 2231-2232. Further, the buffer memory device 2220 may be configured to temporarily store data read from the storage memories 2231 to 2232. The data temporarily stored in the buffer memory device 2220 can be transferred to the host device 2100 or the storage memories 2231 to 2232 according to the control of the controller 2210.

The storage memories 2231-2232 may be used as storage media for the memory system 2200.

The PMIC 2240 may provide power input through the connection terminal 2250 to the background of the memory system 2200. The PMIC 2240 may be configured to manage power of the memory system 2200 according to control of the controller 2210.

The connection terminal 2250 may be connected to the connection terminal 2110 of the host device 2100. Signals (e.g., commands, addresses, data, etc.) and power can be transferred between the host device 2100 and the memory system 2200 through the connection terminals 2250. The connection terminal 2250 may have various configurations according to the type of interface between the host device 2100 and the memory system 2200. Connection terminals 2250 may be located on either side of memory system 2200.

FIG. 14 is a diagram illustrating a data processing system including a memory system in accordance with an illustrative embodiment.

Referring to FIG. 14, data processing system 3000 may include a host device 3100 and a memory system 3200.

Host device 3100 can include a board such as a Printed Circuit Board (PCB). Although not shown in the drawings, the host device 3100 may include a background functional block for performing the functions of the host device 3100.

The memory system 3200 may have a surface-mount type (surface-mount type) package. Memory system 3200 may be mounted on host device 3100 by solder balls 3250. Memory system 3200 may include a controller 3210, a buffer memory device 3220, and a storage memory 3230.

The controller 3210 may be configured to control the operation of the memory system 3200. The controller 3210 may have substantially the same configuration as the controller 1210 in fig. 12.

The buffer memory device 3220 may be configured to temporarily store data to be stored in the memory storage 3230. Further, the buffer memory device 3220 may be configured to temporarily store data read from the storage memory 3230. Data temporarily stored in buffer memory device 3220 may be transferred to host device 3100 or storage memory 3230 according to the control of controller 3210.

The storage memory 3230 may be used as a storage medium for the memory system 3200.

Fig. 15 is a diagram illustrating a network system including a memory system according to an exemplary embodiment.

Referring to fig. 15, a network system 4000 may include a server system 4300 and a plurality of client systems 4410 to 4430 connected to each other through a network 4500.

The server system 4300 may be configured to provide data services in response to requests by the client systems 4410-4430. For example, the server system 4300 may store data provided from the client systems 4410 through 4430. Alternatively, the server system 4300 may provide data to the client systems 4410 through 4430.

The server system 4300 may include a host device 4100 and a memory system 4200.

Referring to fig. 16, the nonvolatile memory device 300 may include a memory cell array 310, a row decoder 320, a data read/write block 330, a column decoder 340, a voltage generator 350, and control logic 360.

The memory cell array 310 may include memory cells MC arranged at intersections between word lines WL1 to WLm and bit lines BL1 to BLn.

The row decoder 320 may be connected to the memory cell array 310 through word lines WL1 to WLm. The row decoder 320 may operate according to the control of the control logic 360. The row decoder 320 may be configured to decode an address supplied from an external device. The row decoder 320 may select and drive the word lines WL1 to WLm based on the decoding result. For example, row decoder 320 may provide word line voltages provided by voltage generator 350 to word lines WL 1-WLm.

The data read/write block 330 may be connected to the memory cell array 310 through bit lines BL1 to BLn. The data read/write block 330 may include read/write blocks RW1 to RWn corresponding to the bit lines BL1 to BLn. The data read/write block 330 may operate according to the control of the control logic 360. Depending on the mode of operation, the data read/write block 330 may operate as a write driver or a sense amplifier. For example, the data read/write block 330 may operate as a write driver configured to store data provided from an external device in the memory cell array 310. Alternatively, the data read/write block 330 may operate as a sense amplifier configured to read data from the memory cell array 310.

Column decoder 340 may operate according to the control of control logic 360. The row decoder 320 may be configured to decode an address supplied from an external device. Based on the decoding result, the column decoder 340 may connect the read/write blocks RW1 to RWn of the data read/write block 330 corresponding to the bit lines BL1 to BLn to a data input/output line or a data input/output buffer.

The voltage generator 350 may be configured to generate a voltage for background operation of the nonvolatile memory device 300. The voltage generated by the voltage generator 350 may be applied to the memory cells of the memory cell array 310. For example, a program voltage generated in a program operation may be applied to a word line of a memory cell that may perform the program operation. Alternatively, the erase voltage generated in the erase operation may be applied to the well region of the memory cell in which the erase operation may be performed. In addition, a read voltage generated in a read operation may be applied to a word line of a memory cell that may perform the read operation.

The control logic 360 may be configured to control the operation of the nonvolatile memory apparatus 300 based on a control signal provided from an external device. For example, the control logic 360 may control read, write, and erase operations of the nonvolatile memory device 300.

The above-described embodiments of the present teachings are intended to illustrate, not limit, the present teachings. Various alternatives and equivalents are possible. The present teachings are not limited by the embodiments described herein. Nor is the present teachings limited to any particular type of semiconductor device. Other additions, deletions, or modifications based on the disclosure are possible and intended to fall within the scope of the appended claims.

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2020-0000715, filed on 1 month 3 in 2020, to the korean intellectual property office, the entire contents of which are incorporated herein by reference.

Claims

1. A resistive memory device, the resistive memory device comprising:

a vertical word line pillar formed on a semiconductor substrate;

A plurality of resistive layers stacked on both sides of the vertical word line pillar;

a gate insulating layer interposed between the vertical word line pillar and the resistive layer;

A plurality of insulating layers alternately laminated with the plurality of resistive layers for electrically isolating the laminated resistive layers; and

A plurality of channel layers interposed between the gate insulating layer and the plurality of resistive layers and electrically isolated from each other by the plurality of insulating layers.

2. The resistive memory device according to claim 1, wherein the resistive layer comprises one of a chalcogenide, a transition metal compound, a ferroelectric, a ferromagnetic, and a metal oxide.

3. The resistive memory device of claim 1, wherein the channel layer comprises at least one of a doped polysilicon layer, a silicon oxide layer, a carbon nanotube layer, a graphene layer, a transition metal dichalcogenide monolayer TMDC, a MoS ₂ layer, an amorphous silicon layer, and an indium gallium zinc oxide IGZO layer.

4. The resistive memory device of claim 1, further comprising a plurality of bit lines connected to the channel layer and adjacent resistive layers.

5. A resistive memory device, the resistive memory device comprising:

A semiconductor substrate having a plurality of memory group regions in a row direction and a column direction;

A word line pillar formed vertically on a surface of the semiconductor substrate in each of the memory group regions;

A gate insulating layer configured to surround sidewalls of the word line pillars;

a plurality of resistive layers stacked on both sides of the word line pillar in a direction perpendicular to a surface of the semiconductor substrate;

a channel layer interposed between the gate insulating layer and the resistive layer; and

A plurality of bit lines connected to the resistive layers, respectively,

Wherein each bit line of the plurality of bit lines is not electrically connected to any other bit line of the plurality of bit lines.

6. The resistive memory device of claim 5, wherein the word line pillars are electrically isolated from word line pillars in adjacent memory bank regions, and the resistive layer and the channel layer adjacent to the resistive layer on the same column and layer extend in the column direction without breaking.

7. The resistive memory device according to claim 5, wherein the resistive layer has a resistance value higher than a resistance value of the channel layer when a selection voltage is applied to the word line pillar, and has a resistance value lower than the resistance value of the channel layer when the selection voltage is not applied to the word line pillar.

8. The resistive memory device according to claim 5, wherein the resistive layer comprises one of a chalcogenide, a transition metal compound, a ferroelectric, a ferromagnetic, and a metal oxide.

9. The resistive memory device of claim 5, wherein the channel layer comprises at least one of a doped polysilicon layer, a silicon oxide layer, a carbon nanotube layer, a graphene layer, a transition metal dichalcogenide monolayer TMDC, a MoS ₂ layer, an amorphous silicon layer, and an indium gallium zinc oxide IGZO layer.

10. A resistive memory device, the resistive memory device comprising:

A plurality of memory groups arranged in a row direction and a column direction, each of the memory groups including one word line, a plurality of bit lines intersecting the word line, and a plurality of memory cells connected between the word line and the bit lines,

Wherein each of the memory cells comprises:

a switching element configured to be turned on in response to a voltage of the word line; and

A variable resistor connected in parallel with the switching element to be programmed by turning off the switching element,

11. The resistive memory device according to claim 10, wherein the word line extends along a first direction, and the plurality of bit lines are stacked along the first direction to intersect the word line.

12. The resistive memory device of claim 11, wherein each of the memory banks comprises a plurality of stacks stacked along the first direction, and

Wherein each of said stacks comprises:

A pair of bit lines located on both sides of the word line; and

A pair of memory cells connected between the word line and the pair of memory cells, respectively.

13. The resistive memory device of claim 10, wherein the memory banks located on the same column share the bit line.

14. The resistive memory device according to claim 10, wherein when the variable resistor is on, a resistance of the variable resistor is lower than an off resistance of the switching element and higher than an on resistance of the switching element.

15. A resistive memory device, the resistive memory device comprising:

a pair of bit line structures extending in a column direction;

A plurality of word lines spaced apart from each other by a uniform gap and extending in a vertical direction to intersect the bit line structure; and

A memory cell formed at an intersection between the word line and the bit line structure,

Wherein each of the memory cells comprises:

A variable resistor connected in parallel with the switching element and electrically connected with the bit line structure,

Wherein the bit line structure includes a plurality of bit lines stacked in the vertical direction,

The variable resistor is electrically connected to a corresponding bit line among the plurality of bit lines, and

Each bit line of the plurality of bit lines is not electrically connected to any other bit line of the plurality of bit lines.

16. The resistive memory device of claim 15, wherein the memory cell is disposed between the word line and the bit line.

17. The resistive memory device of claim 16, wherein memory cells between an unselected one of the word lines and a bit line to which current is applied are configured to perform a program operation, an erase operation, or a read operation.

18. The resistive memory device according to claim 15, wherein when the variable resistor is on, a resistance of the variable resistor is lower than an off resistance of the switching element and higher than an on resistance of the switching element.