CN113067585B

CN113067585B - Polar code decoding method and decoding device

Info

Publication number: CN113067585B
Application number: CN201911295454.5A
Authority: CN
Inventors: 牛凯; 朴瑨楠; 董超; 马亮
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-12-16
Filing date: 2019-12-16
Publication date: 2025-09-12
Anticipated expiration: 2039-12-16
Also published as: CN113067585A

Abstract

The present application provides a polar code decoding method and decoding device. Based on the SCL decoding algorithm for polar codes, the decoding end can improve the decoding performance of polar codes by rearranging the LLR sequence of the polar codes once or multiple times and calculating the decoding result based on the rearranged sequence.

Description

Decoding method and decoding device for polarization code

Technical Field

The present application relates to the field of channel coding, and more particularly, to a method and apparatus for decoding a polar code.

Background

Polarization code (polar code) is currently the only theoretical proof that the aroma limits are reached and that channel coding techniques with practical linear complexity coding capabilities are determined as the coding scheme for the control channels of the fifth generation (5G) communication system. The serial cancellation (successive cancellation, SC) decoding algorithm is the most basic decoding algorithm for polar codes. As the code length approaches infinity, very good progressive performance is achieved. But at medium and short code lengths, the performance of the SC decoding algorithm is not ideal. To improve the decoding performance of the SC decoding algorithm, a serial cancellation list (successive cancellation list, SCL) decoding algorithm is proposed. The SCL decoding algorithm introduces breadth-first search strategies into the code tree search mechanism, keeping a small list of candidate paths each time the decoding decision. And finally, selecting the path with the highest likelihood probability from the candidate path list as a decision path.

Cyclic redundancy check (cyclic redundancy check, CRC) is a channel error detection technique that has been widely used in practical digital communication systems. For polar codes, a set of candidate paths is obtained at the end of SCL decoding, which can be jointly detected and decoded with a CRC with very low complexity, and a candidate sequence that can be detected by the CRC is selected as a decoder output sequence, thereby improving the error correction capability of the decoding algorithm, and thus, a CRC-assisted SCL decoding algorithm (CRC-assisted SCL, CA-SCL) decoding algorithm is proposed.

But the decoding performance of the CA-SCL decoding algorithm is affected by the list size L. When L is smaller, the error rate is higher, and the decoding performance is still not ideal. And, according to the CA-SCL decoding algorithm, every translation is 1 bit, the decoder needs to perform a sorting operation on 2L metric values. If L is increased in order to improve decoding performance, the size of the sorting operation increases rapidly, which causes decoding delay and directly affects the throughput of the decoder. Therefore, how to reduce the error rate of decoding without increasing the decoding delay to further improve the decoding performance of the polar code remains to be solved.

Disclosure of Invention

The application provides a decoding method and device for polar codes, which can improve the decoding performance of polar codes.

The application provides a decoding method of a polarization code, which comprises the steps of performing SCL decoding on an LLR sequence of the polarization code to obtain a first estimated sequence of an information bit sequence, rearranging the LLR sequence for j times to obtain a j-th rearranged sequence of the LLR sequence if the first estimated sequence does not pass CRC, determining a second estimated sequence of the information bit sequence according to the j-th rearranged sequence, and outputting the second estimated sequence as a decoding result under the condition that the second estimated sequence passes CRC, wherein j is more than or equal to 1 and j is an integer.

In the technical scheme of the application, a decoding end firstly carries out SCL decoding on an obtained log-likelihood ratio (LLR) sequence of a polar code to obtain an estimated value of an information bit sequence, and if the estimated value cannot pass through CRC, the decoding end rearranges the LLR sequence to obtain a rearranged sequence of the LLR sequence. And the decoding end redetermines the estimated value of the information bit sequence according to the rearrangement sequence. If the estimated value of the information bit sequence determined according to the rearranged sequence can pass through the CRC, the decoding end outputs the estimated value as a decoding result. If the estimated value of the information bit sequence determined according to the rearranged sequence cannot pass through the CRC, the decoding end rearranges the LLR sequence again and redetermines the estimated value of the information bit sequence, and the method loops until the estimated value of the information bit sequence determined according to a certain rearranged sequence passes through the CRC, and then the decoding is successful.

According to the rearrangement characteristic of the polarization code, by rearranging the LLR sequences, the error rate can be reduced and the decoding performance can be improved under the condition that the list size L of the CA-SCL decoding algorithm is not increased.

Since L is not increased, decoding delay is not additionally brought, and throughput of the decoder is not affected.

It can be understood that the jth rearrangement sequence in the present embodiment refers to a sequence obtained by performing the jth rearrangement on the LLR sequence of the polar code, and may also be referred to as a sequence corresponding to the jth rearrangement.

Herein, if the j-th rearrangement of the LLR sequence is performed, it is explained that the estimated value of the information bit sequence determined from the rearranged sequence obtained from the previous (j-1) rearrangement cannot pass the CRC.

For any one rearrangement that does not pass the CRC, the corresponding rearrangement sequence may be stored until the estimated value of the information bit sequence (i.e., the second estimated sequence) determined from the rearrangement sequence obtained by the j-th rearrangement passes the CRC, and then the estimated value of the information bit sequence determined from the rearrangement sequence obtained by the j-th rearrangement is output as the decoding result.

Or after the first rearrangement, the decoding end obtains the 1 st rearrangement sequence. If the estimated value of the information bit sequence determined from the 1 st rearrangement sequence cannot pass the CRC, a second rearrangement is performed, and the 1 st rearrangement sequence is covered with the 2 nd rearrangement sequence obtained by the second rearrangement. Similarly, if the estimated value of the information bit sequence determined from the rearrangement sequence corresponding to the m-th rearrangement cannot pass the CRC, the m+1th rearrangement is performed to obtain the m+1th rearrangement sequence, and the m+1th rearrangement sequence is used to cover the m-th rearrangement sequence. And determining an estimated value of the information bit sequence according to the (m+1) th rearrangement sequence, and judging whether the estimated value can pass through the CRC or not until the estimated value of the information bit sequence determined according to the (j) th rearrangement corresponding to the rearrangement sequence can pass through the CRC. At this time, the decoding end stores a rearrangement sequence obtained by the j-th rearrangement. Wherein, the m is more than or equal to 1 and j is more than or equal to j-1, j >1, m is an integer.

Note that, herein, the numbers of the rearranged sequences are only for clearly describing the rearrangement process, and thus, the rearranged sequences corresponding to each rearrangement are sequentially numbered. For example, a rearrangement sequence corresponding to the mth rearrangement is referred to as an mth rearrangement sequence, and a rearrangement sequence corresponding to the j-th rearrangement is referred to as a j-th rearrangement sequence. However, for the decoding end, j rearrangement sequences obtained by j rearrangements in the decoding process can be all saved in the decoding process until the decoding is successful. Or the decoding end can also use the rearrangement sequence of the last time to cover the rearrangement sequence of the previous time until the decoding is successful. In this case, the decoding end may only store the latest rearrangement sequence during the decoding process. In the case where the estimated value of the information bit sequence determined from the reordered sequence obtained by the jth reordering passes the CRC, the decoding side saves the reordered sequence obtained by the jth reordering, which can be specifically described as the above procedure.

In the decoding process, the decoding end only outputs the final decoding result, but does not save the rearrangement sequence, which is not limited herein.

With reference to the first aspect, in certain implementation manners of the first aspect, the rearranging the LLR sequence j times includes:

(1) The LLR sequences are rearranged for the mth time to obtain the m rearranged sequences of the LLR sequences;

(2) Determining an nth estimated sequence of the information bit sequence according to the mth rearranged sequence;

(3) Judging whether the nth estimation sequence passes the CRC;

(4) If the nth estimated sequence does not pass the CRC, m=m+1, n=n+1 and returns to (1), wherein m is more than or equal to 1 and less than or equal to j-1, n is more than or equal to 1, j >1, and m and n are integers.

With reference to the first aspect, in certain implementation manners of the first aspect, before the j-th rearrangement of the LLR sequence, the method further includes obtaining a set of rearrangement matrices of the LLR sequence, where each rearrangement matrix in the set of rearrangement matrices is used to uniquely determine one rearrangement sequence of the LLR sequence, and the j-th rearrangement of the LLR sequence includes respectively adopting different rearrangement matrices in the set of rearrangement matrices for an mth rearrangement and a q-th rearrangement of the LLR sequence, and obtaining different rearrangement sequences, where the mth rearrangement and the q-th rearrangement refer to any two rearrangements of the LLR sequence, and q≤j, q is an integer.

With reference to the first aspect, in some implementation manners of the first aspect, the determining the second estimated sequence of the information bit sequence according to the j-th reordered sequence includes determining an intermediate sequence according to the j-th reordered sequence, and obtaining the second estimated sequence according to the intermediate sequence, a generation matrix of a polarization code, and a first reordered matrix in the set of reordered matrices, where the first reordered matrix is different from a reordered matrix used in any one of the previous (j-1) reorders.

Here, the first rearrangement matrix refers to a rearrangement matrix used for the j-th rearrangement. Wherein the first rearrangement matrix belongs to one of the set of rearrangement matrices. But since each permutation uses one permutation matrix of the set of permutation matrices, the permutation matrices used for any two permutations are different. Therefore, for any one rearrangement, the rearrangement matrix used for rearrangement is only required to be different from the rearrangement matrix used for any one previous rearrangement.

With reference to the first aspect, in certain implementation manners of the first aspect, the obtaining the second estimated sequence according to the intermediate sequence, the generating matrix of the polarization code, and the first rearrangement matrix in the set of rearrangement matrices includes calculating to obtain the second estimated sequence according to the following formula:

Wherein, the The second estimated sequence is represented by a sequence of estimates,And representing the intermediate sequence, G represents a generation matrix of the polarization code, and Q represents the first rearrangement matrix.

With reference to the first aspect, in some implementations of the first aspect, obtaining a set of rearrangement matrices of the LLR sequence includes representing an ith bit in a codeword of a polar code as a binary vector b _i, where i is equal to or less than N, where N is a code length of the polar code, determining a binary vector b _i' of a position index i' of the ith bit in the rearranged codeword according to rearrangement characteristics of the polar code, where the rearrangement characteristics of the polar code refer to specific rearrangement of bit positions of the codeword of the polar code, where the rearranged codeword is still the codeword of the polar code, and obtaining the rearranged set of matrices according to b _i and b _i'.

With reference to the first aspect, in certain implementations of the first aspect, each b _i' of the b _i and the set of b _i' satisfies the following formula:

b_i'＝1-(P·(1-b_i)+a)

Wherein P is a random reversible square matrix, and a is a constant vector.

With reference to the first aspect, in certain implementation manners of the first aspect, the obtaining the set of rearrangement matrices according to the b _i and the set of b _i' includes:

Obtaining a rearrangement function i' =p (i) corresponding to each b _i' according to b _i and each b _i' in the group of b _i';

and obtaining the set of rearrangement matrices according to the rearrangement functions i' =p (i) corresponding to the set of b _i' respectively.

In a second aspect, the present application provides a decoding device for polar codes, said decoding device having the functionality to implement the method of the first aspect or any possible implementation thereof. The functions may be implemented by hardware, or may be implemented by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

In a third aspect, the present application provides a decoder comprising one or more processors coupled with one or more memories. The one or more memories are used for storing computer programs, and the one or more processors are used for calling and running the computer programs stored in the one or more memories to execute the method in the first aspect or any possible implementation manner thereof.

Alternatively, the chip may be a channel decoder.

In a fourth aspect, the present application provides a chip comprising one or more processors. The one or more processors are configured to read and execute the computer program stored in the one or more memories to perform the method of the first aspect or any possible implementation thereof. The one or more memories are independently disposed outside the chip.

Optionally, the chip further comprises one or more memories, the one or more memories are connected with the one or more processors through circuits or wires.

Further optionally, the chip further comprises a communication interface.

In a fifth aspect, the present application also provides a decoding apparatus comprising a processor and interface circuitry for receiving computer code or instructions and transmitting to the processor for executing the computer code or instructions to perform the method of the first aspect or any possible implementation thereof.

In a sixth aspect, the application provides a computer readable storage medium having stored therein computer instructions which, when run on a computer, cause the computer to perform a method as in the first aspect or any possible implementation thereof.

In a seventh aspect, the application provides a computer program product comprising computer program code which, when run on a computer, causes the computer to perform the method of the first aspect or any possible implementation thereof.

In an eighth aspect, the application provides a communication device comprising a decoder according to the third aspect.

In a ninth aspect, the present application provides a wireless communication system comprising the communication device of the seventh aspect.

Drawings

Fig. 1 is a schematic diagram of a wireless communication system suitable for use in the present application.

Fig. 2 is a basic flow diagram of wireless communication.

Fig. 3 is an example of an SCL decoding algorithm with l=2.

Fig. 4 is a flowchart of a method 300 for decoding a polarization code according to the present application.

Fig. 5 shows a flowchart of a method for decoding a polarization code according to the present application.

Fig. 6 is a schematic diagram of a system architecture of CRC-polar concatenated coding.

Fig. 7 is a simulation diagram of BLER for a CA-SCL decoding algorithm and a polar code rearrangement decoding algorithm of the present application.

Fig. 8 is a graph comparing BLER for the same decoding times for the polar code rearrangement decoding algorithm and the CA-SCL decoding algorithm of the present application.

Fig. 9 is a schematic diagram of a decoding apparatus 900 according to the present application.

Fig. 10 is a schematic block diagram of a decoding apparatus 900 according to the present application.

Fig. 11 is a schematic block diagram of a decoder 1000 according to an embodiment of the present application.

Detailed Description

The technical scheme of the application will be described below with reference to the accompanying drawings.

Referring to fig. 1, fig. 1 is a schematic diagram of an architecture of a wireless communication system suitable for use in the present application. As shown in fig. 1, the wireless communication system may include at least one network device 110 and at least one terminal device (e.g., 111,112, and 113 shown in fig. 1). The network device 110 and the terminal device communicate wirelessly. When the network device 110 sends a signal to the terminal device, the network device 110 is an encoding end, and the terminal device is a decoding end. When the terminal device sends a signal to the network device 110, the terminal device is an encoding end, and the network device is a decoding end.

Wireless communication systems mentioned by embodiments of the present application include, but are not limited to, wireless local area network (wireless local access network, WLAN) systems, narrowband internet of things (NB-IoT) systems, long term evolution (long term evolution, LTE) systems, fifth generation (5G) communication systems, or 5G-later communication systems, etc.

The network device mentioned in the present application may be any device having a wireless transceiver function. The network device includes, but is not limited to, a Node B (NB), an evolved node B (evolved node base, eNB) in a long term evolution (long term evolution, LTE) system, a radio network controller (radio network controller, RNC), an evolved LTE (evolved LTE) base station, a next generation node B (next generation node B, gNB) in a 5G system, and may also be a base station controller (base station controller, BSC), a base transceiver station (base transceiver station, BTS), an Access Point (AP), a radio backhaul node, a transmission point (transmission point, TP), a transmission reception point (transmission and reception point, TRP), a Home Node B (HNB), and so on. Or may also be a network node that forms a gNB or a transmission point, for example, a baseband unit (building baseband unit, BBU) or a Distributed Unit (DU), etc., which is not limited by the present application.

The terminal device referred to in the present application may also be referred to as a User Equipment (UE), a mobile station, an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a terminal, a wireless communication device, a user agent, a Station (STA) in a WLAN, a cellular phone, a cordless phone, a session initiation protocol (session initiation protocol, SIP) phone, a wireless local loop (wireless local loop, WLL) station, a personal digital assistant (personal DIGITAL ASSISTANT, PDA), a handheld device with wireless communication capabilities, a computing device, other processing devices connected to a wireless modem, a vehicle-mounted device, a wearable device, a mobile station in a 5G network, a terminal device in a future evolved public land mobile network (public land mobile network, PLMN) network, etc.

Referring to fig. 2, fig. 2 is a schematic diagram of a basic flow of wireless communication. As shown in fig. 2, at the transmitting end of the signal, the source sequentially performs source coding, channel coding and digital modulation and then transmits the signal. The receiving end of the signal outputs the signal to the signal sink through digital demodulation, channel decoding and signal source decoding in turn. Channel coding is one of the core technologies in the wireless communication field. Currently, polar codes (polar codes) are channel coding techniques that can theoretically prove to reach shannon's limit and have practical linear complexity coding and decoding capabilities.

Polar codes are a type of linear block code. Among the Polar decoding algorithms, the serial cancellation (successive cancellation, SC) decoding algorithm is the most basic decoding algorithm. The SC decoding algorithm can achieve very good progressive performance as the code length approaches infinity. At a limited code length, there will still be some information bits that cannot be decoded correctly, since the polarized channel is not complete. It is known from the coding principle of polar codes that since the individual polarized channels are not independent of each other, the polarized channels with a larger channel number depend on all the polarized channels with a smaller number. Based on the dependency relationship between polarized channels, the SC decoding algorithm sequentially carries out decoding decision on each bit according to the sequence from the smaller channel sequence number to the larger channel sequence number. And, when deciding the ith bit, it is based on the assumption that the result of the decoding decision of all the previous (i-1) bits is correct. As the code length approaches infinity, each information bit is correctly decoded because the split channel is close to fully polarized (channel capacity is either 0 or 1). However, at a limited code length, there are still some information bits that cannot be decoded correctly because the channel polarization is not complete. Since the SC decoding algorithm needs to use the estimated value of the previous information bit when decoding the latter information bit, and is a greedy algorithm, the next layer is performed by searching only the optimal path at each layer of the code tree. Thus, if the decoding of the previous i-1 information bits is erroneous, a more severe error transfer results.

For the shortcomings of the SC decoding algorithm, a serial cancellation list (successive cancellation list, SCL) decoding algorithm is proposed. In the SCL decoding algorithm, the number of candidate routes allowed to be reserved is increased at each layer of the code tree, and only ' optimal one path is allowed to be selected for next-layer expansion ' from each layer of the SC decoding algorithm, and ' best path is allowed to be selected for next-layer expansion ' instead of ' maximum. Specifically, when the SCL decoding algorithm decodes, path searching is sequentially performed from the root node of the decoding tree to the leaf node layer by layer. Unlike SC, SCL decoding algorithms are breadth-first, which introduce breadth-first search strategies into the code tree search mechanism, spread and prune first, and finally reach leaf nodes. The decoding decision of each layer keeps a small surviving path list, and finally, the path with the highest likelihood probability is selected from the surviving path list as the decision path. Given a list length L, the SCL decoding algorithm has a complexity of O (lnlog n), whose performance can approach the maximum likelihood (maximum likelihood, ML) decoding performance.

Referring to fig. 3, fig. 3 is an example of an SCL decoding algorithm with l=2. As shown in fig. 3, assuming that the list size of the SCL decoding algorithm is L, when the decoding end performs SCL decoding, each layer retains L surviving paths from the root node of the code tree, and enters the path expansion of the next layer until reaching the leaf node of the code tree. When SCL decoding of the polar code is completed, a set of candidate paths is obtained. And finally, the decoding end selects one path with the best metric value from the L candidate paths as a decoding path to output. It should be appreciated that, in the code tree, a path formed from the root node to any one of the nodes corresponds to a path metric (PATH METRIC, PM) value, and the PM value may be used as a reference for determining the quality of the path. The decoding end reserves L candidate paths at each layer of reference PM value of the code tree. Thus, according to the SCL decoding algorithm, the decoding process of the polar code looks for a suitable decoding path on the full binary tree shown in fig. 3. As shown in fig. 3, when the list size l=2 of the SCL decoding algorithm, 2 candidate paths are reserved at each layer starting from the root node to extend to the next layer until the leaf node is reached. Taking the example shown in fig. 3 as an example, upon completion of decoding according to the SCL decoding algorithm, two candidate paths are retained in the candidate list, [0011] and [1000], respectively. Finally, the decoding end can select one with the optimal metric value from the 2 candidate paths as the decoding path.

And CRC assisted SCL (CRC-SCL, CA-SCL) decoding algorithm is based on SCL decoding algorithm, CRC check bits are added in the information bit sequence. During decoding, the decoding end adopts SCL decoding algorithm to decode, L candidate paths are normally obtained, and then the L candidate paths are selected by means of the prior information that correct information bits can pass CRC, so that the best decoding path is output as a decoding result.

Taking fig. 3 as an example, the decoding end inputs the reserved 2 candidate paths into a CRC module to perform CRC, and outputs the candidate paths passing through the CRC as a decoding result. Assuming that candidate path 0011 shown in fig. 3 passes the CRC and candidate [1000] does not pass the CRC, candidate path [0011] is output as a decoding result.

Although the CA-SCL decoding algorithm may improve decoding performance with a lower complexity relative to the SCL decoding algorithm. The error rate of the CA-SCL decoding algorithm still needs to be reduced.

Therefore, the application provides a decoding method of a polarization code, which aims to reduce the error rate of a CA-SCL decoding algorithm.

Referring to fig. 4, fig. 4 is a flowchart of a method 400 for decoding a polarization code according to the present application. The method 400 may be performed by a decoding side (i.e., a decoding apparatus), or may be performed by a chip, a processing circuit, or the like installed in the decoding side, a device or a component, or the like, having a function of implementing the method described below. Alternatively, the decoding end may be a network device as shown in fig. 1, or may be a terminal device.

410. SCL decoding is carried out on the LLR sequence of the polarization code, and a first estimated sequence of the information bit sequence is obtained.

For descriptive convenience, the LLR sequence obtained at the decoding end is hereinafter denoted as y, and the information bit sequence is denoted as u.

According to the coding and decoding flow of the polarization code, the coding end performs polar coding on the information bit sequence to obtain a polarization code word (or polarization code). The encoding end transmits the polarized code word to the decoding end. The decoding side demodulates the signal received on the polarized channel to obtain a sequence of LLRs (or also called a sequence of soft values). Of course, the polarized codeword obtained by polar coding may also be subjected to corresponding processing of channel coding procedures such as modulation and mapping, which will not be described in detail herein.

The decoding end performs SCL decoding on y with list size L to obtain an estimated sequence of u, which is called as a first estimated sequence.

Optionally, the specific value of the list size L is not limited.

In step 410, the process of decoding the SCL with list size L for the LLR sequence may be referred to above in describing the SCL decoding algorithm, e.g., fig. 3, and will not be described in detail herein.

420. And if the first estimated sequence does not pass through the CRC, rearranging the LLR sequence j times to obtain a j rearranging sequence of the LLR sequence.

In the coding theory, the rearrangement characteristic of the code word means that the bit positions of the code word of a code are rearranged in a specific manner, and the code word obtained after rearrangement is still the code word of the code.

Therefore, in step 420, the decoding end rearranges the LLR sequences, which means that the decoding end rearranges the bit positions in the LLR sequences, and the LLR sequences after the rearrangement are called rearranged sequences.

In step 420, j is equal to or greater than 1, and j is an integer. In other words, the LLR sequences may be reordered one or more times in the event that the first estimated sequence fails the CRC. Wherein, each pair of LLR sequences is rearranged once, a rearranged sequence is obtained. Thus, after the j-th rearrangement is completed, the j-th rearranged sequence of the LLR sequence will be obtained.

Note that the j rearrangements of the LLR sequences are performed sequentially. When the j-1 th rearrangement sequence of the LLR sequence is obtained after the j-1 th rearrangement, whether the j-1 th rearrangement is performed depends on whether the estimated value of the information bit sequence obtained from the j-1 th rearrangement sequence can pass the CRC.

Specifically, according to the j-1 rearrangement sequence, an estimated value of the information bit sequence can be obtained, and if the estimated value can pass through the CRC, the decoding end outputs the estimated value as a decoding result, and decoding is finished. If the estimated value does not pass the CRC and the decoding frequency does not reach the set maximum decoding frequency, the decoding end needs to perform j-th rearrangement on the LLR sequence.

Therefore, if the LLR sequence is rearranged j times, it is explained that none of the estimated values of the information bit sequence determined from the rearranged sequence obtained from the previous (j-1) times passes the CRC.

For example, taking the m-th rearrangement of the previous (j-1) rearrangements as an example, the LLR sequences are rearranged m-th to obtain a rearranged sequence. An estimated sequence of information bit sequences is calculated from the reordered sequence. If the estimated sequence can pass the CRC, the estimated sequence is output as a decoding result, and decoding is finished. If the estimated sequence does not pass the CRC, then the m+1st rearrangement is performed to obtain yet another rearranged sequence of LLR sequences. Then, a further estimated sequence of the information bit sequence is calculated from the reordered sequence obtained by the m+1th reordering. If the further estimated sequence passes the CRC, the further estimated sequence is output as a decoding result, if the further estimated sequence does not pass the CRC, the next reordering is continued, and so on.

Of course, before each rearrangement, it is also necessary to determine whether the current decoding number reaches the set maximum decoding number. If the current decoding times do not reach the set maximum decoding times, the next rearrangement is continued. Otherwise, the decoding fails.

430. A second estimated sequence of information bit sequences is determined based on the j-th reordered sequence of LLR sequences.

Here, the second estimated sequence refers to an estimated sequence (or, an estimated value) of the information bit sequence determined according to the j-th rearranged sequence, which is obtained by performing the j-th rearrangement of the LLR sequence.

In addition, the second estimation sequence is numbered for distinction from the first estimation sequence above, and has no other special meaning.

It should be further noted that, the decoding end performs j rearrangements on the LLR sequence, and each rearrangement results in a rearranged sequence of the LLR sequence. Further, an estimated value of the information bit sequence can be calculated from each reordered sequence. If the decoding end rearranges through the previous (j-1), and the calculated estimated value of the information bit sequence does not pass through the CRC, the LLR sequence is rearranged for the j time to obtain a j-th rearranged sequence, and according to the j-th rearranged sequence, the further estimated value of the information bit sequence is obtained. The estimated value of the information bit sequence determined from the j-th reorder sequence calculation is referred to herein as a second estimated sequence.

The process of rearranging the LLR sequences and determining the estimated value of the information bit sequence from the rearranged sequences mentioned in steps 420-430 will be described in detail below.

440. In the case where the second estimation sequence passes the CRC, the second estimation sequence is output as a decoding result.

If so, a second estimated sequence of information bit sequences is calculated based on the j-th reordered sequence. If the second estimated sequence passes the CRC, the decoding end judges that the second estimated sequence is the best decoding path, and the second estimated sequence is output as a decoding result.

It will be appreciated that in another case, if the second estimated sequence does not pass through the CRC, the j-th rearrangement is the same as any one of the previous (j-1) rearrangements described above, and the decoding end performs the j+1-th rearrangement on the LLR sequence, so that the repetition is omitted.

If the estimated value of the information bit sequence determined according to the obtained m-th rearrangement sequence does not pass through the CRC after the m-th rearrangement, and the current decoding times reach the set maximum decoding times, the decoding end judges that the decoding fails. And the estimated value of the information bit sequence determined in the m-th rearrangement sequence does not pass through the CRC, and the current decoding frequency is smaller than the set maximum decoding frequency, and then the m+1th rearrangement is performed.

As can be seen from the above description, in the decoding method of the polar code of the present application, the LLR sequence is firstly SCL decoded to obtain an estimated value of the information bit sequence, and if the estimated value cannot pass through the CRC, the decoding end rearranges the LLR sequence to obtain a rearranged sequence of the LLR sequence. And the decoding end redetermines the estimated value of the information bit sequence according to the rearrangement sequence. If the estimated value of the information bit sequence determined according to the rearranged sequence can pass through the CRC, the decoding end outputs the estimated value as a decoding result. If the estimated value of the information bit sequence determined according to the rearranged sequence cannot pass through the CRC, the decoding end rearranges the LLR sequence again and redetermines the estimated value of the information bit sequence, and the method loops until the estimated value of the information bit sequence determined according to a certain rearranged sequence passes through the CRC, and then the decoding is successful.

An example of a detailed flow of the decoding method proposed by the present application is given below in conjunction with fig. 5.

As shown in fig. 5, fig. 5 shows a flowchart of a method for decoding a polarization code according to the present application. The flow shown in fig. 5 may be executed by the decoding end.

510. Initializing.

The initialization mainly includes the initialization of the channel model. For example the code length N of the polarization code, the generator matrix G of the polarization code, the length K of the information bit sequence, and the strategy for selecting information bits in the information bit sequence (denoted as u). Wherein n=2 ⁿ.

It will be appreciated that the information bit sequence u includes information bits and freeze bits.

Step 510 may include selecting a channel type (channel model), selecting a modulation scheme, and the like.

For example, the channel type may be Additive White Gaussian Noise (AWGN), and the modulation mode may be Binary Phase Shift Keying (BPSK).

Alternatively, as an example, for AWGN channel, BPSK modulation, the transmit bit sequence may be x=1-2 c and the llr sequence may be y=x+n. Where n represents the noise sequence of AWGN.

520. A set of rearrangement matrices Q of the polarization codes is determined.

The rearrangement matrix is used for rearranging the LLR sequences to obtain rearranged sequences.

It will be appreciated that the rearrangement patterns are different, and the corresponding rearrangement matrices Q are also different, so that the number of rearrangement matrices of the LLR sequence is plural. Or, the decoding end needs to determine a set of rearrangement matrices Q of the polarization code, where each rearrangement matrix Q corresponds to a specific rearrangement mode.

The number of rearrangement matrices is equal to the maximum number of rearrangement attempts preset by the decoder, and can be determined by the preset capacity of the decoder.

The decoding end rearranges the LLR sequences once, and a rearrangement matrix different from the previous one needs to be selected. In other words, the decoding end performs the j-th rearrangement of the LLR sequence, and selects a rearrangement matrix different from the previous (j-1) rearrangement, so that the j-th rearrangement sequence obtained by the j-th rearrangement and the j-1 rearrangement sequence obtained by the previous (j-1) rearrangement are different from each other.

For example, the set of rearrangement matrices may be denoted as Q ₁,Q₂,…,Q_j,…,Q_M, respectively. And (3) carrying out 1 st rearrangement on the LLR sequence by adopting Q ₁ to obtain a1 st rearrangement sequence. And (3) rearranging the LLR sequence for the 2 nd time by adopting Q ₂ to obtain a2 nd rearranged sequence. Similarly, the j-th rearrangement of the LLR sequence is performed by adopting Q _j to obtain the j-th rearrangement sequence.

In one implementation, the decoding end may calculate the rearrangement matrix of the polarization code offline and store it in advance.

In another implementation manner, the decoding end can calculate the rearrangement matrix of the polarization code in an online calculation manner.

The method of computing the rearrangement matrix may be the same whether off-line or on-line, as described in more detail below.

It is assumed that the rearrangement function of the ith bit in codeword c of the polar code can be expressed as:

i'=p(i) (1)

Then, the rearranged codeword c' according to the rearrangement function satisfies the following formula (2):

c'=(c_p(0),c_p(1),...,c_p(N-1)) (2)

how to obtain the rearrangement function i' =p (i) is given below:

let i be represented as a binary vector of the following formula (3):

b_i＝(b_i,0,b_i,1,...,b_i,n-1)^T (3)

The binary vector of i' is denoted b _i', from the rearrangement properties of the polarization code, one can obtain:

b_i'＝1-(P(1-b_i)+a) (4)

Wherein P is a random reversible square matrix, and a is a constant vector. The size of P is equal to the code length N of the polarization code.

Thus, according to equation (4), the rearrangement process of the polarization code can be expressed as i' =p (i).

Further, according to the rearrangement process of the polarization code i' =p (i), a rearrangement matrix Q of the polarization code can be obtained as the following formula (5):

c'=c·Q (5)

530. Decoding is carried out according to a polarization code rearrangement decoding algorithm.

As described above, in the technical solution of the present application, the decoding end performs SCL decoding with list size L on the LLR sequence, and if the estimated value of the obtained information bit sequence cannot pass through the CRC, it is necessary to re-determine the estimated value of the information bit sequence by rearranging the LLR sequence. Therefore, the decoding algorithm of the polarization code provided in the present application will be simply referred to as a polarization code rearrangement decoding algorithm hereinafter.

The process of re-ordering the decoding of step 530 is described in detail below in connection with steps 531-537.

It should be appreciated that step 530 is a generalized illustration of steps 531-537, or that steps 531-537 are specific implementations of the polar code re-ordering decoding algorithm.

531. The current decoding number j=0 and the maximum decoding number is J _max.

532. SCL decoding with list size L is carried out on LLR sequence y to obtain estimated value of uAnd j=j+1.

533. JudgingWhether or not the CRC is passed.

If it isWith CRC, step 540 is performed.

If it isIf the CRC fails, 534 is performed.

534. And judging whether J is less than or equal to J _max.

If J is less than J _max, then step 535 is performed, otherwise step 540 is performed.

535. According to step 420, a rearrangement matrix Q of the polar codes is obtained, and the LLR sequences y of the polar codes are rearranged to obtain y' =y·q.

It should be appreciated that y' is the reordered sequence of the LLR sequences described above.

536. SCL decoding the rearranged sequence y' with list size L to obtain

Wherein, the I.e. the intermediate sequence as referred to herein.

It can be appreciated that, according to the rearrangement characteristics of the polarization code described above, the coding formula for the polarization code is:

c=u·G (6)

and there is c' =c·q according to the rearrangement matrix Q of the polarization code.

Let c ' =u ' G, u ' denote the rearranged information bit sequence corresponding to the rearranged codeword of the polarization code.

In other words, the mapping relationship between the codeword c ' obtained after the rearrangement of the polarization code and the generation matrix G of the polarization code can be expressed as c ' =u ' G (7)

If it is assumed that u' and u satisfy the following equation (8):

u'=uT (8)

And c '=cq= uGQ =u' g= uTG, this can be achieved by:

T=GQG=u'G=uTG (9)

537. obtaining T by using the formula (9), according to the formula ObtainingExecution returns to step 433.

540. Output ofAs a result of the decoding.

The method for decoding the polarization code provided by the application is described in detail above.

The following is an example to aid understanding.

For example, let the index of each bit in codeword c of the polarization code be i=0, 1,2,3,4,5,6,7, if p (i) = 0,2,4,6,1,3,5,7, respectively.

Then, the binary vector b _i' = (000,001,010,011,100,101,110,111) of the position index of each bit in the codeword c, the binary vector b _i' = (000,010,100,110,001,011,101,111) of the position index of each bit in the codeword c in the rearranged set of codewords.

In one example, one rearrangement matrix of the set of rearrangement matrices described above may be represented as formula (10):

the matrix T can be expressed as formula (11):

In applying channel coding techniques in practice, many practical factors, such as efficiency, performance, and latency, often need to be considered. As can be seen from the channel coding theory, as the code length N increases, the decoding error probability becomes exponentially zero. Therefore, to increase the effectiveness of error correction codes, long codes must be used. However, the code length is increased, the code rate is correspondingly reduced, and the complexity and the calculated amount of the decoder are correspondingly increased. The cascade code is proposed to solve the contradiction, the coding process is completed in several stages, the requirement of channel error correction on the coding length can be met, and the error correction capability and the high coding gain which are close to or even the same as those of the long code are obtained. Moreover, the accompanying increasing coding complexity is not very great. In other words, if a system includes multiple (at least two) encodings, the multiple encodings are considered to be concatenated encodings.

The concatenated coding includes an outer code coding and an inner code coding. Wherein the input of the outer code coding is the information bit sequence to be coded, and the output of the outer code is used as the input of the inner code. The output of the inner code coding is the code word after the cascade coding is completed. For example, in CRC-polar concatenated coding, the outer code of the concatenated coding employs CRC coding, and the inner code employs polar coding. Fig. 6 shows the basic flow of CA-SCL encoding.

Referring to fig. 6, fig. 6 is a schematic diagram of a system structure of a CRC-polar concatenated codec. As shown in fig. 6, when cascade encoding is performed on CRC and polar, assuming that the code length of the polar code is N and the code length of the CRC check code is m, if the information bit length of the polar code is K and the encoded information bit length is K, k=k+m. The CA-SCL decoding algorithm firstly adopts SCL decoding algorithm to decode and obtain L candidate paths, and then selects the L candidate paths by means of the prior information that the correct information bits can pass through CRC, so as to output the best decoding path.

It should be understood that the CA-SCL decoding algorithm is an enhancement to the SCL algorithm, the kernel of the SCL is unchanged, CRC is added to information bits just before Polar encoding, and CRC checking auxiliary path selection is performed after the SCL decoding obtains candidate paths, so that Polar decoding performance can be improved with lower complexity.

In the CA-SCL decoding shown in FIG. 6, the rearrangement decoding algorithm provided by the application can be adopted.

Referring to fig. 7, fig. 7 is a simulation diagram of BLER for a CA-SCL decoding algorithm and a polar code rearrangement decoding algorithm of the present application. In fig. 7, it is assumed that the code length n=32, the information bit length k=16, and the length of the crc bit sequence is 8. The polarization code is constructed by constructing Polarization Weight (PW), and the simulation channel is an AWGN channel. The number of polarization code rearrangement decoding times is 50.

As can be seen from fig. 7, under the same condition of the list size L (l=1, 2,4 as shown in fig. 7), the block error rate (block error ratio, BLER) of the polar code re-ordering decoding algorithm of the present application is lower than the BLER of the CA-SCL decoding algorithm. The polarization code rearrangement decoding algorithm of the present application is illustrated in fig. 7 as CA-SCL period.

Referring to fig. 8, fig. 8 is a graph comparing BLER for the same decoding times for the polarization code rearrangement decoding algorithm and the CA-SCL decoding algorithm of the present application. It can be seen from fig. 7 that when the average decoding times are the same, the BLER of the rearrangement decoding algorithm of the polar code is lower than that of the CA-SCL decoding algorithm.

From the simulation data, the polar code rearrangement decoding algorithm can obtain performance gain when the list size L is the same, compared to conventional CA-SCL decoding. In addition, in complexity, as the signal-to-noise ratio increases, the average number of times of decoding required by the polar code rearrangement decoding algorithm of the present application gradually decreases, and tends to be 1.

Therefore, the polar code rearrangement decoding algorithm provided by the application can improve the decoding performance of polar codes.

The polar code rearrangement decoding algorithm provided by the application is described in detail above, and the decoding device provided by the application is described below.

Referring to fig. 9, fig. 9 is a schematic diagram of a decoding apparatus 900 according to the present application. As shown in fig. 9, the decoding apparatus 900 includes a processing unit 910 and a communication unit 920.

A processing unit 910, configured to perform SCL decoding on the LLR sequence to obtain a first estimated sequence of information bit sequences;

The processing unit 910 is further configured to reorder the LLR sequence j times to obtain a j-th reorder sequence of the LLR sequence if the first estimated sequence does not pass the CRC;

A communication unit 920, configured to output the second estimation sequence as a decoding result when the processing unit 910 determines that the second estimation sequence passes the CRC.

Optionally, in one embodiment, the processing unit 910 is specifically configured to:

(3) Judging whether the nth estimation sequence passes the CRC;

and rearranging the LLR sequence j times, wherein the rearranging comprises the m-th rearrangement and the q-th rearrangement of the LLR sequence, respectively adopting different rearranging matrixes in the group of rearranging matrixes, and obtaining different rearranging sequences, wherein the m-th rearrangement and the q-th rearrangement refer to any two rearrangements of the LLR sequence, and q is less than or equal to j and q is an integer.

determining an intermediate sequence according to the j-th rearrangement sequence;

and obtaining the second estimated sequence according to the intermediate sequence, the generation matrix of the polarization code and a first rearrangement matrix in the group of rearrangement matrices, wherein the first rearrangement matrix is different from a rearrangement matrix used for any one of the previous (j-1) rearrangements.

The second estimated sequence is calculated according to the following formula:

Optionally, the processing unit 910 is specifically configured to:

Representing the ith bit in the code word of the polarization code as a binary vector b _i, wherein i is less than or equal to N, and N is the code length of the polarization code;

Determining binary vectors b _i' of position indexes i' of the ith bit in a group of rearranged code words according to rearrangement characteristics of the polarized codes, wherein the rearrangement characteristics of the polarized codes refer to specific rearrangement of bit positions of the code words of the polarized codes, and the code words obtained after rearrangement are still code words of the polarized codes;

The set of rearrangement matrices is obtained from the b _i and the set of b _i'.

Optionally, in one embodiment, each b _i' of the b _i and the set of b _i' satisfies the following formula:

b_i'＝1-(P·(1-b_i)+a)

Wherein P is a random reversible square matrix, and a is a constant vector.

In one possible design, the above-described functions of the decoding apparatus 900 may be implemented by hardware, or by executing corresponding software by hardware.

As an embodiment, the decoding apparatus 900 may include one or more processors configured to execute a computer program stored in a memory, so that the decoding apparatus 900 performs any one of the method embodiments provided by the present application.

Optionally, the memory for storing the computer program is located outside the decoding device 900, and the one or more processors are connected to the memory through circuits and/or wires. The memory may be one or more.

Optionally, the decoding apparatus 900 further comprises one or more memories.

Further optionally, the decoding apparatus 900 further comprises one or more communication interfaces.

As some examples, the communication interface or interfaces may be an input-output interface, or an output-output circuit, as the application is not limited in this regard.

As another embodiment, the decoding apparatus 900 may also be implemented by hardware.

Referring to fig. 10, fig. 10 is a schematic block diagram of a decoding apparatus 900 according to the present application. As shown in fig. 10, the decoding apparatus 900 includes an input interface circuit 901, a logic circuit 902, and an output interface circuit 903.

The device comprises an input interface circuit 901 for obtaining LLR sequences, a logic circuit 902 for decoding the LLR sequences by adopting the polarized code rearrangement decoding algorithm provided by the application, and an output interface circuit 903 for outputting decoding results.

Alternatively, the decoding apparatus 900 may be a chip or an integrated circuit. For example, the chip may be a System On Chip (SOC), a baseband chip, or the like.

Alternatively, the decoding apparatus 900 may be a device or a module for implementing channel decoding in the decoding side. Such as a channel decoder or channel decoding circuit, etc.

Fig. 11 is a schematic block diagram of a decoder 1000 according to an embodiment of the present application. As shown in fig. 11, the decoder 1000 includes one or more processors 1100, one or more memories 1200, and one or more communication interfaces 1300. The communication interface 1300 is used for obtaining the LLR sequence, the memory 1200 is used for storing a computer program, and the processor 1100 is used for calling and running the computer program from the memory 1200, so that the decoder 1000 adopts the polar code rearrangement decoding method provided by the application to finish decoding the LLR sequence.

Further, the communication interface 1300 is further configured to output the decoding result.

In addition, the decoding apparatus 900 shown in fig. 9 may be implemented by the decoder 1000 shown in fig. 11.

For example, the communication unit 930 may be implemented by the communication interface 1300 in fig. 11, the processing unit 910 may be implemented by the processor 1100, and so on.

Alternatively, the memory and processor in the apparatus embodiments may be integrated together or physically separate units from each other.

In addition, the application also provides a decoding device, which comprises a processor and an interface circuit, wherein the interface circuit is used for receiving computer codes or instructions and transmitting the computer codes or instructions to the processor, and the processor is used for running the computer codes or instructions so as to execute the rearrangement decoding method of the polarization codes.

Furthermore, the present application provides a computer readable storage medium having stored therein a computer program which, when run on a computer, causes the polarization code rearrangement decoding method of the present application to be implemented.

The present application also provides a computer program product comprising computer program code for causing the polarization code rearrangement decoding method of the present application to be implemented when said computer program code is run on a computer.

The application also provides a chip comprising one or more memories and one or more processors. The one or more memories are used for storing computer programs, and the one or more processors are used for calling and running the computer programs from the one or more memories, so that the device provided with the chip executes the polarization code rearrangement decoding method.

The application also provides a communication device comprising the decoder 1000.

The decoding side, i.e. the receiving side of the signals and/or data, is herein referred to. Accordingly, the party transmitting the signal and/or data is the transmitting end. Alternatively, the decoding end may be a network device (e.g. a 5G gNB) in the communication system, or may be a terminal device, which is not limited by the scheme of the present application.

In the above embodiments, the processor may be a central processing unit (central processing unit, CPU), a general purpose processor, a digital signal processor (DIGITAL SIGNAL processor, DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (field programmable GATE ARRAY, FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, a microprocessor or one or more integrated circuits for controlling the execution of programs in accordance with aspects of the present application, or the like. For example, the processor may include a digital signal processor device, a microprocessor device, an analog-to-digital converter, a digital-to-analog converter, and the like. The processor may allocate the functions of control and signal processing of the mobile device among the devices according to their respective functions. Further, the processor may include functionality to operate one or more software programs, which may be stored in memory. The functions of the processor may be implemented by hardware, or may be implemented by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

The memory may be read-only memory (ROM) or other type of static storage device that can store static information and instructions, random access memory (random access memory, RAM) or other type of dynamic storage device that can store information and instructions, but may also be electrically erasable programmable read-only memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ-only memory, EEPROM), compact disc read-only memory (compact disc read-only memory) or other optical disk storage, optical disk storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. Both an application running on a computing device and the computing device can be a component. One or more components may reside within a process and/or thread of execution. The components may reside on one computer and/or be distributed between two or more computers. Furthermore, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes in accordance with a signal having one or more data packets (e.g., data from two components interacting with one another in a local system, distributed system, and/or network such as the internet with other systems by way of the signal).

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware, depending on the specific application and design constraints of the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the several embodiments provided by the present application, the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are also merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present application.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present application

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for decoding a polarization code, comprising:

Performing Serial Cancellation List (SCL) decoding on the LLR sequence of the polarization code to obtain a first estimated sequence of the information bit sequence;

If the first estimated sequence does not pass the cyclic redundancy check CRC, j rearranges the LLR sequence for j times to obtain a j rearranged sequence of the LLR sequence;

Performing SCL decoding on the j-th rearrangement sequence to determine a second estimation sequence of the information bit sequence;

And under the condition that the second estimated sequence passes through the CRC, outputting the second estimated sequence as a coding result, wherein j is more than or equal to 1 and j is an integer.

2. The method of claim 1, wherein the reordering the sequence of LLRs j times comprises:

(3) Judging whether the nth estimation sequence passes the CRC;

3. The method of claim 1 or 2, wherein prior to the j rearrangements of the sequence of LLRs, the method further comprises:

obtaining a set of rearrangement matrices of the LLR sequence, each rearrangement matrix of the set of rearrangement matrices being used to uniquely determine one rearrangement sequence of the LLR sequence;

And, said rearranging the LLR sequence j times, comprising:

And respectively adopting different rearrangement matrixes in the group of rearrangement matrixes to the mth rearrangement and the q-th rearrangement of the LLR sequence to obtain different rearrangement sequences, wherein the mth rearrangement and the q-th rearrangement refer to any two rearrangements of the LLR sequence, and q is less than or equal to j and q is an integer.

4. A method according to claim 3, wherein said SCL decoding said j-th reordered sequence to obtain a second estimated sequence of said information bit sequence comprises:

determining an intermediate sequence according to the j-th rearrangement sequence, wherein the intermediate sequence is an output result obtained by decoding the j-th rearrangement sequence by adopting a serial cancellation list SCL decoding algorithm;

5. The method of claim 4, wherein the obtaining the second estimated sequence from the intermediate sequence, the generator matrix of the polarization code, and a first rearrangement matrix of the set of rearrangement matrices comprises:

The second estimated sequence is calculated according to the following formula:

6. The method of claim 3, wherein obtaining a set of rearrangement matrices for the sequence of LLRs comprises:

7. The method of claim 6, wherein each b _i' of the b _i and the set of b _i' satisfies the following formula:

b_i'＝1-(P·(1-b_i)+a)

Wherein P is a random reversible square matrix, and a is a constant vector.

8. The method of claim 7, wherein said deriving said set of rearrangement matrices from said b _i and said set of b _i' comprises:

9. A decoding apparatus, comprising:

A processing unit for:

Performing said SCL decoding on said j-th reordered sequence, determining a second estimated sequence of said information bit sequence, and determining whether said second estimated sequence passes a CRC, and

And the communication unit is used for outputting the second estimated sequence as a decoding result when the processing unit determines that the second estimated sequence passes the CRC, wherein j is more than or equal to 1 and j is an integer.

10. The coding device of claim 9, wherein the processing unit is configured to:

(3) Judging whether the nth estimation sequence passes the CRC;

11. The coding device according to claim 9 or 10, wherein the processing unit is configured to:

and, the processing unit is further configured to:

12. The coding device of claim 11, wherein the processing unit is configured to:

13. The decoding device according to claim 12, wherein the processing unit is configured to calculate the second estimated sequence according to the following formula:

14. The decoding device according to claim 11, wherein the processing unit is specifically configured to:

15. The coding device of claim 14, wherein each b _i' of the b _i and the set of b _i' satisfies the following formula:

b_i'＝1-(P·(1-b_i)+a)

Wherein P is a random reversible square matrix, and a is a constant vector.

16. The coding device of claim 15, wherein the processing unit is configured to:

17. A decoding apparatus comprising at least one processor coupled to at least one memory, the at least one processor configured to execute a computer program or instructions stored in the at least one memory to cause the decoding apparatus to perform the method of any one of claims 1-8.

18. A decoding device comprising a processor and interface circuitry for receiving computer code or instructions and transmitting to the processor, the processor for executing the computer code or instructions to perform the method of any of claims 1-8.

19. A computer readable storage medium comprising a computer program which, when run on a computer, implements the method according to any one of claims 1-8.

20. A computer program product comprising instructions for performing the method of any of claims 1-8.