CN113055015A

CN113055015A - Analog-to-digital converter with low driving current requirement

Info

Publication number: CN113055015A
Application number: CN202110302221.4A
Authority: CN
Inventors: 李强; 高剑峰; 周雄
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-12-18
Filing date: 2021-03-22
Publication date: 2021-06-29

Abstract

In a biomedical system, an analog-to-digital converter is required to process the collected bioelectrical signals. In terms of speed, accuracy, area and power consumption, SAR ADC has obvious advantages compared with ADCs of other structures. The accuracy of traditional SAR ADCs is limited by sampling noise, comparator noise and other influences. Using oversampling technology can make it perform better in terms of accuracy. Adjusting the timing of the SAR ADC can also effectively reduce the ADC's requirements for the driving capability of the front-end circuit, which is more suitable for applications in biomedical systems. Based on the above advantages, the present invention proposes an analog-to-digital converter with a low driving current requirement. The oversampling technology is used to effectively improve the accuracy of the ADC. Combined with the special circuit timing design, the requirement of the ADC on the driving capability of the pre-stage circuit is reduced. , which improves the performance of the analog-to-digital converter.

Description

Analog-to-digital converter with low driving current requirement

Technical Field

The invention relates to a low-power consumption successive approximation type (SAR) analog-to-digital converter with low driving current requirement, which has the characteristics of medium precision, low power consumption and low driving capability requirement on a preceding stage circuit, and is suitable for being applied to a biomedical system.

Background

In recent years, the demand for biomedical systems has increased rapidly, and various portable biological signal acquisition systems, wearable or implantable biomedical devices have developed rapidly and are continuously integrated into the lives of people. In the biomedical system, the acquired biological signals are slowly changed signals in most of the time, so that an appropriate analog-to-digital converter needs to be selected for processing the acquired biological signals. The SAR ADC has obvious advantages compared with the ADC with other structures in the aspects of speed, precision, area, power consumption and the like, and is more suitable for being applied to a biological electric signal processing system.

The system structure of the successive approximation type analog-to-digital converter mainly comprises four modules: a sample-and-hold circuit, a capacitor array, a comparator, and control logic. The sampling hold circuit is mostly designed based on a grid voltage bootstrap circuit, and the grid voltage of the sampling tube can be increased to be higher than the power voltage, so that the on-resistance of the sampling switch is reduced, and the rail-to-rail sampling can be realized. The capacitor array acts as a sampling capacitor during sampling and holding, and in the quantization process, the digital code word is converted into an analog voltage by inverting the corresponding capacitor. The comparator is used for comparing the voltage of the upper electrode plate of the capacitor array, and controlling the capacitor array to turn over after a comparison result is obtained. The control logic is used for generating a sampling signal, a comparator working and resetting signal and a capacitor array overturning signal, and the whole SAR ADC can work normally and orderly.

Disclosure of Invention

The invention provides a method for reducing the requirement of an ADC on the driving capability of a preceding stage circuit, which is combined with an oversampling technology, improves the precision of an analog-to-digital converter, reduces the requirement on the driving capability of an input signal, and solves the problem that the analog-to-digital converter has the requirement on the high driving capability of the input signal.

The invention provides an analog-digital converter with low driving current requirement, which adopts a successive approximation type architecture, and the whole circuit consists of five modules: the circuit comprises a sample-and-hold circuit, a capacitor array, a comparator, a digital logic circuit and a clock circuit.

As shown in fig. 1, an overall circuit diagram of the present invention is shown, a continuous time signal input from the outside is converted into a discrete time signal by a sample-and-hold circuit, after sampling is completed, a voltage obtained by sampling is held on an upper plate of a capacitor array, under the control of a clock signal, a comparator starts to compare the voltages of the upper plates of capacitors at two ends, an obtained comparison result generates a control signal through a logic circuit, the capacitor array is controlled to be turned over, after the capacitor is turned over, the comparator performs the next comparison, and the process is repeated until quantization is completed.

Fig. 2 shows a control timing diagram of the present invention, and the overall timing adopts an asynchronous operation mode. When the falling edge of the sampling signal comes, the sampling phase is ended, and the quantization phase is started. In the quantization stage, the falling edge of the sampling signal triggers the rising edge of the working signal of the comparator to generate, the comparator starts to work, the first comparison is completed, the digital logic circuit latches the comparison result of the comparator, and the control signal is generated to control the corresponding capacitor of the capacitor array to overturn. Based on the comparison result, the comparator self-circulation clock circuit will pull the comparator working signal low, and the comparator resets. After the capacitor array is turned over, the comparator self-circulation clock circuit pulls the working signal of the comparator high to trigger the start of the next comparison, and the process is circulated until the quantization stage is finished. When the last bit of the latch completion signal of the digital logic circuit comes, the quantization is completed, at this time, the digital code word obtained by the quantization is stored in the register, and then the reset operation of each module is carried out. After the reset is completed, the rising edge of the sampling signal is triggered, next sampling can be started, and the sampling-quantization-reset-sampling process is executed circularly, so that the analog-digital conversion of the input analog signal can be completed.

Fig. 3 is a graph showing the input signal and the voltage variation of the electrode plate on the capacitor array according to the present invention. Because the biological signal is a slowly changing signal in most of time, the sampling signal frequency is far higher than the input signal frequency under the over-sampling condition, so that the voltage difference between two sampling points of the analog-to-digital converter is small in change, the voltage of the upper electrode plate of the capacitor can be reset to the voltage sampled for the first time when the first quantization is finished, and when the second sampling is started, the voltage of the upper electrode plate of the capacitor can be changed along with the input signal only by the aid of the small driving current provided by the preceding stage circuit. By the mode, the requirement of the analog-to-digital converter on the driving capability of the front-stage circuit is greatly reduced, and the method is more suitable for being applied to a biomedical system.

Drawings

Fig. 1 is a schematic diagram of an analog-to-digital converter of the present invention.

Fig. 2 is a timing diagram of the operation of the analog-to-digital converter of the present invention.

FIG. 3 is a diagram illustrating the input signal and the voltage variation of the upper electrode plate of the capacitor array according to the present invention.

Detailed Description

The invention is described in detail below with reference to the figures and the specific embodiments.

The low-power consumption successive approximation type analog-to-digital converter with low driving current requirement provided by the invention is suitable for processing bioelectricity signals in a biomedical system, wherein the sampling holding circuit is designed based on a grid voltage bootstrap switch technology, the sampling ending moment is controlled by an external input signal, and the ADC sampling frequency can be adjusted according to the requirement. During the high level period of the sampling clock, the voltage of the upper electrode plate of the capacitor array changes along with the input signal. After sampling is finished, the capacitor array keeps the voltage at the sampling end moment on an upper polar plate of the capacitor array. The capacitor array weights are 256,128, 64,32,16,8,4,2,1, respectively. The method comprises a one-bit redundant bit for increasing the quantization range and solving the problem that the output digital code word exceeds the ADC quantization range caused by the misadjustment of a comparator. Attenuating capacitor C_pFor matching the input signal to the ADC quantization range. By adopting the upper polar plate sampling mode, the total capacitance value of the ADC can be reduced by half, the reduction of the chip area is facilitated, and the power consumption is saved. And a split capacitor array overturning mode is adopted, so that the overturning speed of the capacitor is improved, and the power consumption is saved. The comparator adopts a three-stage structure, the first stage is a pre-amplification stage, and when comparing, because the input voltages are different, the discharge speeds of the differential input pair transistors are different, so that the voltage drop speeds of the drain ends are different, and the voltages of the drain ends are different. The second stage is formed by an inverter, providing additional gain to further amplify the signal generated by the first stageA voltage difference. The third stage is a StrongARM dynamic latch comparator circuit, the voltage difference generated by the previous two stages is further compared and latched to obtain a comparison result, and the noise of the comparator can be reduced and the speed of the comparator can be improved due to the three-stage structure. The digital logic circuit is designed based on a latch, latches a comparison result generated by the comparator and controls the corresponding bit capacitor to overturn, and then starts the next comparison after the overturn is completed. The clock circuit adopts asynchronous working time sequence, the delay unit is realized by adopting phase inverter cascade, and the delay time is controllable. The output buffer is designed based on the D trigger, and after quantization is finished each time, the output code words are stored in the D trigger array through the rising edge of the quantization finished signal. And at the end of the next sampling, outputting the digital code word obtained by the last quantization by the falling edge of the sampling signal, and circulating the process to obtain the digital code word of each quantization. The ideal DAC is adopted to carry out digital-to-analog conversion on the output code words, so that analog voltage values can be obtained, Fourier transformation is carried out on the analog voltage values, and indexes such as SNDR, SFDR, ENOB, THD and the like can be obtained.

Simulation is carried out in cadence, Transient simulation is carried out by selecting a Transient, simulation conditions are set, in order to realize incoherence between an input signal and a sampling signal, the frequency of the input signal is set to be 78.125Hz, the amplitude is 150mV, the common mode voltage is 900mV, the power supply voltage is 1.8V, the ground voltage is 0V, and the reference voltage V of a flip capacitor is set_refpAnd V_refnThe voltage is respectively 1.8V and 0V, the sampling frequency is set to be 10KHz, the Transient simulation time is set to be 20m, simulation is operated, the output analog voltage can be obtained, the output result is analyzed, and the performance condition of the ADC can be obtained.

Claims

1. The analog-to-digital converter with low driving current requirement is characterized in that the requirement of the analog-to-digital converter on the driving capability of a preceding stage circuit is low, the precision of the SAR ADC is improved by combining an oversampling technology, and the performance of the ADC is improved.

2. The analog-to-digital converter with low driving current requirement as claimed in claim 1, when the quantization is finished, the voltage of the upper plate of the capacitor is restored to the sampled voltage through the reset capacitor array, the current for resetting the voltage of the upper plate of the capacitor array is provided by the power supply, no input signal is needed to provide the current, the sampling frequency is much higher than the frequency of the input signal under the condition of oversampling because the input signal changes slowly, the voltage difference between two samplings is small, and thus the voltage of the upper plate of the capacitor can change along with the input signal only by the previous stage circuit providing a small driving current, and the requirement of the ADC on the driving capability of the previous stage circuit is effectively reduced.

3. A low drive current requirement analog-to-digital converter as claimed in claim 1, wherein the oversampling is achieved by controlling the switching frequency of the sample-and-hold circuit such that, at the nyquist sampling rate, the signal bandwidth is half of the nyquist sampling rate, the noise is distributed over the entire signal bandwidth, and the total noise power is Δ²12, when sampling is carried out by adopting the Nyquist frequency OSR times, the total noise power is not changed, but the noise power in the signal bandwidth is reduced to 1/OSR of the total noise power, the OSR is increased by one time, and the SNDR is increased by 3dB, so that the precision of the ADC can be effectively improved by the oversampling technology.