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CN113053996A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN113053996A
CN113053996A CN202010869878.4A CN202010869878A CN113053996A CN 113053996 A CN113053996 A CN 113053996A CN 202010869878 A CN202010869878 A CN 202010869878A CN 113053996 A CN113053996 A CN 113053996A
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Prior art keywords
trench
substrate
iii
semiconductor structure
compound layer
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CN113053996B (en
Inventor
王庆森
陈旷举
萧鹏展
刘汉英
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Nuvoton Technology Corp
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Nuvoton Technology Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a III-V compound layer disposed on the substrate. The III-V group compound layer is provided with n grooves which are communicated with each other up and down, and n is more than or equal to 2. Among the n trenches, a width of an uppermost 1 st trench decreases to a width of a lowermost nth trench, and the nth trench exposes a portion of the substrate.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present invention relates generally to semiconductor structures and methods of fabricating the same, and more particularly to a semiconductor structure and a method of fabricating the same that can release stress between a III-V compound layer and a substrate.
Background
Group III-V compounds have been actively studied due to their characteristics such as high energy gap, high thermal conductivity, and chemical stability, and have been widely used in recent years in devices such as High Electron Mobility Transistors (HEMTs), Schottky Barrier Diodes (SBDs), and the like.
However, after epitaxially growing a group III-V compound layer on a silicon substrate, stress is generated at an interface between the group III-V compound layer and the silicon substrate due to lattice mismatch (mismatch) between the group III-V compound layer and the silicon substrate, and thus the formed structure is easily damaged.
Disclosure of Invention
The invention provides a semiconductor structure which can release stress between a III-V compound layer and a substrate.
The invention provides a manufacturing method of a semiconductor structure, which is used for manufacturing the semiconductor structure.
The semiconductor structure of the invention includes a substrate and a III-V compound layer disposed on the substrate. The III-V group compound layer is provided with n grooves which are communicated with each other up and down, and n is more than or equal to 2. Among the n trenches, a width of an uppermost 1 st trench decreases to a width of a lowermost nth trench, and the nth trench exposes a portion of the substrate.
In an embodiment of the semiconductor structure of the present invention, the nth trench exposes a surface of the substrate.
In an embodiment of the semiconductor structure of the present invention, the nth trench extends into the substrate.
In an embodiment of the semiconductor structure of the present invention, an included angle between a sidewall of each of the n trenches and the surface of the substrate is between 30 ° and 90 °.
In an embodiment of the semiconductor structure of the present invention, the n trenches have a total depth D, and the depth of each of the n trenches is between D/n ± 50%.
In one embodiment of the semiconductor structure of the present invention, the group III-V compound layer includes a gallium nitride layer.
The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming a III-V compound layer on a substrate; and sequentially forming n grooves which are communicated with each other up and down in the III-V group compound layer, wherein n is more than or equal to 2. Among the n trenches, a width of an uppermost 1 st trench decreases to a width of a lowermost nth trench, and the nth trench exposes a portion of the substrate.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the nth trench exposes a surface of the substrate.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the nth trench extends into the substrate.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, an included angle between a sidewall of each of the n trenches and the surface of the substrate is between 30 ° and 90 °.
In an embodiment of the method for fabricating a semiconductor structure of the present invention, the n trenches have a total depth D, and each of the n trenches has a depth between D/n ± 50%.
In one embodiment of the method of fabricating a semiconductor structure of the present invention, the III-V compound layer includes a gallium nitride layer.
In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the n trenches are formed in the order of the 1 st trench to the n-th trench.
Based on the above, in the present invention, a plurality of trenches that are communicated with each other up and down are formed in the III-V compound layer, and the lowermost trench exposes a portion of the substrate, i.e., the trenches penetrate the III-V compound layer, so that the stress between the III-V compound layer and the substrate can be effectively released.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIGS. 1A-1C are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the invention;
FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;
reference numerals:
100: substrate
102: III-V compound layer
104: first trench
106: second trench
108: third groove
D: thickness of
d1, d2, d 3: depth of field
θ 1, θ 2: included angle
Detailed Description
Fig. 1A to fig. 1C are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the invention. First, referring to fig. 1A, a substrate 100 is provided. The substrate 100 is, for example, a silicon substrate. Next, a III-V compound layer 102 is formed on the substrate 100. The III-V compound layer 102 is, for example, a gallium nitride layer. The III-V compound layer 102 is formed, for example, by an epitaxial growth process. In this embodiment, the III-V compound layer 102 has a thickness D. Further, in the present embodiment, the III-V compound layer 102 has a single-layer structure, but the present invention is not limited thereto. In other embodiments, the III-V compound layer 102 may also have a multilayer structure.
After the III-V compound layer 102 is formed on the substrate 100, stress may be generated at an interface between the III-V compound layer 102 and the substrate 100 due to lattice mismatch between the III-V compound layer 102 and the substrate 100. As a result, the subsequently formed device is easily damaged due to the stress. In particular, when the above problems occur in the main device region of the chip, the whole chip is discarded, which results in increased production cost. Accordingly, the present invention is directed to relieving stress due to lattice mismatch, which will be described in detail below.
Next, referring to fig. 1B, a first trench 104 is formed in the III-V compound layer 102. The bottom of the first trench 104 is located in the III-V compound layer 102, i.e., the first trench 104 does not penetrate the III-V compound layer 102. In the present embodiment, the first trench 104 has a depth d 1. The first trench 104 is formed, for example, by a patterning process, which is well known to those skilled in the art and will not be described herein.
Thereafter, referring to fig. 1C, a second trench 106 is formed in the III-V compound layer 102 exposed at the bottom of the first trench 104. In the present embodiment, the second trench 106 exposes the surface of the substrate 100, i.e., the first trench 104 and the second trench 106 penetrate the III-V compound layer 102. The second trench 106 is formed, for example, by a patterning process, which is well known in the art and will not be described herein. The second trench 106 has a depth d 2. That is, in the present embodiment, the sum of the depth D1 of the first trench 104 and the depth D2 of the second trench 106 is the thickness D of the III-V compound layer 102. In addition, since the second trench 106 is formed in the III-V compound layer 102 exposed at the bottom of the first trench 104, the width of the second trench 106 is smaller than that of the first trench 104. As a result, a step structure may be formed at the sidewalls of the first trench 104 and the second trench 106. The step structure can prevent a metal layer formed later from remaining, as will be described below.
In the present embodiment, the first trench 104 and the second trench 106 formed in the III-V compound layer 102 penetrate the III-V compound layer 102, so that the stress between the III-V compound layer 102 and the substrate 100 caused by lattice mismatch can be effectively released, and further damage of the subsequently formed devices due to the influence of the stress can be avoided.
In the present embodiment, the first trench 104 having a larger width is formed in the III-V compound layer 102, and then the second trench 106 having a smaller width is formed, so that the misalignment between the first trench 104 and the second trench 106 can be avoided. If the second trench 106 having a smaller width is formed first and then the first trench 104 having a larger width is formed, it is not easy to form the first trench 104 at a desired position because the second trench 106 has a smaller size.
In addition, in the present embodiment, the depth D1 of the first trench 104 and the depth D2 of the second trench 106 are each half of the sum (which may be regarded as the thickness D in the present embodiment) of the depth D1 of the first trench 104 and the depth D2 of the second trench 106 of the III-V compound layer 102, but the present invention is not limited thereto as long as the depth D1 of the first trench 104 and the depth D2 of the second trench 106 are each between (half of the sum of the depth D1 and the depth D2) ± 50%. In other words, when 2 grooves are formed in the III-V compound layer 102, the depth of each groove is between (the sum of the depth d1 and the depth d 2)/2 ± 50%.
Since the sidewalls of the 2 grooves in the III-V compound layer 102 have a step structure and the depth d1 and the depth d2 are each between (half of the sum of the depth d1 and the depth d 2) ± 50%, when a subsequent film is formed on the III-V compound layer 102 and covers the step structure, the film on the step structure can be easily and completely removed by an etching process, thereby preventing residues on the step structure. Particularly, when the film layer is a metal layer, if the metal layer remains on the step structure after the etching process, an induced current is generated at the remaining metal layer during the operation of other devices (especially high voltage devices), thereby affecting the device performance.
In the present embodiment, the second trench 106 exposes the surface of the substrate 100, but the present invention is not limited thereto. In other embodiments, the second trench 106 may also extend into the substrate 100. This will be explained below.
Fig. 2 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the invention. In the present embodiment, the same elements as those of fig. 1 will be denoted by the same reference numerals, and a description thereof will not be given.
Referring to fig. 2, in the present embodiment, the second trench 106 extends into the substrate 100. At this time, since 2 trenches are formed in the III-V compound layer 102, the depth d1 of the first trench 104 and the depth d2 of the second trench 106 are still between (the sum of the depth d1 and the depth d 2)/2 ± 50%, respectively.
That is, whether the second trench 106 exposes the surface of the substrate 100 or extends into the substrate 100, the depth d1 of the first trench 104 and the depth d2 of the second trench 106 both have to be between (the sum of the depth d1 and the depth d 2)/2 ± 50% to effectively prevent the film layer from remaining on the step structure formed by the first trench 104 and the second trench 106 in the subsequent process.
In addition, in the above embodiments, the sidewalls of the first trench 104 and the second trench 106 are perpendicular to the plane of the substrate 100, but the invention is not limited thereto.
FIG. 3 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. In the present embodiment, the same elements as those of fig. 1 will be denoted by the same reference numerals, and a description thereof will not be given.
Referring to fig. 3, in the present embodiment, an included angle θ 1 between a sidewall of the first trench 104 and the surface of the substrate 100 is between 30 ° and 90 °, and an included angle θ 2 between a sidewall of the second trench 106 and the surface of the substrate 100 is between 30 ° and 90 °. That is, the first trench 104 and the second trench 106 have sloped sidewalls. When the first trench 104 and the second trench 106 have inclined sidewalls, the film layer remaining on the step structure formed by the first trench 104 and the second trench 106 in the subsequent process can be more effectively avoided.
In the case where the first trench 104 and the second trench 106 have sloped sidewalls, the second trench 106 may also expose the surface of the substrate 100 or extend into the substrate 100 (as shown in fig. 2).
In each of the above embodiments, 2 grooves are formed in the III-V compound layer 102, but the present invention is not limited thereto. In other embodiments, more recesses may be formed in the III-V compound layer 102 depending on the actual requirements.
FIG. 4 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. In the present embodiment, the same elements as those of fig. 1 will be denoted by the same reference numerals, and a description thereof will not be given.
Referring to fig. 4, in the present embodiment, a first trench 104, a second trench 106 and a third trench 108 are formed in the III-V compound layer 102, and the third trench 108 is located between the first trench 104 and the second trench 106. The width of the third trench 108 is smaller than the width of the first trench 104 and larger than the width of the second trench 106. That is, the width of the uppermost trench decreases to the width of the lowermost trench. In addition, the second trench 106 exposes the surface of the substrate 100, i.e., the first trench 104, the second trench 106, and the third trench 108 penetrate the III-V compound layer 102. Since the first trench 104, the second trench 106 and the third trench 108 formed in the III-V compound layer 102 penetrate the III-V compound layer 102, the stress generated between the III-V compound layer 102 and the substrate 100 due to lattice mismatch can be effectively released, and further, damage of the subsequently formed devices due to the influence of the stress can be avoided.
In addition, in the present embodiment, 3 grooves are formed in the III-V compound layer 102, and thus the depth of each groove is between (the total depth of 3 grooves)/3 ± 50%. That is, the depth d1 of the first trench 104, the depth d2 of the second trench 106, and the depth d3 of the third trench 108 are all between (the sum of the depth d1, the depth d2, and the depth d 3)/3 ± 50%, so as to effectively prevent the film layer from remaining on the step structure formed by the first trench 104, the second trench 106, and the third trench 108 in the subsequent process.
Similarly, in other embodiments, the first trench 104, the second trench 106, and the third trench 108 may have sloped sidewalls, and the second trench 106 may also extend into the substrate 100 (as shown in fig. 2).
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (13)

1. A semiconductor structure, comprising:
a substrate; and
a III-V compound layer disposed on the substrate;
wherein the III-V group compound layer is provided with n grooves which are mutually communicated up and down, the width of the 1 st groove at the top to the width of the n groove at the bottom is decreased gradually, the n groove exposes a part of the substrate, and n is more than or equal to 2.
2. The semiconductor structure of claim 1, wherein the nth trench exposes a surface of the substrate.
3. The semiconductor structure of claim 1, wherein the nth trench extends into the substrate.
4. The semiconductor structure of claim 1, wherein an angle between a sidewall of each of the n trenches and the surface of the substrate is between 30 ° and 90 °.
5. The semiconductor structure of claim 1, wherein the n trenches have a total depth D, and each trench of the n trenches has a depth between D/n ± 50%.
6. The semiconductor structure of claim 1, wherein the III-V compound layer comprises a gallium nitride layer.
7. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a III-V compound layer on a substrate; and
sequentially forming n trenches in the III-V compound layer, the n trenches being in communication with each other,
among the n grooves, the width of the 1 st groove at the top to the width of the n groove at the bottom are decreased gradually, the n groove exposes a part of the substrate, and n is more than or equal to 2.
8. The method of fabricating a semiconductor structure according to claim 7, wherein the nth trench exposes a surface of the substrate.
9. The method of fabricating a semiconductor structure according to claim 7, wherein the nth trench extends into the substrate.
10. The method of claim 7, wherein an angle between a sidewall of each of the n trenches and the surface of the substrate is between 30 ° and 90 °.
11. The method of claim 7, wherein the n trenches have a total depth D, and each of the n trenches has a depth between D/n ± 50%.
12. The method of fabricating a semiconductor structure according to claim 7, wherein the group III-V compound layer comprises a gallium nitride layer.
13. The method for manufacturing a semiconductor structure according to claim 7, wherein the n trenches are formed in the order of the 1 st trench to the n-th trench.
CN202010869878.4A 2019-12-26 2020-08-26 Semiconductor structure and manufacturing method thereof Active CN113053996B (en)

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US20080261403A1 (en) * 2007-04-20 2008-10-23 Lattice Power (Jiangxi) Corporation Method for obtaining high-quality boundary for semiconductor devices fabricated on a partitioned substrate
US20110159615A1 (en) * 2009-12-28 2011-06-30 Hon Hai Precision Industry Co., Ltd. Led units fabrication method
CN102203968A (en) * 2008-09-25 2011-09-28 艾比维利股份有限公司 Group iii nitride semiconductor light emitting device
US20130015487A1 (en) * 2010-03-30 2013-01-17 Toyoda Gosei Co., Ltd. Semiconductor light-emitting device
US20130161643A1 (en) * 2011-12-27 2013-06-27 Mark Albert Crowder Method for Fabricating Three-Dimensional Gallium Nitride Structures with Planar Surfaces
US20180012770A1 (en) * 2016-03-03 2018-01-11 Gan Systems Inc. GaN-on-Si SEMICONDUCTOR DEVICE STRUCTURES FOR HIGH CURRENT/ HIGH VOLTAGE LATERAL GaN TRANSISTORS AND METHODS OF FABRICATION THEREOF

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JP3724110B2 (en) * 1997-04-24 2005-12-07 三菱電機株式会社 Manufacturing method of semiconductor device
JP3534624B2 (en) * 1998-05-01 2004-06-07 沖電気工業株式会社 Method for manufacturing semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080261403A1 (en) * 2007-04-20 2008-10-23 Lattice Power (Jiangxi) Corporation Method for obtaining high-quality boundary for semiconductor devices fabricated on a partitioned substrate
CN102203968A (en) * 2008-09-25 2011-09-28 艾比维利股份有限公司 Group iii nitride semiconductor light emitting device
US20110159615A1 (en) * 2009-12-28 2011-06-30 Hon Hai Precision Industry Co., Ltd. Led units fabrication method
US20130015487A1 (en) * 2010-03-30 2013-01-17 Toyoda Gosei Co., Ltd. Semiconductor light-emitting device
US20130161643A1 (en) * 2011-12-27 2013-06-27 Mark Albert Crowder Method for Fabricating Three-Dimensional Gallium Nitride Structures with Planar Surfaces
US20180012770A1 (en) * 2016-03-03 2018-01-11 Gan Systems Inc. GaN-on-Si SEMICONDUCTOR DEVICE STRUCTURES FOR HIGH CURRENT/ HIGH VOLTAGE LATERAL GaN TRANSISTORS AND METHODS OF FABRICATION THEREOF

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CN113053996B (en) 2023-07-28
TW202125698A (en) 2021-07-01
US11502195B2 (en) 2022-11-15
TWI725688B (en) 2021-04-21
US20210202739A1 (en) 2021-07-01

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