CN113051629B - An integrated circuit based on on-chip fuse to realize on-off PUF - Google Patents

Abstract

The invention discloses an integrated circuit based on an on-chip fuse to realize an on-off type PUF. Two completely identical on-chip fuses are connected in series between a power source and a ground, and the common ends of the two on-chip fuses are connected to a closed-circuit terminal. The drain-source resistance of the low-threshold MOS tube is used as a pull-up resistor or a pull-down resistor, and the common terminal is used as the output key value of the PUF; when a process deviation causes a certain on-chip fuse to blow first, the remaining unfused on-chip fuses will be used to connect the common The terminal is pulled up to the power supply or pulled down to the ground; and when the process deviation is small so that both on-chip fuses are blown, the output terminal will be pulled up to the power supply or pulled down to the ground by the drain-source resistance of the low-threshold MOS transistor that is turned off. The present invention is only composed of two on-chip fuses and one MOS transistor, and will be permanently fixed and directly output the key value after being fused once powered on, the structure is simple, and the key output speed is fast.

Description

An integrated circuit based on on-chip fuse to realize on-off PUF

technical field

The invention relates to a security chip key generation circuit, in particular to an integrated circuit that realizes an on-off type physical unclonable function PUF based on an on-chip fuse, and belongs to the technical field of information security integrated circuits.

Background technique

In the security chip, the physical unclonable function (PUF) is usually used to provide the key required for the security chip. The PUF detects the random changes in the physical properties of the materials constituting the circuit device during the production process of the integrated circuit, even if the chip is a chip. It is also impossible for manufacturers and circuit designers to use the same circuit to copy the exact same key, and the attacker cannot deduce the original key through reverse engineering. There are various PUF structures today, such as the transient effect ring oscillator type and Arbiter type PUF based on delay units, RO type PUF based on the difference of ring oscillator oscillation frequency, SRAM PUF based on minimum data hold voltage detection, based on resistive change However, these traditional PUFs sample the mismatch between the noise, resistance, oscillation frequency, delay, threshold voltage and other characteristics of the device or circuit, and are easily affected by voltage and temperature. , and new types of memory such as new magnetic random access memories are not compatible with standard CMOS processes and require special processing, which greatly increases the cost of chips. In addition, the post-production trimming of unstable PUF cells by a show of hands and an error correction code (Error Correction Code, ECC) will also bring about a large digital circuit overhead. Therefore, the existing traditional PUF has problems such as low stability and high calibration hardware cost.

In order to avoid the problem of low stability caused by the traditional PUF sampling the analog characteristics of the circuit or device, some studies have proposed an on-off (On-Off) type PUF. A very simple design scheme is to combine two metal The spacing of interconnect lines is reduced to less than the minimum spacing allowed by the process. In the actual production process of the chip, due to the limited resolution of the process lithography, it is possible to connect two interconnect lines together, and the connection probability is affected by the random deviation of the process. , the connection state of the two interconnecting lines will be randomly on or off after the actual chip is produced. This PUF implementation is not affected by temperature and environment. Whether the interconnect line is on or off is permanently determined after the chip is produced. It has 100% stability, and the implementation cost is very low, and no additional correction circuit is required. However, it should be pointed out that this implementation method is difficult to control the bias characteristics of the output key, and the connection state between the interconnecting lines is easily affected by the distance. If the distance is slightly farther, the two interconnecting lines have a high probability of not intersecting, while the distance is slightly closer. Then there is a high probability of intersection. It will be very difficult to obtain a 50% probability of intersection. The process itself needs to be analyzed and iterated many times to obtain a suitable spacing, and the situation of each casting will be different. Different process conditions must be realized. Convergence at the lower end is very difficult for the design and highly susceptible to process influences.

In order to obtain better bias characteristics, another effective way of implementing on-off PUF is to use on-chip wire fuse, that is, on-chip fuse fuse, to obtain a permanent and stable PUF key. Referring to the invention CN106952890A, a PUF scheme and circuit implementation based on the principle of internal wire fusing of the chip, a PUF scheme based on the principle of fusing internal wires of the chip is proposed. And fuse 2 are relatively narrow metal wires, they are connected by wider metal wires, and the left end of fuse 1 is connected to the power supply through switch S1, and the right end of fuse 2 is connected to ground through switch S2. The circuit first goes through the mismatch sampling stage, that is, S1 and S2 are turned on at the same time, and a path will be formed between the power and ground, resulting in a large current. Due to the mismatch between fuse 1 and fuse 2 in production, the fuse 1 and A metal wire in fuse 2 has a larger resistance and is easier to blow. In this way, when one of fuse 1 and fuse 2 is blown first, S1 and S2 are disconnected, S5 is closed, and S3 and S4 are closed respectively. By detecting whether there is current between S3 and S4, that is, whether there is current between the power supply and ground, further Detect which one of fuse 1 and fuse 2 is blown, and then use an encoding circuit to encode the blown situation of fuse 1 and fuse 2, and the final encoded value is the output key of the PUF.

This implementation can obtain bias characteristics that are less affected by the process, but it should be pointed out that since both fuses are blown, when both fuses are blown, their common terminal will be in a high-impedance state , the output value cannot be determined, so the public end of the two fuses cannot be directly output as a key, but only a complex current detection circuit and an encoding circuit can be used to realize the output of the PUF key. Therefore, after adopting a large number of switches, coding control circuits and current detection circuits to realize the on-off detection of the fuse, the circuit cost is greatly increased. At the same time, in order to obtain the output key value, each time the key is sampled, it takes multiple clock cycles to control the on-off control of S1, S2, S3, S4 and S5 respectively, which greatly reduces the key sampling and output. rate.

To sum up, it can be seen that the existing on-off PUF based on the on-chip fuse has the problems of poor bias characteristics, high circuit cost, and low sampling speed. It is necessary to find a stable, simple and efficient circuit structure to avoid a large number of Use of switches, detection circuits, and encoding to reduce circuit cost and increase sampling rate.

SUMMARY OF THE INVENTION

In view of the problems described in the background technology, the present invention proposes a simple integrated circuit of a high-stability on-off type PUF based on an on-chip fuse. First, the left and right ends of the two on-chip fuses are directly connected to the power supply and the ground, respectively. The public terminal is directly used as the output key value of the PUF. When the power is turned on, the two fuses will pass a large current. If the fuse connected to the power supply is blown, the common input terminal will be connected to the ground through the fuse connected to the ground. The output is 0; and when the fuse connected to the ground is blown, the common input terminal is connected to the power supply through the fuse connected to the power supply, and the output is 1. At the same time, in order to avoid the state where both fuses are blown and the common terminal is in a high-impedance state, the common output terminal is pulled down to the ground or pulled up to the power supply through a large resistance. When both fuses are blown, the common output terminal can be Pulled down to ground or pulled up to power with defined output value. The circuit does not need a switch to control, and does not need a current detection circuit and an encoding circuit to detect the fuse state. After power-on, it directly outputs a stable PUF key value. The circuit is simple, and the key sampling and output rate is fast.

In order to achieve the above object, the present invention adopts the following scheme:

An integrated circuit based on an on-chip fuse that realizes an on-off physical unclonable function PUF, characterized in that two identical on-chip fuses are connected in series between the power supply and the ground, and the two on-chip fuses are connected in common The terminal is connected to the drain-source resistance of the low-threshold MOS tube that is cut off as a pull-up resistor or pull-down resistor, and the common terminal is used as the output key value of the PUF; when a process deviation causes an on-chip fuse to blow first, the remaining unblown fuses will be blown first. The on-chip fuse pulls the common terminal up to the power supply or pulls it down to the ground; and when the process deviation is small so that both on-chip fuses are blown, the output terminal will be pulled up to the power supply or pulled down by the drain-source resistance of the low-threshold MOS transistor. land.

Further, the on-chip fuse is composed of metal or polysilicon conductive interconnect lines that are large at both ends and slender in the middle, and whose width is as low as the minimum size allowed by the process.

Further, the size and shape of the two on-chip fuses are exactly the same, and they are well matched during the layout process, and the environments of the two are exactly the same, so as to obtain random process deviations under the exact same design environment, and then Blows two fuses randomly.

Further, the pull-up resistor or pull-down resistor of the common terminal is respectively composed of a small-sized and low-threshold NMOS transistor or PMOS transistor that is turned off, and the chip area is reduced as much as possible while obtaining a higher up-down-down resistance value; a low-threshold NMOS transistor Or the PMOS tube has a relatively high drain-source impedance when it is cut off, which can effectively reduce the DC power consumption from the power supply to the ground when one fuse is blown, and can still provide higher power when both fuses are blown. Fast charge and discharge time.

Further, the width of the conductive interconnection between the common terminal and the pull-up resistor or the pull-down resistor is larger than the width of the on-chip fuse, so as to avoid the case of the conductive interconnection connected to the pull-up resistor or the pull-down resistor being blown.

The beneficial effects of the present invention are:

In the present invention, two identical on-chip fuses are directly connected in series with the power supply and the ground. Pull or pull down resistor, when the process deviation causes a fuse to blow first, the common terminal will be pulled up to the power supply or pulled down to the ground by the remaining unblown fuses; and when the process deviation is small, both fuses will be blown. , the drain-source resistance of the cut-off low-threshold MOS transistor will pull up the common terminal to the power supply or pull down to the ground. The invention has simple structure and high speed. First of all, it is only composed of two on-chip fuses and one MOS transistor, without additional switches, current detection circuits and encoding circuits, and the circuit is very simple. Secondly, the PUF will be permanently fixed and directly output the key value after one power-on and fuse. It does not require multiple clock cycles to sample and output the key, and the key sampling and output speed is fast.

Description of drawings

Fig. 1 is a kind of PUF scheme based on chip internal wire fusing principle proposed with reference to the invention patent;

Fig. 2 is a kind of circuit schematic diagram of the integrated circuit that realizes on-off type PUF based on on-chip fuse of the present invention;

Fig. 3 is a kind of layout of the integrated circuit that realizes on-off type PUF based on on-chip fuse of the present invention;

FIG. 4 is an equivalent circuit diagram of an integrated circuit fuse of an on-off type PUF based on an on-chip fuse of the present invention when the fuse is blown.

Detailed ways

The present invention is further described below with reference to the accompanying drawings and specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, but should not be construed as a limitation of the present invention, and any modifications, equivalent replacements, or Improvements, etc., should be included within the scope of the claims of the present invention, and those not described in detail in this technical solution are all known technologies.

Embodiment: Figure 2 and Figure 3 show an example of an integrated circuit implementing an on-off PUF based on an on-chip fuse of the present invention, wherein Figure 2 is a circuit principle, and Figure 3 is a layout layout. In FIG. 2 , fuse 1 and fuse 2 are two identical wires composed of on-chip interconnecting wires. The two ends are large and the middle is narrow and long. The width of the long thin wire in the middle is the minimum width allowed by the process. The specific layout is shown in Figure 3. One end of the fuse 1 is connected to the power supply, the other end is connected to one end of the fuse 2 to form a common terminal, and the other end of the fuse 2 is connected to the ground. The common terminal of the two fuses is used as the output terminal of the PUF, and the default potential of the common terminal can be determined in two ways: (1) As shown in Figure 2(a) and Figure 3(a), the common terminal is passed through The pull-down resistor formed by the cut-off low-threshold NMOS transistor determines the default potential to be 0; (2) As shown in Figures 2(b) and 3(b), the common terminal is pulled up by the cut-off low-threshold PMOS tube. The resistor determines the default potential to be 1. In FIG. 3 , the width of the interconnection line connected to the pull-up and pull-down resistors is larger than the width of the long thin line in the middle of the fuse, so as to prevent the interconnection line from being blown first during the fusing process.

Taking Fig. 2(a) and Fig. 3(a) as an example, during circuit design and layout, fuse 1 and fuse 2 and their external environment are completely consistent, but due to the process deviation in the actual production process of the chip , the electrical and thermal characteristics of the two fuses have random deviations. After power-on, the power supply at the left end of fuse 1 and the right end of fuse 2 form a path, and a large current will form in the fuse. If the long-line resistance is higher, fuse 1 will be blown first. Since the low-threshold NMOS tube drain-source resistance of the cut-off is much larger than the resistance of fuse 2, the output end will be pulled down from fuse 2 to ground, and the output will be 0. Its equivalent circuit diagram is shown in the figure below. Figure 4(a) shows. On the contrary, if the slender wire resistance of fuse 2 is higher after the chip is produced, then fuse 2 will be blown first. At this time, the output terminal will be pulled up by fuse 1 to the power supply, and the output will be 1. Its equivalent circuit diagram is shown in Figure 4 (b). ) shown. In addition, if the process deviation of fuse 1 and fuse 2 is not large, it is possible that both fuses are blown. At this time, the drain-source resistance of the low-threshold NMOS transistor that is turned off is pulled down to ground, and the output is still 0. Its equivalent circuit diagram is shown in Figure 4(c).

It should be pointed out that the reason why the low-threshold NMOS transistor drain-source resistance of the cut-off is used as the pull-down resistor is because at the cut-off, the drain-source end of the NMOS transistor is equivalent to an open circuit, and its drain-source resistance is large, which can save a very small area cost. Under the premise, obtain a larger pull-down resistor. The low threshold NMOS is used because when both fuses are blown, if a normal threshold NMOS is used, its drain-source resistance is very large when it is cut off, even greater than the fuse impedance after the fuse, so there is a discharge from the output to the ground. The longer time even leads to the risk of unknown output voltage. When the low-threshold NMOS is turned off, its drain-source resistance is relatively large, but it is much smaller than the drain-source resistance when the normal threshold NMOS is turned off, so that it can obtain higher pull-down resistance and lower static power consumption when fuse 2 is blown. A shorter output discharge time can also be obtained when both fuses are blown at the same time.

The situations shown in Figures 2(b) and 3(b) are similar to the above, except that when both fuses are blown, the drain-source resistance of the off PMOS tube is pulled up to the power supply by default, and the output is 1.

It can be seen that after adopting the above-mentioned on-off PUF structure based on the on-chip fuse, the whole circuit is only composed of 2 interconnecting wire fuses and 1 MOS with a very small area, without the need for switches, current detection circuits and coding circuits. After power-on and fusing, the circuit will be permanently fixed, no clock control is required, and the output key sampling and output speed is fast, which will greatly increase its application range.

The above description is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited to this. The equivalent replacement or change of the inventive concept thereof shall be included within the protection scope of the present invention.

Claims (5)

1. An integrated circuit for realizing an on-off Physical Unclonable Function (PUF) based on-chip fuses is characterized in that two completely consistent on-chip fuses are connected between a power supply and the ground in series, a cut-off low-threshold MOS (metal oxide semiconductor) tube drain-source resistor is connected to a common end of the two on-chip fuses to serve as a pull-up resistor or a pull-down resistor, and the common end serves as an output key value of the PUF; when the process deviation causes that a fuse wire on a certain chip is firstly fused, the common terminal is pulled up to a power supply or pulled down to the ground by the fuse wires on the rest un-fused chips; and when the process deviation is small, so that the two on-chip fuses are all fused, the output end is pulled up to a power supply or pulled down to the ground through the cut-off drain-source resistor of the low-threshold MOS tube.

2. An integrated circuit implementing a Physically Unclonable Function (PUF) of the on-off type based on-chip fuses as claimed in claim 1, characterized in that the on-chip fuses are formed by metal or polysilicon conductive interconnects with large ends and slender middle, and the width is as low as the minimum size allowed by the process.

3. The integrated circuit for realizing the on-off Physical Unclonable Function (PUF) based on the on-chip fuses as claimed in claim 1, wherein the size and the shape of the two on-chip fuses are completely consistent, the two on-chip fuses are well matched in the layout process, and the two on-chip fuses are completely consistent in environment, so that random process deviation is obtained under the completely same design environment, and the two fuses are randomly blown.

4. The integrated circuit for realizing the on-off Physical Unclonable Function (PUF) based on the on-chip fuse as claimed in claim 1, wherein the pull-up resistor or the pull-down resistor of the common terminal is respectively composed of a cut-off small-size low-threshold NMOS transistor or PMOS transistor, and the chip area is reduced as much as possible while a higher pull-up and pull-down resistance value is obtained; the low-threshold NMOS tube or the PMOS tube has a proper high drain-source impedance when being cut off, the direct current power consumption from a power supply to the ground can be effectively reduced under the condition that one fuse wire is fused, and the quick charging and discharging time can still be provided under the condition that two fuse wires are fused.

5. The integrated circuit for realizing the PUF based on the on-chip fuse, according to claim 1, wherein the width of the conductive interconnection line connecting the common terminal with the pull-up resistor or the pull-down resistor is larger than that of the on-chip fuse, so as to avoid the situation that the conductive interconnection line connecting the pull-up resistor or the pull-down resistor is blown.

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