CN113050363B - Method for establishing optical proximity correction model and optical proximity correction method - Google Patents
Method for establishing optical proximity correction model and optical proximity correction method Download PDFInfo
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- CN113050363B CN113050363B CN201911380295.9A CN201911380295A CN113050363B CN 113050363 B CN113050363 B CN 113050363B CN 201911380295 A CN201911380295 A CN 201911380295A CN 113050363 B CN113050363 B CN 113050363B
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- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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Abstract
A method for establishing an optical proximity correction model comprises the steps of providing a wafer layout figure and an initial test figure, obtaining light intensity parameter information of the wafer layout figure and the initial test figure, comparing the light intensity parameter information of the wafer layout figure and the light intensity parameter information of the initial test figure, judging whether the light intensity parameter information of the initial test figure covers the light intensity parameter information of the wafer layout figure, taking the initial test figure as the test figure when the light intensity parameter information of the wafer layout figure covers the light intensity parameter information, taking the figure corresponding to the light intensity parameter information which is missing of the initial test figure as the new added figure when the light intensity parameter information is not covered, adding the new added figure into the initial test figure to obtain the test figure, and establishing the optical proximity correction model corresponding to the wafer layout figure according to the test figure. The test patterns in the optical proximity correction model can better represent wafer layout patterns, so that the accuracy of optical proximity correction is improved.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to an establishment method of an optical proximity correction model and an optical proximity correction method.
Background
Photolithography is a technique of paramount importance in semiconductor fabrication technology, which enables transferring patterns from a reticle to a silicon wafer to form a semiconductor product that meets design requirements.
In semiconductor manufacturing, as the design dimensions continue to shrink, the diffraction effect of light becomes more and more pronounced, resulting in optical image degradation of the design pattern, and severe distortion of the actual lithographic pattern relative to the pattern on the reticle, resulting in the actual pattern being formed lithographically on the wafer and the design pattern being different, a phenomenon known as optical proximity effect (Optical Proximity Effect, OPE).
In order to correct for optical proximity effects, optical proximity correction (Optical Proximity Correction, OPC) is generated. The core idea of the optical proximity correction is to build an optical proximity correction model based on the consideration of canceling the optical proximity effect, and design a photomask pattern according to the optical proximity correction model, so that although the optical proximity effect occurs in the corresponding photomask pattern, since the cancellation of the phenomenon is already considered when designing the photomask pattern according to the optical proximity correction model, the lithographic pattern after lithography is close to the target pattern that the user actually wants.
Disclosure of Invention
The problem solved by the embodiment of the invention is to provide an establishment method of an optical proximity correction model and an optical proximity correction method, which improve the accuracy of optical proximity correction.
In order to solve the problems, the embodiment of the invention provides a method for establishing an optical proximity correction model, which comprises the steps of providing a wafer layout pattern and an initial test pattern, obtaining the light intensity parameter information of the wafer layout pattern, obtaining the light intensity parameter information of the initial test pattern, comparing the light intensity parameter information of the wafer layout pattern with the light intensity parameter information of the initial test pattern, judging whether the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer layout pattern, taking the initial test pattern as a test pattern when the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer layout pattern, taking a pattern corresponding to the light intensity parameter information which is missing from the initial test pattern as a new pattern when the light intensity parameter information of the wafer layout pattern is not covered by the light intensity parameter information of the initial test pattern, adding the new pattern into the initial test pattern to obtain the test pattern, and establishing the optical proximity correction model corresponding to the wafer layout pattern according to the test pattern.
Optionally, before the light intensity parameter information of the wafer layout pattern and the light intensity parameter information of the initial test pattern are obtained, an initial optical proximity correction model is provided, the step of obtaining the light intensity parameter information of the wafer layout pattern comprises the steps of performing simulated exposure on the wafer layout pattern by using the initial optical proximity correction model, drawing a space light intensity distribution curve of the wafer layout pattern after performing simulated exposure on the wafer layout pattern, extracting the light intensity parameter information of the wafer layout pattern from the space light intensity distribution curve of the wafer layout pattern, and the step of obtaining the light intensity parameter information of the initial test pattern comprises the steps of performing simulated exposure on the initial test pattern by using the initial optical proximity correction model, drawing the space light intensity distribution curve of the initial test pattern after performing simulated exposure on the initial test pattern, and extracting the light intensity parameter information of the initial test pattern from the space light intensity distribution curve of the initial test pattern.
Optionally, the spatial light intensity distribution curve is a spatial light intensity distribution of a best focus plane.
Optionally, the light intensity parameter information comprises a plurality of spatial light intensity parameters, before comparing the light intensity parameter information of the wafer layout pattern with the light intensity parameter information of the initial test pattern, the method further comprises the steps of selecting at least two of the plurality of spatial light intensity parameters in the wafer layout pattern, establishing a first coordinate system, selecting at least two of the plurality of spatial light intensity parameters in the initial test pattern, establishing a second coordinate system, and comparing the light intensity parameter information of the wafer layout pattern with the light intensity parameter information of the initial test pattern by utilizing the first coordinate system and the second coordinate system.
Optionally, the light intensity parameter information comprises three spatial light intensity parameters, the first coordinate system and the second coordinate system are three-dimensional space coordinate systems, the step of comparing the light intensity parameter information of the wafer layout pattern with the light intensity parameter information of the initial test pattern comprises projecting the first coordinate system and the second coordinate system into the same two-dimensional plane coordinate system, and the step of judging whether the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer layout pattern comprises the step of judging whether the light intensity parameter information of the initial test pattern does not cover the light intensity parameter information of the wafer layout pattern if the area range of the spatial light intensity parameter of the wafer layout pattern is located in the area range of the spatial light intensity parameter of the initial test pattern in the same two-dimensional plane coordinate system.
Optionally, the three-dimensional space coordinate system comprises an X axis, a Y axis and a Z axis which are perpendicular to each other, and the step of projecting the first coordinate system and the second coordinate system into the same two-dimensional plane coordinate system comprises the step of sequentially projecting the first coordinate system and the second coordinate system into the X-Y plane coordinate system, the X-Z plane coordinate system and the Y-Z plane coordinate system.
Optionally, the spatial light intensity parameter of the light intensity parameter information includes one or more of a light intensity maximum value, a light intensity minimum value and a normalized image logarithmic slope.
Optionally, before the light intensity parameter information of the wafer layout pattern is obtained, the method further comprises the steps of grouping the wafer layout pattern to obtain multiple groups of patterns with the same light intensity parameter information, and obtaining the light intensity parameter information of each group of patterns with the same light intensity parameter information in the step of obtaining the light intensity parameter information of the wafer layout pattern.
Optionally, the initial optical proximity correction model includes an optical model and a photoresist model, the photoresist model including a photoresist exposure reference threshold.
Correspondingly, the embodiment of the invention also provides an optical proximity correction method, which comprises the steps of providing an optical proximity correction model obtained by the method, providing a wafer layout figure, and carrying out optical proximity correction on the wafer layout figure according to the optical proximity correction model.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
Before an optical proximity correction model corresponding to a wafer layout pattern is established, acquiring the optical intensity parameter information of the wafer layout pattern and the optical intensity parameter information of an initial test pattern, comparing the optical intensity parameter information of the wafer layout pattern with the optical intensity parameter information of the initial test pattern to judge whether the optical intensity parameter information of the initial test pattern covers the optical intensity parameter information of the wafer layout pattern, wherein when the optical intensity parameter information of the initial test pattern covers the optical intensity parameter information of the wafer layout pattern, the initial test pattern is used as a test pattern, when the optical intensity parameter information of the initial test pattern does not cover the optical intensity parameter information of the wafer layout pattern, the pattern corresponding to the optical intensity parameter information which is missing of the initial test pattern is used as a new pattern, and adding the new pattern into the initial test pattern to obtain the test pattern.
Drawings
FIG. 1 is a schematic diagram of a linewidth error between a simulated linewidth of a wafer layout pattern and an actual linewidth of a corresponding physical wafer pattern after optical proximity correction is performed by an optical proximity correction model established by a method for establishing an optical proximity correction model;
FIG. 2 is a flowchart of an embodiment of a method for creating an optical proximity correction model according to the present invention;
FIG. 3 is a schematic view of the spatial light intensity distribution curve of any one of the wafer layout patterns in the embodiment of FIG. 2;
FIG. 4 is a three-dimensional coordinate system corresponding to the light intensity parameter information of the wafer layout pattern in the embodiment shown in FIG. 2;
FIG. 5 is a three-dimensional coordinate system corresponding to the light intensity parameter information of the initial test pattern in the embodiment shown in FIG. 2;
FIG. 6 is a schematic diagram of the embodiment of FIG. 2 comparing the light intensity parameter information of the wafer layout pattern with the light intensity parameter information of the initial test pattern;
Fig. 7 is a schematic diagram of a linewidth error between a simulated linewidth of a wafer layout pattern and an actual linewidth of a corresponding physical wafer pattern after optical proximity correction using the optical proximity correction model established by the method shown in fig. 2.
Detailed Description
The establishment of the optical proximity correction model requires test patterns which can be used for representing wafer layout patterns, such as the shape, the size, the environment of the patterns and the like of the wafer layout patterns, and when the optical proximity correction model is established, enough test patterns are selected for different line widths (CDs) and pitches (pitch), so that the optical proximity correction accuracy of the wafer layout patterns with different line widths and pitches is higher.
When the optical proximity correction model is built, the initial optical proximity model is generally utilized to perform simulated exposure on the test pattern to obtain the simulated line width of the test pattern, meanwhile, the test pattern is transferred onto the physical wafer by utilizing a photoetching process, the actual line width of the test pattern corresponding to the physical wafer is collected, and then the initial optical proximity model is optimized according to the simulated line width and the line width error of the actual line width to obtain the final optical proximity model.
The qualified optical proximity model not only can enable the linewidth error corresponding to the test pattern to be smaller, but also can enable the linewidth error of the wafer layout pattern to be smaller.
After the optical proximity correction model is established by the current method for establishing the optical proximity correction model, the linewidth error of the wafer layout pattern is larger when the optical proximity correction model is applied to the wafer layout pattern although the linewidth error corresponding to the test pattern is smaller.
Fig. 1 shows a schematic diagram of linewidth error between a simulated linewidth of a wafer layout pattern and an actual linewidth of a corresponding physical wafer pattern after optical proximity correction is performed by using an optical proximity correction model established by a current method for establishing an optical proximity correction model. As shown in fig. 1, the line width error between the simulated line width of the wafer layout pattern and the actual line width of the corresponding physical wafer pattern is as high as about 8nm, so that the accuracy of optical proximity correction is low.
Currently, one way is to add more test patterns to meet different demands on pattern type, line width and pitch, in an attempt to increase the accuracy of the built optical proximity correction model for optical proximity correction by adding a data pool. However, even if a larger number of test patterns are used to construct the optical proximity correction model, the linewidth error between the simulated linewidth of the wafer layout pattern and the actual linewidth of the corresponding physical wafer pattern is still high. Moreover, increasing the data pool correspondingly results in increased data collection time, the number of line width measurement devices, and the demand of modeling hardware or software, and lower process feasibility.
In order to solve the technical problems, the embodiment of the invention provides an establishing method of an optical proximity correction model, which comprises the steps of providing a wafer layout figure and an initial test figure, obtaining the light intensity parameter information of the wafer layout figure, obtaining the light intensity parameter information of the initial test figure, comparing the light intensity parameter information of the wafer layout figure with the light intensity parameter information of the initial test figure, judging whether the light intensity parameter information of the initial test figure covers the light intensity parameter information of the wafer layout figure, wherein when the light intensity parameter information of the initial test figure covers the light intensity parameter information of the wafer layout figure, the initial test figure is used as a test figure, when the light intensity parameter information of the initial test figure does not cover the light intensity parameter information of the wafer layout figure, taking the figure corresponding to the light intensity parameter information of the initial test figure as a new added figure, adding the new added figure into the initial test figure to obtain the test figure, and establishing the optical proximity correction model corresponding to the wafer layout figure according to the test figure.
According to the invention, after the optical proximity correction model is established according to the test pattern, the test pattern in the optical proximity correction model can better represent the wafer layout pattern, and when the optical proximity correction is carried out according to the optical proximity correction model, the accuracy of the optical proximity correction is higher, and correspondingly, the error between the simulated line width of the wafer layout pattern and the actual line width of the corresponding physical wafer pattern is smaller.
Referring to fig. 2, a flowchart of an embodiment of a method for creating an optical proximity correction model according to the present invention is shown. The method for establishing the optical proximity correction model in the embodiment comprises the following basic steps:
Step S1, providing a wafer layout pattern and an initial test pattern;
S2, acquiring light intensity parameter information of the wafer layout graph;
S3, acquiring light intensity parameter information of the initial test pattern;
S4, comparing the light intensity parameter information of the wafer layout pattern with the light intensity parameter information of the initial test pattern;
s5, judging whether the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer layout pattern or not;
S6, when the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer layout pattern, the initial test pattern is used as a test pattern;
s7, when the light intensity parameter information of the initial test pattern does not cover the light intensity parameter information of the wafer layout pattern, taking the pattern corresponding to the light intensity parameter information which is missing in the initial test pattern as an added pattern, and adding the added pattern into the initial test pattern to obtain a test pattern;
and S8, establishing an optical proximity correction model corresponding to the wafer layout graph according to the test graph.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring to fig. 2, step S1 is performed to provide a wafer layout pattern and an initial test pattern.
The wafer layout pattern is a preset pattern in an actual design chip which needs to be generated in the photoetching mask plate, and the wafer layout pattern is used for manufacturing the photoetching mask plate of the actual design chip. And transferring the wafer layout pattern to a physical wafer for production by using the photoetching mask plate.
The physical wafer comprises a plurality of chip areas which are arranged in an array, and cutting lines are arranged between the adjacent chip areas. In this embodiment, the wafer layout pattern is used to expose a photoresist pattern that forms a single chip area.
And the wafer layout graph is stored in an original layout file. The original layout file refers to a layout file containing design graphics, which is designed and formed by using an EDA tool. Typically, the original layout file is a layout file that passed DRC (design rule check) verification.
As an example, the file format of the original layout is GDS format. In other embodiments, the file format of the original layout may be other formats such as OASIS.
In this embodiment, the wafer layout pattern is a pattern to be processed, and after an optical proximity correction model corresponding to the wafer layout pattern is established, optical proximity correction needs to be performed on the wafer layout pattern.
In this embodiment, the number of the wafer layout patterns is plural, so the method for establishing the optical proximity correction model further includes performing pattern grouping on the wafer layout patterns to obtain multiple groups of patterns with the same light intensity parameter information.
And acquiring the light intensity parameter information of the wafer layout patterns, so that the similar wafer layout patterns are classified into the same group of patterns by performing pattern grouping on the wafer layout patterns, and the data acquisition amount when the light intensity parameter information is acquired is reduced. Correspondingly, when the light intensity parameter information of the wafer layout patterns is obtained later, the light intensity parameter information of all wafer layout patterns in each group of homotype patterns does not need to be collected, so that the efficiency of establishing the optical proximity correction model is improved.
Specifically, similar wafer layout patterns are grouped by a pattern grouping tool.
The initial test pattern is the same as the wafer layout pattern, or the initial test pattern comprises a part of the wafer layout pattern, that is, at least a part of the wafer layout pattern can find the pattern corresponding to the initial test pattern in the initial test pattern.
The initial test pattern is used to prepare for forming the test pattern.
The test pattern is used for representing a wafer layout pattern and is used as a set of all types of actual design chips used under the current manufacturing technology level or node. And the optical proximity correction model is built by using the test pattern, and the test pattern is beneficial to enabling the optical proximity correction model built later to have wider adaptability so as to be convenient for meeting the requirements of almost all actual design chips.
In this embodiment, the method for establishing the optical proximity correction model further includes providing an initial optical proximity correction model.
And establishing an optical proximity correction model corresponding to the wafer layout pattern according to the test pattern and the initial optical proximity correction model. And the initial optical proximity correction model is used for carrying out subsequent simulated exposure on the wafer layout graph and the initial test graph.
The initial Optical proximity correction Model includes an Optical Model (Optical Model) and a photoresist Model (CTR Model), the photoresist Model including a photoresist exposure reference threshold. The optical model is built according to various parameters of an optical lens system, such as numerical aperture, exposure wavelength, type, thickness, refractive index, extinction coefficient and the like of a photoresist layer stack, and the photoresist model is built according to parameters of a photoresist exposure reference threshold (namely minimum energy required in photoresist exposure) and the like.
In this embodiment, when the photoresist material is known, the photoresist exposure reference threshold is fixed, so that the minimum energy required for photoresist exposure can be obtained.
With continued reference to fig. 2, step S2 is performed to obtain the light intensity parameter information of the wafer layout pattern.
The light intensity parameter information of the wafer layout pattern is used for being compared with the light intensity parameter information of the initial test pattern, so that whether the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer layout pattern or not is judged, and whether the initial test pattern can be used for representing the wafer layout pattern in the process of establishing the optical proximity correction model or not is judged.
The method comprises the steps of obtaining light intensity parameter information of a wafer layout pattern, namely performing simulated exposure on the wafer layout pattern by using the initial optical proximity correction model, drawing a space light intensity distribution curve of the wafer layout pattern after performing simulated exposure on the wafer layout pattern, and extracting the light intensity parameter information of the wafer layout pattern from the space light intensity distribution curve of the wafer layout pattern.
In this embodiment, the spatial light intensity distribution curve is the spatial light intensity distribution of the optimal focusing plane, and the photoresist is located on the optimal focusing plane relative to the defocused plane, so that the optimal critical dimension can be obtained, which is beneficial to forming a better quality pattern on the physical wafer in the following process.
As shown in fig. 3, fig. 3 shows a schematic diagram of a spatial light intensity distribution curve of any one wafer layout pattern. Wherein, the abscissa represents the imaging position of the wafer layout graph, the ordinate represents the normalized light intensity, and the solid line represents the light intensity threshold (T). Wherein, the zero point of the abscissa represents the center point of the wafer layout graph.
In this embodiment, the spatial light intensity parameter of the light intensity parameter information includes one or more of a light intensity maximum value (Imax), a light intensity minimum value (Imin), and a Normalized Image Log Slope (NILS).
The spatial light intensity parameter of the light intensity parameter information is not limited to the above-mentioned type. In other embodiments, the spatial light intensity parameter may further include a slope (K), ILS (image log slope), or Normalized Slope (NS), etc. at the light intensity threshold position.
As an example, the light intensity parameter information of the wafer layout pattern includes a plurality of spatial light intensity parameters (AERIAL PARAMETER). Specifically, the light intensity parameter information of the wafer layout graph comprises three light intensity parameters, namely a light intensity maximum value, a light intensity minimum value and a normalized image logarithmic slope.
In the embodiment, before the light intensity parameter information of the wafer layout patterns is obtained, the method further comprises the step of grouping the wafer layout patterns to obtain a plurality of groups of patterns with the same light intensity parameter information. Therefore, in the step of acquiring the light intensity parameter information of the wafer layout pattern, the light intensity parameter information of each group of the patterns with the same type is acquired.
That is, for each group of homotypic patterns, the light intensity parameter information of all wafer layout patterns in the homotypic patterns is not required to be acquired, so that the data acquisition amount when the light intensity parameter information is acquired is reduced, and the efficiency of establishing the optical proximity correction model is further improved.
For example, one wafer layout pattern is arbitrarily selected from each group of pattern patterns, and the light intensity parameter information of the selected wafer layout pattern is obtained and used for representing the light intensity parameter information of all wafer layout patterns in the pattern patterns.
In this embodiment, after the light intensity parameter information of the wafer layout pattern is obtained, the method for establishing the optical proximity correction model further includes selecting at least two of a plurality of spatial light intensity parameters in the wafer layout pattern, and establishing a first coordinate system.
And establishing a first coordinate system so as to prepare for the subsequent comparison of the light intensity parameter information.
In this embodiment, the light intensity parameter information of the wafer layout pattern includes three spatial light intensity parameters, so the first coordinate system is a three-dimensional spatial coordinate system.
Specifically, the three-dimensional space coordinate system includes an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other.
As shown in fig. 4, fig. 4 shows a three-dimensional space coordinate system corresponding to the light intensity parameter information of the wafer layout pattern. The X-axis represents the intensity maximum (Imax), the Y-axis represents the intensity minimum (Imin), and the Z-axis represents the Normalized Image Log Slope (NILS).
The dark graph in fig. 4 is used for representing the distribution of the light intensity parameter information of the wafer layout graph in the three-dimensional space coordinate system, and the light graph is used for representing the projection of the light intensity parameter information in each two-dimensional plane coordinate system.
With continued reference to fig. 2, step S3 is performed to obtain the light intensity parameter information of the initial test pattern.
The light intensity parameter information of the initial test pattern is used for being compared with the light intensity parameter information of the wafer layout pattern, so that whether the initial test pattern covers all types of patterns in the wafer layout pattern is judged.
The method comprises the steps of obtaining light intensity parameter information of an initial test pattern, namely performing simulated exposure on the initial test pattern by using the initial optical proximity correction model, drawing a spatial light intensity distribution curve of the initial test pattern after performing simulated exposure on the initial test pattern, and extracting the light intensity parameter information of the initial test pattern from the spatial light intensity distribution curve of the initial test pattern.
In this embodiment, the spatial light intensity parameter of the light intensity parameter information includes one or more of a light intensity maximum value, a light intensity minimum value, and a normalized image logarithmic slope.
As an example, the light intensity parameter information of the initial test pattern includes a plurality of spatial light intensity parameters. Specifically, the light intensity parameter information of the initial test pattern includes three light intensity parameters, namely a light intensity maximum value, a light intensity minimum value and a normalized image logarithmic slope.
For detailed description of the step of obtaining the light intensity parameter information of the initial test pattern, reference may be made to the foregoing description of obtaining the light intensity parameter information of the wafer layout pattern, which is not repeated herein.
In this embodiment, after the light intensity parameter information of the initial test pattern is obtained, the method for establishing the optical proximity correction model further includes selecting at least two of the plurality of spatial light intensity parameters in the initial test pattern, and establishing a second coordinate system.
And establishing a second coordinate system so as to prepare for the subsequent comparison of the light intensity parameter information.
In this embodiment, the light intensity parameter information of the initial test pattern includes three spatial light intensity parameters, and therefore, the second coordinate system is a three-dimensional spatial coordinate system.
Specifically, the three-dimensional space coordinate system includes an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other.
As shown in fig. 5, fig. 5 shows a three-dimensional space coordinate system corresponding to the light intensity parameter information of the initial test pattern. The X-axis represents the maximum intensity, the Y-axis represents the minimum intensity, and the Z-axis represents the normalized image log slope.
The dark graph in fig. 5 is used for representing the distribution of the light intensity parameter information of the initial test graph in the three-dimensional space coordinate system, and the light graph is used for representing the projection of the light intensity parameter information in each two-dimensional plane coordinate system.
With continued reference to fig. 2, step S4 is performed to compare the light intensity parameter information of the wafer layout pattern with the light intensity parameter information of the initial test pattern.
And judging whether the initial test pattern can be used for representing all types of patterns in the wafer layout pattern or not according to the comparison result of the light intensity parameter information of the wafer layout pattern and the light intensity parameter information of the initial test pattern.
In this embodiment, in the foregoing step, at least two of the plurality of spatial light intensity parameters in the wafer layout pattern are selected to establish a first coordinate system, and at least two of the plurality of spatial light intensity parameters in the initial test pattern are selected to establish a second coordinate system, so that the light intensity component parameter information of the wafer layout pattern and the light intensity parameter information of the initial test pattern are compared by using the first coordinate system and the second coordinate system.
And comparing the first coordinate system with the second coordinate system to judge whether any space light intensity parameter of the wafer layout pattern is positioned in the range of the corresponding space light intensity parameter in the initial test pattern, so that whether the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer layout pattern can be intuitively judged.
In this embodiment, the step of comparing the light intensity parameter information of the wafer layout pattern with the light intensity parameter information of the initial test pattern includes projecting the first coordinate system and the second coordinate system into the same two-dimensional plane coordinate system.
By projecting the first and second coordinate systems into the same two-dimensional planar coordinate system, the amount of calculation when comparing the light intensity parameter information is reduced, and comparison is easier.
Specifically, the three-dimensional space coordinate system includes an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other, and therefore, the step of projecting the first coordinate system and the second coordinate system into the same two-dimensional plane coordinate system includes projecting the first coordinate system and the second coordinate system into the X-Y plane coordinate system, the X-Z plane coordinate system, and the Y-Z plane coordinate system in order.
As shown in fig. 6, fig. 6 is a schematic diagram illustrating comparison between the light intensity parameter information of the wafer layout pattern and the light intensity parameter information of the initial test pattern. Taking the projection of the first coordinate system and the second coordinate system to an X-Y plane coordinate system as an example, the X axis represents the maximum light intensity (Imax), the Y axis represents the minimum light intensity (Imin), the triangle pattern is used for representing the light intensity parameter information of the initial test pattern, and the diamond pattern is used for representing the light intensity parameter information of the wafer layout pattern.
It should be noted that, in other embodiments, the comparison of the light intensity parameter information may also be performed by using a three-dimensional space coordinate system.
With continued reference to fig. 2, step S5 is executed to determine whether the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer layout pattern.
And when the light intensity parameter information of the initial test pattern does not cover the light intensity parameter information of the wafer layout pattern, executing a step S7, taking a pattern corresponding to the light intensity parameter information which is missing from the initial test pattern as an added pattern, and adding the added pattern into the initial test pattern to obtain the test pattern.
When the light intensity parameter information of the initial test pattern does not cover the light intensity parameter information of the wafer layout pattern, the pattern corresponding to the light intensity parameter information which is missing from the initial test pattern is used as a new pattern, and the new pattern is added into the initial test pattern to obtain a test pattern, so that after an optical proximity correction model is established according to the test pattern, the test pattern in the optical proximity correction model can be used for representing the wafer layout pattern, and when the optical proximity correction is carried out according to the optical proximity correction model, the accuracy of the optical proximity correction is higher, and correspondingly, the error between the simulation line width of the wafer layout pattern and the actual line width of the corresponding physical wafer pattern is smaller.
The method comprises the steps of judging whether the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer pattern or not, wherein in the same two-dimensional plane coordinate system, if the area range of the light intensity parameter of the wafer pattern is located in the area range of the light intensity parameter of the initial test pattern, the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer pattern, and if the area range of the light intensity parameter of the wafer pattern exceeds the area range of the light intensity parameter of the initial test pattern, the light intensity parameter information of the initial test pattern does not cover the light intensity parameter information of the wafer pattern.
As shown in fig. 6, taking the projection of the first coordinate system and the second coordinate system to the X-Y plane coordinate system as an example, the X-axis represents the maximum light intensity (Imax), the Y-axis represents the minimum light intensity (Imin), the triangle pattern is used to represent the light intensity parameter information of the initial test pattern, and the diamond pattern is used to represent the light intensity parameter information of the wafer layout pattern. As can be seen from fig. 6, the area where the light intensity parameter of the wafer layout pattern is located exceeds the area where the light intensity parameter of the initial test pattern is located, that is, the light intensity parameter information representing the initial test pattern does not cover the light intensity parameter information of the wafer layout pattern.
As an example, the missing part of the light intensity parameter information of the initial test pattern is indicated by a solid circle in fig. 6.
It should be noted that, in order to verify whether the light intensity parameter information of the test pattern covers the light intensity parameter information of the wafer layout pattern after the new pattern is added to the initial test pattern to obtain the test pattern, the light intensity parameter information of the wafer layout pattern and the light intensity parameter information of the test pattern may be compared again, so as to ensure that the light intensity parameter information of the test pattern completely covers the light intensity parameter information of the wafer layout pattern.
With continued reference to fig. 2, step S8 is executed to establish an optical proximity correction model corresponding to the wafer layout pattern according to the test pattern.
The light intensity parameter information of the test pattern covers the light intensity parameter information of the wafer layout pattern, so that after the optical proximity correction model is established according to the test pattern, the test pattern in the optical proximity correction model can better represent the wafer layout pattern, and after the optical proximity correction is carried out according to the optical proximity correction model, the accuracy of the optical proximity correction is higher, and correspondingly, the error between the simulated line width of the wafer layout pattern and the actual line width of the corresponding physical wafer pattern is smaller.
Specifically, in order to further improve the accuracy of the optical proximity correction, the optical proximity correction model is a model-based optical proximity correction model.
Correspondingly, the embodiment also provides an optical proximity correction method, which comprises the steps of providing an optical proximity correction model obtained by the method in the previous embodiment, providing a wafer layout figure, and carrying out optical proximity correction on the wafer layout figure according to the optical proximity correction model.
From the foregoing description, the test patterns in the optical proximity correction model can better represent the wafer layout patterns, so that the accuracy of optical proximity correction is high after optical proximity correction is performed according to the optical proximity correction model.
Fig. 7 is a schematic diagram of linewidth error between a simulated linewidth of a wafer layout pattern and an actual linewidth of a corresponding physical wafer pattern after optical proximity correction is performed by using an optical proximity correction model established by the method of the present embodiment. As shown in fig. 7, the maximum value of the line width error between the simulated line width of the wafer layout pattern and the actual line width of the corresponding physical wafer pattern is reduced from about 3nm to about 8nm, so that the accuracy of the optical proximity correction is high.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (9)
1. The method for establishing the optical proximity correction model is characterized by comprising the following steps of:
Providing a wafer layout pattern and an initial test pattern;
Acquiring light intensity parameter information of the wafer layout pattern, and acquiring light intensity parameter information of the initial test pattern, wherein the light intensity parameter information comprises a plurality of space light intensity parameters;
Selecting at least two of a plurality of space light intensity parameters in the wafer layout graph, establishing a first coordinate system, selecting at least two of a plurality of space light intensity parameters in the initial test graph, and establishing a second coordinate system;
Comparing the light intensity parameter information of the wafer layout pattern with the light intensity parameter information of the initial test pattern, wherein the step of comparing the light intensity parameter information of the wafer layout pattern with the light intensity parameter information of the initial test pattern comprises the steps of projecting the first coordinate system and the second coordinate system into the same two-dimensional plane coordinate system;
Judging whether the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer layout pattern, wherein in the same two-dimensional plane coordinate system, if the area range of the space light intensity parameter of the wafer layout pattern is positioned in the area range of the space light intensity parameter of the initial test pattern, the light intensity parameter information of the initial test pattern covers the light intensity parameter information of the wafer layout pattern, the initial test pattern is taken as a test pattern, and if the area range of the space light intensity parameter of the wafer layout pattern exceeds the area range of the space light intensity parameter of the initial test pattern, the light intensity parameter information of the initial test pattern does not cover the light intensity parameter information of the wafer layout pattern, the pattern corresponding to the light intensity parameter information which is deleted by the initial test pattern is taken as a new pattern, and the new pattern is added into the initial test pattern to obtain the test pattern;
and establishing an optical proximity correction model corresponding to the wafer layout pattern according to the test pattern.
2. The method of claim 1, wherein prior to obtaining the light intensity parameter information of the wafer layout pattern and the light intensity parameter information of the initial test pattern, further comprising providing an initial optical proximity correction model;
The step of obtaining the light intensity parameter information of the wafer layout pattern comprises the steps of performing simulated exposure on the wafer layout pattern by using the initial optical proximity correction model, drawing a space light intensity distribution curve of the wafer layout pattern after performing simulated exposure on the wafer layout pattern;
the step of obtaining the light intensity parameter information of the initial test pattern comprises the steps of performing simulated exposure on the initial test pattern by using the initial optical proximity correction model, drawing a spatial light intensity distribution curve of the initial test pattern after performing simulated exposure on the initial test pattern, and extracting the light intensity parameter information of the initial test pattern from the spatial light intensity distribution curve of the initial test pattern.
3. The method of claim 2, wherein the spatial light intensity distribution curve is a spatial light intensity distribution of a best focus plane.
4. The method of claim 1, wherein the light intensity parameter information comprises three spatial light intensity parameters;
the first coordinate system and the second coordinate system are three-dimensional space coordinate systems.
5. The method of claim 4, wherein the three-dimensional spatial coordinate system includes an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other;
the step of projecting the first and second coordinate systems into the same two-dimensional planar coordinate system comprises projecting the first and second coordinate systems into an X-Y planar coordinate system, an X-Z planar coordinate system and a Y-Z planar coordinate system in sequence.
6. The method of any one of claims 1 to 5, wherein the spatial light intensity parameter of the light intensity parameter information includes one or more of a light intensity maximum, a light intensity minimum, and a normalized image log slope.
7. The method of claim 1, further comprising, prior to obtaining the light intensity parameter information of the wafer layout pattern, performing pattern grouping on the wafer layout pattern to obtain a plurality of groups of homotypic patterns, wherein the light intensity parameter information of the homotypic patterns is the same;
in the step of obtaining the light intensity parameter information of the wafer layout patterns, one wafer layout pattern is arbitrarily selected from each group of the same type patterns, and the light intensity parameter information of the selected wafer layout pattern is obtained.
8. The method of claim 2, wherein the initial optical proximity correction model comprises an optical model and a photoresist model, the photoresist model comprising a photoresist exposure reference threshold.
9. An optical proximity correction method, comprising:
providing an optical proximity correction model obtained by the method of any one of claims 1 to 8;
providing a wafer layout figure;
and carrying out optical proximity correction on the wafer layout graph according to the optical proximity correction model.
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| CN114488721B (en) * | 2022-03-15 | 2023-08-11 | 福建省晋华集成电路有限公司 | Optical proximity correction method, optical proximity correction device, electronic equipment and storage medium |
| CN114415467B (en) * | 2022-03-29 | 2022-07-05 | 合肥晶合集成电路股份有限公司 | Method and system for acquiring optical proximity effect correction model |
| CN115457350B (en) * | 2022-11-08 | 2023-04-18 | 华芯程(杭州)科技有限公司 | Optical proximity correction etching model training method and optical proximity correction method |
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| CN104614930A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Method for establishing OPC model and optical proximity correction method for user target graphs |
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| CN103149792A (en) * | 2011-12-07 | 2013-06-12 | 无锡华润上华科技有限公司 | Optical proximity correction method |
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| CN104614930A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Method for establishing OPC model and optical proximity correction method for user target graphs |
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