CN113037372B - Time-triggered passive optical bus and implementation method thereof - Google Patents

Abstract

The invention discloses a time-triggered passive optical bus and an implementation method thereof, and relates to the field of light-based time-triggered buses. , a second optical bus connector, a plurality of optical bus terminal controllers, a first optical splitter and a second optical splitter; each optical bus terminal controller has two ports, and the two ports are connected to two Optical splitter; each optical bus connector has 2 optical fiber ports, one port of the first optical bus connector is connected to the first optical splitter, and one port of the second optical bus connector is connected to the second optical splitter , the other port of the first optical bus connector is connected to the other port of the second optical bus connector, and a corresponding implementation method is provided at the same time, which realizes a reduction in the weight of the body and the difficulty of wiring, strong anti-interference ability and avoidance of The cold start phase sends the collided bus.

Description

A time-triggered passive optical bus and its realization method

technical field

The invention relates to the field of light-based time-triggered buses, in particular to a time-triggered passive optical bus and an implementation method thereof.

Background technique

Optical fiber is short for optical fiber. Optical fiber communication is a communication method in which light waves are used as information carriers and optical fibers are used as transmission media. In principle, the basic material elements that constitute optical fiber communication are optical fibers, light sources and photodetectors. Optical fiber communication is a communication method in which light waves are used as carriers and optical fibers are used as transmission media to transmit information from one place to another. It is called "wired" optical communication. Today, optical fiber is far superior to the transmission of cable and microwave communication because of its transmission frequency bandwidth, high anti-interference and low signal attenuation, and has become the main transmission method in world communication.

The communication organization mode of TTA (Time-Triggered Architecture, time-triggered architecture) is realized by TDMA (Time Division Multiple Address), and each communication device sends information in a designated time slot (slot) on the time axis. The TTA architecture is based on a global synchronous clock and uses a pre-designed static global scheduling list to drive data transmission in TDMA mode, independent of external events. This transmission mode enables TTA to provide data transmission services between devices with minimal jitter and predictable delay, and avoid bus collisions. There are many technologies for realizing the time-triggered architecture in the prior art, among which the patent number CN103850802A and the patent name are: The patent of the electronic controller based on the time-triggered protocol TTP/C bus and the FADEC system discloses an electronic controller based on the TTP/C bus. The controller, and the connection relationship between the controller and various functional modules, through the electronic controller of the TTP/C bus, realizes the redundancy of the TTP/C bus, completes the time synchronization function, and exchanges data between the functional sub-boards.

At present, for the time-triggered architecture bus protocol, most of them use the TTP/C protocol, which is completed with the cable as the medium. And general cable links such as RS485, CAN speed is limited, it is difficult to meet the high-speed data transmission requirements. At the same time, the cable is heavier than the optical fiber, and the cable that is too long will increase the overall weight of the fuselage. And due to the characteristics of the bus, conflict avoidance has also become a problem that needs to be considered. The configuration of Configuration Data is cumbersome and needs to be configured one by one.

SUMMARY OF THE INVENTION

The invention discloses a time-triggered passive optical bus, which aims to provide a bus that is lighter in weight, improves bandwidth, and avoids collision in the cold start stage.

In order to solve the above problems, the present invention has adopted the following technical solutions:

A time-triggered passive optical bus includes a first optical bus connector, a second optical bus connector, a plurality of optical bus terminal controllers, a first optical splitter and a second optical splitter; each optical bus The terminal controller has two ports, and the two ports are respectively connected to the first optical splitter and the second optical splitter; each optical bus connector has 2 optical fiber ports, and one port of the first optical bus connector is connected In the first optical splitter, one port of the second optical bus connector is connected to the second optical splitter, and the other port of the first optical bus connector is connected to the other port of the second optical bus connector.

Each of the optical bus connectors is provided with an optical bus connector state control unit, and each of the optical bus terminal controllers is provided with an optical bus terminal controller state control unit.

The invention also discloses a method for realizing a time-triggered passive optical bus, which is applied to the above-mentioned time-triggered passive optical bus. The bus includes two optical bus connectors and a plurality of optical bus terminal controllers. , two optical splitters, the optical bus connectors are all provided with an optical bus connector state control unit, the optical bus terminal controllers are all provided with an optical bus terminal controller state control unit, two optical bus connectors Denoted as the first optical bus connector and the second optical bus connector, and the two optical splitters are denoted as the first optical splitter and the second optical splitter, including the following steps:

S1: Initialize the device, load the optical bus connector state control unit and the optical bus terminal controller state control unit;

S2: Open the state control logic of the optical bus connector state control unit or the optical bus terminal controller state control unit;

S3: Wait for the link topology to be generated, and wait for the link time parameter measurement to be completed;

S4: Complete the configuration of the optical bus terminal controller, and complete the cold start process;

S5: Maintain the link topology and perform OTTB_FRAME transmission.

Preferably, the state control logic of the optical bus connector state control unit includes the following steps:

Step 010: By default, the first optical bus connector is used to send configuration data, which is sent to each node through the first optical splitter, and the second optical bus connector forwards the configuration data from the first optical bus connector to the second optical bus connector. Splitter, and complete the measurement of the link delay information of the second optical splitter, set the local member vector to 0, initialize the local clock of the device to 0, use a local clock globally, and use the Micro Clock as the minimum clock for the local clock cycle;

Step 020: The first optical bus connector cyclically sends the T_SYNC_FRAME frame to the connected first optical splitter and the second optical bus connector, and the two optical bus connectors respectively record the sending time t1 at which they send the T_SYNC_FRAME frame, and start at the same time Timing, waiting for the corresponding device to respond or the response times out; the optical bus connector receives the N_RESP_FRAME frame from the corresponding device, stops the timing, and records the time t2 when the N_RESP_FRAME frame is currently received. The two optical bus connectors calculate their respective link delays Parameter T_wiredelay=(t2-t1-t_cost)/2, where t_cost is the time spent by the optical bus terminal controller to process T_SYNC_FRAME;

Step 030: Wait for the completion of the traversal detection of all network devices in the current network, and send the configuration information and the link delay parameters respectively measured by the two optical splitters to the optical bus terminal controller;

Step 040: Fill the member vector field in the ALLOW_COLDSTART_FRAME frame with the local member vector;

Step 050: Detect and maintain topology;

The state control logic of the optical bus terminal controller state control unit includes the following steps:

Step 110: Set the member vectors of all devices, set the corresponding position of its Membership Flag to 1, other positions to 0, and initialize the local clock of the device to 0;

Step 120: Monitor whether there is a T_SYNC_FRAME frame from the optical bus connector on the two links respectively, and the member vector in the frame is the same as the member vector value of the device itself, and use the time information of the T_SYNC_FRAME frame sent by the first optical bus connector to synchronize. The local clock processes the T_SYNC_FRAME frames of the two links respectively. When any link receives the T_SYNC_FRAME frame, it immediately sends the response message N_RESP_FRAME through the link;

Step 130: The optical bus terminal controller that has completed the response monitors its own configuration information on the link, and after verifying its own configuration information, if the verification passes, it returns CON_ACK, and if the verification fails, it returns CON_FAIL;

Step 140: After listening to the ALLOW_COLDSTART_FRAME frame, all the optical bus terminal controllers receive the member vector containing the global view of the current network, so far the cold start process is completed, and all the optical bus terminal controllers that receive the ALLOW_COLDSTART_FRAME frame The link delay of the optical bus connector is set at the same time, and the current integration cycle is set to 0. After reaching the global time GLOBAL_RESTART_POINT_TIME, the local clock is reset to 0, and then normal communication is realized according to the configuration information;

Step 150: Each optical bus terminal controller forming the group sends the TIME_TRIGGER_FRAME time-triggered traffic according to the local planned time scale, and uses the GMP algorithm and the distributed clock algorithm to complete the maintenance of the topology.

Preferably, the step 010 includes the following steps:

Step 011: Initialize the local clock, if the system contains a GPS device, synchronize the local GPS_CLOCK counter to the GPS device, and clear the local counter to 0; if the system does not contain an external clock source, only clear the local clock counter to 0;

Step 012: Set the sending member vector to 64'h0000_0001, that is, the target device this time is the device whose member vector is 64'h0000_0001; set the local member vector to 64'h0000_0000.

Preferably, the step 020 includes the following steps:

Step 021: the first optical bus connector sends a T_SYNC_FRAME frame containing the sending member vector to the first optical splitter and the second optical bus connector respectively, records the sending time t1 and starts the Link_latency_measure_count counter;

Step 022: Shift 1 in the sending member vector to the left by one, and wait for the next sending;

Step 023: wait for the N_RESP_FRAME message responded by the corresponding device, if the first optical bus connector receives the correct N_RESP_FRAME message, then set the corresponding position of the local member vector;

Step 024: Calculate the link delay parameter T_wiredelay=(t2-t1-t_cost)/2 according to the time point t2 when the N_RESP_FRAME message is received, and the known optical bus terminal controller processing and calculating the time t_cost of the T_SYNC_FRAME frame;

Step 025: If all devices in the system have been traversed and detected, jump to the step 030, otherwise go back to the step 021.

Preferably, the step 030 includes the following steps:

Step 031: Check the devices whose member variable is 1 in the local member vector, and send their respective Configuration Data information and link time parameters to these optical bus terminal controllers. The link time parameters include two parts, one part is the control of each optical bus terminal. The link delay between the connector and the optical bus connector, and the other part is the internal processing delay of the optical bus connector;

Step 032: After the optical bus terminal controller replies with the CON_ACK information or exceeds the maximum number of reconfiguration times, the optical bus terminal controller configures the next optical bus terminal controller.

Preferably, the step 040 includes the following steps:

Step 041: use the local member vector as the member vector field in the ALLOW_COLDSTART_FRAME frame, use the GPS_CLOCK variable as the GPS information field in the ALLOW_COLDSTART_FRAME frame, and send the ALLOW_COLDSTART_FRAME frame;

Step 042: After sending the ALLOW_COLDSTART_FRAME frame, clear the local clock, and then reset the local clock to 0 after the local clock normally timed to GLOBAL_RESTART_POINT_TIME, and then implement normal communication according to the configuration information.

Preferably, the step 050 includes the following steps:

Step 051: For the multiple optical bus terminal controllers that do not exist in the original group, the measurement of the link time parameters and the configuration data information are completed in the respective first Node Slots after the multiple optical bus terminal controllers are powered on. Configure and broadcast the link time parameters to all other devices in their respective Node Slots;

Step 052: The unqualified OTTB_FRAME sent by the optical bus terminal controller is not forwarded by the optical bus connector and a WARNING primitive warning is issued.

Preferably, the step 150 includes the following steps:

Step 151: If the ALLOW_COLDSTART_FRAME frame is received, the member vector in the ALLOW_COLDSTART_FRAME frame is added to its own local member vector, and if a non-ALLOW_COLDSTART_FRAME frame is received, its own integration operation is completed;

Step 152: Each optical bus terminal controller sends a data frame in its own Node Slot, and updates the local member vector according to the GMP algorithm.

The invention has high link rate, reduces the weight of the fuselage, reduces the difficulty of wiring, the anti-interference ability of the optical fiber is strong, and the overall anti-interference ability of the system is improved; at the same time, the uplink and downlink wavelengths are different, which provides a cooling system that can avoid conflicts. Startup method: Compared with the TTP/C protocol, which requires offline measurement of the link-related time parameter information in advance, the optical bus connector will measure the link time parameter in real time, which realizes the online measurement of the time parameter and simplifies the calculation of the link parameter. ; In addition, the optical bus connector completes the loading of the Configuration Data of all online devices at one time, and increases the monitoring of the status of the optical bus terminal controller, while simplifying the measurement of link time parameters.

Description of drawings

1 is a schematic structural diagram of a time-triggered passive optical bus according to Embodiment 1;

Fig. 2 is the flow chart of the realization method of the present invention in embodiment 2;

Fig. 3 is the frame format diagrams such as T_SYNC_FRAME, N_RESP_FRAME, ALLOW_COLDSTART_FRAME, OTTB_FRAME in Embodiment 3 and Embodiment 4;

Fig. 4 is the CON_ACK, CON_FAIL and WARNING primitive format diagram in embodiment 3 and embodiment 4;

Fig. 5 is the state control logic flow chart of the optical bus connector state control unit of embodiment 3;

Fig. 6 is the state control logic flow chart of the optical bus terminal controller state control unit of embodiment 4;

FIG. 7 is a schematic structural diagram of a conventional time-triggered bus technology.

Detailed ways

Example 1

A time-triggered passive optical bus structure in this embodiment is shown in FIG. 1 , including a first optical bus connector, a second optical bus connector, a plurality of optical bus terminal controllers, a first optical splitter, and a first optical bus connector. Two optical splitters; each optical bus terminal controller has two ports, and the two ports are respectively connected to the first optical splitter and the second optical splitter; each optical bus connector has 2 fiber ports, One port of the first optical bus connector is connected to the first optical splitter, one port of the second optical bus connector is connected to the second optical splitter, and the other port of the first optical bus connector is connected to the second optical bus connected to the other port of the device.

The optical bus connectors are all provided with an optical bus connector state control unit, and the optical bus terminal controllers are all provided with an optical bus terminal controller state control unit.

In this embodiment, the optical bus terminal controller 4 is a device with cold start capability, and when the optical bus terminal controller 4 is powered on, the optical bus connector state control unit works normally. Distinguish from the respective member vectors in the optical bus connector, specifically, the local member vector of the optical bus terminal controller 4 is described as NL_MV4, the transmission member vector of the optical bus connector is described as TS_MV1, and the local member vector of the optical bus connector is described as TS_MV1. The member vector is described as TL_MV1, and the initial value of the transmit member vector of the optical bus connector is set to 64'h0001 and the initial value of the local member vector is 64'h0000_0000. The initial value of TL_MV1 of optical bus terminal controller 1 is 64'h0000_0001, the initial value of TL_MV2 of optical bus terminal controller 2 is 64'h0000_0002, the initial value of TL_MV3 of optical bus terminal controller 3 is 64'h0000_0004, the optical bus terminal controller The initial value of TL_MV4 of 4 is 64'h0000_0008, and the initial value of TL_MV5 of the optical bus terminal controller 5 is 64'h0000_0010. The optical bus terminal controller 5 is powered on after the TTPON system is formed for a period of time. Rule setting A person skilled in the art can freely set according to needs. The setting rules are different, and the order of receiving configuration files is not used, but it does not affect the formation, maintenance and normal time trigger traffic of the entire network.

Example 2

A method for implementing a time-triggered passive optical bus, which can be applied to a time-triggered passive optical bus in Embodiment 1. The bus includes two optical bus connectors, multiple optical bus terminal controllers, and two optical branches. The optical bus connector is equipped with an optical bus connector state control unit, and the optical bus terminal controller is equipped with an optical bus terminal controller state control unit. The two optical bus connectors are marked as the first optical bus connector and the second optical bus connector. Two optical bus connectors, the two optical splitters are denoted as the first optical splitter and the second optical splitter, and the work flow chart shown in Figure 2 includes the following steps:

S1: Initialize the device, load the optical bus connector state control unit and the optical bus terminal controller state control unit;

S2: Open the state control logic of the optical bus connector state control unit or the optical bus terminal controller state control unit;

S3: Wait for the link topology to be generated, and wait for the link time parameter measurement to be completed;

S4: Complete the configuration of the optical bus terminal controller, and complete the cold start process;

S5: Maintain the link topology and perform OTTB_FRAME transmission.

Example 3

Referring to FIG. 5 , this embodiment is based on the method flow of Embodiment 2, wherein the state control logic of the optical bus connector state control unit includes the following steps:

Step 010: By default, the first optical bus connector is used to send configuration data, which is sent to each node through the first optical splitter, and the second optical bus connector forwards the configuration data from the first optical bus connector to the second optical bus connector. Splitter, and complete the measurement of the link delay information of the second optical splitter, set the local member vector to 0, initialize the local clock of the device to 0, use a local clock globally, and use the Micro Clock as the minimum clock for the local clock cycle;

Step 020: The first optical bus connector cyclically sends the T_SYNC_FRAME frame to the connected first optical splitter and the second optical bus connector, and the two optical bus connectors respectively record the sending time t1 at which they send the T_SYNC_FRAME frame, and start at the same time Timing, waiting for the corresponding device to respond or the response times out; the optical bus connector receives the N_RESP_FRAME frame from the corresponding device, stops the timing, and records the time t2 when the N_RESP_FRAME frame is currently received. The two optical bus connectors calculate their respective link delays Parameter T_wiredelay=(t2-t1-t_cost)/2, where t_cost is the time spent by the optical bus terminal controller to process T_SYNC_FRAME;

Step 030: Wait for the completion of the traversal detection of all network devices in the current network, and send the configuration information and the link delay parameters respectively measured by the two optical splitters to the optical bus terminal controller;

Step 040: Fill the member vector field in the ALLOW_COLDSTART_FRAME frame with the local member vector;

Step 050: Detect and maintain topology.

Preferably, step 010 includes the following steps:

Step 011: Initialize the local clock, if the system contains a GPS device, synchronize the local GPS_CLOCK counter to the GPS device, and clear the local counter to 0; if the system does not contain an external clock source, only clear the local clock counter to 0;

Step 012: Set the sending member vector to 64'h0000_0001, that is, the target device this time is the device whose member vector is 64'h0000_0001; set the local member vector to 64'h0000_0000.

Preferably, step 020 includes the following steps:

Step 021: the first optical bus connector sends a T_SYNC_FRAME frame containing the sending member vector to the first optical splitter and the second optical bus connector respectively, records the sending time t1 and starts the Link_latency_measure_count counter;

Step 022: Shift 1 in the sending member vector to the left by one, and wait for the next sending;

Step 023: wait for the N_RESP_FRAME message responded by the corresponding device, if the first optical bus connector receives the correct N_RESP_FRAME message, then set the corresponding position of the local member vector;

Step 024: Calculate the link delay parameter T_wiredelay=(t2-t1-t_cost)/2 according to the time point t2 when the N_RESP_FRAME message is received, and the known optical bus terminal controller processing and calculating the time t_cost of the T_SYNC_FRAME frame;

Step 025: If all devices in the system have been traversed and detected, go to Step 030, otherwise go back to Step 021.

Preferably, step 030 includes the following steps:

Step 031: Check the devices whose member variable is 1 in the local member vector, and send their respective Configuration Data information and link time parameters to these optical bus terminal controllers. The link time parameters include two parts, one part is the control of each optical bus terminal. The link delay between the connector and the optical bus connector, and the other part is the internal processing delay of the optical bus connector;

Step 032: After the optical bus terminal controller replies with the CON_ACK information or exceeds the maximum number of reconfiguration times, the optical bus terminal controller configures the next optical bus terminal controller.

Preferably, step 040 includes the following steps:

Step 041: use the local member vector as the member vector field in the ALLOW_COLDSTART_FRAME frame, use the GPS_CLOCK variable as the GPS information field in the ALLOW_COLDSTART_FRAME frame, and send the ALLOW_COLDSTART_FRAME frame;

Step 042: After sending the ALLOW_COLDSTART_FRAME frame, clear the local clock, and then reset the local clock to 0 after the local clock normally timed to GLOBAL_RESTART_POINT_TIME, and then implement normal communication according to the configuration information.

Preferably, step 050 includes the following steps:

Step 051: For the multiple optical bus terminal controllers that do not exist in the original group, the measurement of the link time parameters and the configuration data information are completed in the respective first Node Slots after the multiple optical bus terminal controllers are powered on. Configure and broadcast the link time parameters to all other devices in their respective Node Slots;

Step 052: The unqualified OTTB_FRAME sent by the optical bus terminal controller is not forwarded by the optical bus connector and a WARNING primitive warning is issued.

Example 4

Referring to FIG. 6, this embodiment is based on the method of Embodiment 2, wherein the state control logic of the state control unit of the optical bus terminal controller includes the following steps:

Step 110: Set the member vectors of all devices, set the corresponding position of its Membership Flag to 1, other positions to 0, and initialize the local clock of the device to 0;

Step 120: Monitor whether there is a T_SYNC_FRAME frame from the optical bus connector on the two links respectively, and the member vector in the frame is the same as the member vector value of the device itself, and use the time information of the T_SYNC_FRAME frame sent by the first optical bus connector to synchronize. The local clock processes the T_SYNC_FRAME frames of the two links respectively. When any link receives the T_SYNC_FRAME frame, it immediately sends the response message N_RESP_FRAME through the link;

Step 130: The optical bus terminal controller that has completed the response monitors its own configuration information on the link, and after verifying its own configuration information, if the verification passes, it returns CON_ACK, and if the verification fails, it returns CON_FAIL;

Step 140: After listening to the ALLOW_COLDSTART_FRAME frame, all the optical bus terminal controllers receive the member vector containing the global view of the current network, so far the cold start process is completed, and all the optical bus terminal controllers that receive the ALLOW_COLDSTART_FRAME frame The link delay of the optical bus connector is set at the same time, and the current integration cycle is set to 0. After reaching the global time GLOBAL_RESTART_POINT_TIME, the local clock is reset to 0, and then normal communication is realized according to the configuration information;

Step 150: Each optical bus terminal controller forming the group sends the TIME_TRIGGER_FRAME time-triggered traffic according to the local planned time scale, and uses the GMP algorithm and the distributed clock algorithm to complete the maintenance of the topology.

Further, step 150 includes the following steps:

Step 151: If the ALLOW_COLDSTART_FRAME frame is received, the member vector in the ALLOW_COLDSTART_FRAME frame is added to its own local member vector, and if a non-ALLOW_COLDSTART_FRAME frame is received, its own integration operation is completed;

Step 152: Each optical bus terminal controller sends a data frame in its own Node Slot, and updates the local member vector according to the GMP algorithm.

It should be noted that the frame format diagram of frames T_SYNC_FRAME, N_RESP_FRAME, ALLOW_COLDSTART_FRAME and OTTB_FRAME in this embodiment and Embodiment 3 is shown in FIG. 3 , and the format diagram of CON_ACK, CON_FAIL and WARNING primitives is shown in FIG. 4 .

In addition, a member vector is a set of vectors composed of bits, each of which corresponds to a controller. When a bit is 1, it means that the controller corresponding to the bit is working normally, so this embodiment uses "member vector" The controller whose least significant bit is 1" is used as the clock measure.

Compared with the existing time-triggered bus technology, the schematic diagram of the existing time-triggered bus technology is shown in Figure 7. If device 1 and device 2 are far away from device 4 and device 5, and device 1 and device 5 send cold start almost simultaneously frame, the following situation may occur, that is, device 2 receives a cold start frame from device 1, device 4 receives a cold start frame from device 5, but the two cold start frames collide at device 3 , Device 3 detected a collision. If the above situation occurs, it will lead to an extreme situation, that is, device 2 completes the integration using the cold start frame from device 1, device 4 completes the integration using the cold start frame from device 5, and the second device 3 cannot be due to the collision. Complete the integration. This approach formed two small groups. At the same time, for the bus shown in Figure 7, each device needs to be configured with Configuration Data, which also makes the configuration cumbersome.

In this method, the rough synchronization of the remaining optical bus terminal controllers is completed in advance through the optical bus connector, and ALLOW_COLDSTART_FRAME is sent through the optical bus connector to make the clocks of each node reach an agreement, so as to avoid the cold start scheme of small groups. At the same time, the optical bus connector realizes the configuration of one machine to multiple machines by means of unified configuration. The optical bus connector fault warning mechanism is realized by utilizing the characteristics of full-duplex communication of the optical fiber link.

Claims (7)

1. A method for realizing time-triggered passive optical bus is characterized in that,

the time-triggered passive optical bus comprises a first optical bus connector, a second optical bus connector, a plurality of optical bus terminal controllers, a first optical splitter and a second optical splitter; each optical bus terminal controller is provided with two ports which are respectively connected to the first optical splitter and the second optical splitter; each optical bus connector is provided with 2 optical fiber ports, one port of the first optical bus connector is connected with the first optical splitter, one port of the second optical bus connector is connected with the second optical splitter, and the other port of the first optical bus connector is connected with the other port of the second optical bus connector;

the optical bus connectors are provided with optical bus connector state control units, and the optical bus terminal controllers are provided with optical bus terminal controller state control units;

the implementation method of the time-triggered passive optical bus comprises the following steps:

s1: the device comprises an initialization device, a state control unit of an optical bus connector and a state control unit of an optical bus terminal controller are loaded;

s2: opening the state control logic of the state control unit of the optical bus connector or the state control unit of the optical bus terminal controller;

s3: waiting for generating a link topology and waiting for the completion of link time parameter measurement;

s4: completing the configuration of the optical bus terminal controller and completing the cold start process;

s5: maintaining a link topology, and transmitting OTTB _ FRAME;

the state control logic of the optical bus connector state control unit comprises the steps of,

step 010: the method comprises the steps that a first optical bus connector is used for sending configuration data in a default mode, the configuration data are issued to each node through a first optical splitter, a second optical bus connector forwards the configuration data from the first optical bus connector to a second optical splitter, measurement of link delay information of the second optical splitter is completed, a local member vector is set to be 0, a local Clock of initialization equipment is set to be 0, a local Clock is used globally, and the local Clock takes Micro Clock as a minimum Clock period;

step 020: the first optical bus connector circularly sends T _ SYNC _ FRAME FRAMEs to the connected first optical splitter and the second optical bus connector, the two optical bus connectors respectively record the sending time T1 of the T _ SYNC _ FRAME FRAMEs, and meanwhile, timing is started to wait for the response of corresponding equipment or response timeout; the method comprises the steps that an optical bus connector receives an N _ RESP _ FRAME FRAME of corresponding equipment, timing is stopped, the time T2 of the current N _ RESP _ FRAME FRAME is recorded, two optical bus connectors respectively calculate a link delay parameter T _ wiredelay which is (T2-T1-T _ cost)/2, wherein T _ cost is the time spent by an optical bus terminal controller in processing T _ SYNC _ FRAME;

step 030: waiting for the completion of traversal detection of all network equipment in the current network, and sending configuration information and link delay parameters obtained by respectively measuring two optical splitters to an optical bus terminal controller;

step 040: populating a member vector field in an ALLOW _ COLDSTART _ FRAME FRAME with a local member vector;

step 050: detecting and maintaining topology;

the state control logic of the state control unit of the optical bus terminal controller comprises the following steps:

step 110: setting member vectors of all devices, setting the corresponding position of the self Membership Flag to be 1, setting other positions to be 0, and initializing a local clock of the device to be 0;

step 120: monitoring whether T _ SYNC _ FRAME FRAMEs from the optical bus connectors exist on the two links respectively, wherein member vectors in the FRAMEs are the same as member vector values of equipment, synchronizing local clocks by using time information of the T _ SYNC _ FRAME FRAMEs sent by the first optical bus connector, processing the T _ SYNC _ FRAME FRAMEs of the two links respectively, and sending a response message N _ RESP _ FRAME through any link immediately after receiving the T _ SYNC _ FRAME FRAMEs;

step 130: the optical bus terminal controller which completes the response monitors the configuration information of the optical bus terminal controller on the link, and after the configuration information of the optical bus terminal controller is verified, if the verification passes the recovery CON _ ACK, the recovery CON _ FAIL is carried out;

step 140: after monitoring an all _ COLDSTART _ FRAME FRAME, all optical bus terminal controllers receive a member vector containing a current network GLOBAL view, so far, the cold start process is completed, all the optical bus terminal controllers receiving the all _ COLDSTART _ FRAME FRAME set a local clock to be a link delay relative to an optical bus connector, simultaneously set the current integration period to be 0, reset the local clock to be 0 after reaching a GLOBAL TIME GLOBAL _ RESTART _ POINT _ TIME, and then realize normal communication according to configuration information;

step 150: and each optical bus terminal controller forming the group sends TIME _ TRIGGER _ FRAME TIME TRIGGER flow according to a local planned TIME scale, and the maintenance of the topology is completed by utilizing a GMP algorithm and a distributed clock algorithm.

2. The method of claim 1, wherein the step 010 comprises the following steps:

step 011: initializing a local CLOCK, synchronizing a local GPS _ CLOCK counter to the GPS equipment if the system contains the GPS equipment, and clearing 0 of the local counter; if the system does not contain an external clock source, only clearing 0 from the local clock counter;

step 012: setting the sending member vector to be 64 'h 0000_0001, namely the target device at this time is the device of which the member vector is 64' h0000_ 0001; the local member vector is set to 64' h0000 — 0000.

3. The method as claimed in claim 2, wherein the step 020 comprises the following steps:

step 021: the first optical bus connector sends T _ SYNC _ FRAME FRAMEs containing the sending member vectors to the first optical splitter and the second optical bus connector respectively, records the sending time T1 and starts a Link _ latency _ measure _ count counter;

step 022: shifting 1 in the sending member vector to the left by one bit, and waiting for the next sending;

step 023: waiting for an N _ RESP _ FRAME message corresponding to the equipment response, and setting the corresponding position of the local member vector if the first optical bus connector receives the correct N _ RESP _ FRAME message;

and 024: according to a time point T2 of receiving the N _ RESP _ FRAME message and a known time T _ cost of processing and calculating a T _ SYNC _ FRAME by the optical bus terminal controller, calculating a link delay parameter T _ wireless delay (T2-T1-T _ cost)/2;

step 025: if all the devices in the system have been detected through traversal, go to the step 030, otherwise go back to the step 021.

4. A method for implementing a time triggered passive optical bus as recited in claim 2, wherein said step 030 includes the steps of:

step 031: checking the equipment with the member variable of 1 in the local member vector, and sending respective Configuration Data information and link time parameters to the optical bus terminal controllers, wherein the link time parameters comprise two parts of contents, one part is link time delay between each optical bus terminal controller and an optical bus connector, and the other part is internal processing time delay of the optical bus connector;

step 032: and after the optical bus terminal controller replies CON _ ACK information or exceeds the maximum reconfiguration times, configuring the next optical bus terminal controller.

5. A method as claimed in claim 2, wherein said step 040 includes the following steps:

step 041: using a local member vector as a member vector field in an ALLOW _ COLDSTART _ FRAME FRAME, using a GPS _ CLOCK variable as a GPS information field in the ALLOW _ COLDSTART _ FRAME FRAME, and sending the ALLOW _ COLDSTART _ FRAME FRAME;

step 042: and clearing the local clock after sending an ALLOW _ COLDSTART _ FRAME FRAME, resetting the local clock to be 0 after the local clock normally TIMEs to GLOBAL _ RESTART _ POINT _ TIME, and then realizing normal communication according to the configuration information.

6. A method for implementing a time triggered passive optical bus as claimed in claim 2, wherein said step 050 comprises the steps of:

step 051: for a plurality of optical bus terminal controllers which do not exist in an original group, completing measurement of link time parameters and configuration of configuration data information in respective first Node slots after the plurality of optical bus terminal controllers are powered on, and broadcasting the link time parameters to all other equipment in the respective Node slots;

step 052: the optical bus connector is not forwarded and a WARNING primitive is issued by the optical bus termination controller sending an out-of-spec OTTB _ FRAME.

7. A method for implementing a time triggered passive optical bus as claimed in claim 1, wherein said step 150 comprises the steps of:

step 151: if an ALLOW _ COLDSTART _ FRAME FRAME is received, adding the member vector in the ALLOW _ COLDSTART _ FRAME FRAME into a local member vector of the user, and if a non-ALLOW _ COLDSTART _ FRAME FRAME is received, completing the integration operation of the user;

step 152: each optical bus terminal controller sends data frames in its Node Slot and updates the local member vector according to the GMP algorithm.

Images