CN113037215B - Crystal oscillator control circuit and electronic equipment - Google Patents
Crystal oscillator control circuit and electronic equipment Download PDFInfo
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- CN113037215B CN113037215B CN201911350992.XA CN201911350992A CN113037215B CN 113037215 B CN113037215 B CN 113037215B CN 201911350992 A CN201911350992 A CN 201911350992A CN 113037215 B CN113037215 B CN 113037215B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
本发明实施例提供一种晶振控制电路及电子设备，用以在无线通讯中同时满足RF时钟高精度和RTC时钟低功耗的要求。所述电路包括依次连接的晶振驱动模块、晶振、电容阵列模块、电容阵列控制模块和频率输出模块，晶振驱动模块还分别连接电容阵列控制模块和频率输出模块，其中，晶振驱动模块用于为晶振提供驱动能量，并将晶振产生的第一时钟信号输出至频率输出模块和电容阵列控制模块；电容阵列模块用于改变晶振的负载电容，调节晶振的输出频率和功耗；电容阵列控制模块用于在第一时钟信号的控制下生成控制信号；频率输出模块用于对第一时钟信号进行频率补偿和/或分频处理，输出满足预设频率精度要求的第二时钟信号。
The embodiment of the present invention provides a crystal oscillator control circuit and electronic device, which are used to simultaneously meet the requirements of high precision of RF clock and low power consumption of RTC clock in wireless communication. The circuit includes a crystal oscillator drive module, a crystal oscillator, a capacitor array module, a capacitor array control module and a frequency output module connected in sequence, and the crystal oscillator drive module is also connected to the capacitor array control module and the frequency output module respectively, wherein the crystal oscillator drive module is used to provide driving energy for the crystal oscillator and output the first clock signal generated by the crystal oscillator to the frequency output module and the capacitor array control module; the capacitor array module is used to change the load capacitance of the crystal oscillator and adjust the output frequency and power consumption of the crystal oscillator; the capacitor array control module is used to generate a control signal under the control of the first clock signal; the frequency output module is used to perform frequency compensation and/or frequency division processing on the first clock signal, and output a second clock signal that meets the preset frequency accuracy requirements.
Description
Technical Field
The present disclosure relates to integrated circuit design, and more particularly, to a crystal oscillator control circuit and an electronic device.
Background
Wireless communication nodes are basic building blocks of everything interconnection, and these nodes can be implemented by adopting different technologies, wherein, the radio frequency communication technology is used as the main technology, and has strict control protocol, and the unified time slot specified by the protocol is especially critical for the always-on real-time system.
As shown in fig. 1, taking bluetooth low energy (Bluetooth Low Energy, BLE) transmission as an example, most of the time, the nodes in the BLE network are in a dormant state, but they wake up themselves at accurate time to perform precisely synchronized radio frequency communication strictly according to the protocol after networking. The connection events of BLE in fig. 1 are separated by a plurality of connection intervals, and the device is in a sleep state most of the time after the connection is established, in which case the power consumption can be as low as 1 microampere (μa), whereas in the connection event, the power consumption can be as high as tens of milliamperes. In a connection event, radio Frequency (RF) communication requires that the Frequency offset between nodes is very small, and in order to ensure signal quality, a communication chip usually calibrates the Frequency offset to ±10ppm (PARTS PER MI L L ion, million concentration). In a sleep state, the sleep Clock accuracy requirement of a Clock chip (RTC) is relatively low, but because the RTC Clock accuracy can affect the window widening time, too poor Clock accuracy can lead to early wake-up, which is unfavorable for low-power consumption application, so in low-power consumption application, the RTC also needs higher Clock accuracy, and generally only a quartz crystal oscillator can meet the requirement.
In the prior art, there are two schemes for wireless communication, one scheme is to apply a high-frequency crystal oscillator during RF communication, and a low-frequency crystal oscillator is needed to meet the low power consumption requirement of the RTC in the dormant state. But for some wearable wireless nodes, the scheme cannot meet the requirements of low power consumption, low cost and small size at the same time. Another approach is to keep the external high frequency crystal oscillator, providing a high quality reference source for the rf system, while the low frequency crystal oscillator is replaced by an internal RC oscillator or ring oscillator. The scheme has the advantages that the cost and the power consumption are combined, but the internal oscillator is easily influenced by power supply voltage, temperature and the like, so that the frequency is unstable, the frequency precision can only reach the level of 500ppm normally even under the condition of calibration, and the requirement of a high-precision RTC clock cannot be met.
In summary, the prior art cannot meet the requirements of high precision of the RF clock and low power consumption of the RTC clock.
Disclosure of Invention
The embodiment of the invention provides a crystal oscillator control circuit and electronic equipment, which are used for simultaneously meeting the requirements of high precision of an RF clock and low power consumption of an RTC clock in wireless communication.
In a first aspect, an embodiment of the present invention provides a crystal oscillator control circuit, including a crystal oscillator driving module, a crystal oscillator, a capacitor array module, a capacitor array control module and a frequency output module, which are sequentially connected, where the crystal oscillator driving module is further connected to the capacitor array control module and the frequency output module respectively,
The crystal oscillator driving module is used for providing driving energy for the crystal oscillator and outputting a first clock signal generated by the crystal oscillator to the frequency output module and the capacitor array control module;
The capacitor array module is used for changing the load capacitance of the crystal oscillator and adjusting the output frequency and the power consumption of the crystal oscillator under the control of the control signal sent by the capacitor array control module;
The capacitor array control module is used for generating a control signal under the control of the first clock signal, and the control signal is used for adjusting the capacitance value of the capacitor array module;
The frequency output module is used for carrying out frequency compensation and/or frequency division processing on the first clock signal based on the frequency control signal output by the capacitor array control module and outputting a second clock signal meeting the preset frequency precision requirement.
The crystal oscillator control circuit provided by the embodiment of the invention consists of five parts, namely a crystal oscillator driving module, a crystal oscillator, a capacitor array module, a capacitor array control module and a frequency output module. The device comprises a crystal oscillator driving module, a capacitance array module and a first clock signal, wherein the crystal oscillator driving module is connected with the crystal oscillator and used for providing driving energy for the crystal oscillator to enable the crystal oscillator to maintain reliable piezoelectric oscillation characteristics and output corresponding oscillation waveforms, the capacitance array module is connected with the crystal oscillator and used for changing load capacitance of the crystal oscillator and adjusting output frequency and power consumption of the crystal oscillator under the control of a control signal sent by the capacitance array control module, the capacitance array control module is connected with the capacitance array module and used for generating the control signal under the control of a first clock signal and adjusting capacitance value of the capacitance array module so as to smoothly control the output frequency and power consumption of the crystal oscillator, and the frequency output module is connected with the crystal oscillator driving module and used for carrying out frequency compensation and/or frequency division processing on the first clock signal and outputting a second clock signal meeting the requirement of preset frequency precision. Compared with the prior art, the cost and the stability of the crystal oscillator control circuit are considered in the wireless communication process, and the requirements of high precision of the RF clock and low power consumption of the RTC clock can be simultaneously met.
In one possible implementation, the crystal oscillator is a single external high-frequency crystal oscillator, and the crystal oscillator driving module, the capacitor array control module and the frequency output module are all arranged inside the chip.
In one possible implementation, the capacitor array module comprises a plurality of capacitor assemblies and a switch assembly connected between each capacitor assembly and a ground wire, wherein each switch assembly performs a switching action according to a control signal sent by the capacitor array control module so as to control whether the capacitor assembly connected with each switch assembly is connected with the capacitor array module or not.
In one possible implementation, the capacitance components in the capacitance array module, whose capacitance values are adjusted by an amount greater than a preset threshold, are coded by a capacitance thermometer.
In one possible implementation, the capacitance components in the capacitance array module, whose capacitance values are adjusted to be less than or equal to a preset threshold, are binary coded.
In one possible implementation, the capacitive array control module includes a two-way selector, a digital comparator, and a up-down counter connected in sequence, wherein,
The double-path selector is used for selecting one path of signal from the received radio frequency coding signal or clock coding signal to output to the digital comparator according to the control of the preset dormancy timing signal;
the digital comparator is used for comparing the output signal of the two-way selector with the control signal output by the capacitor array control module and outputting an adjusting signal for adjusting the control signal;
And the bidirectional counter is used for counting the regulating signal output by the digital comparator under the control of the first clock signal subjected to the preset processing and regulating the control signal according to the counting result.
In one possible implementation, the preset processing of the up-down counter includes one or more of frequency division processing and delay processing.
In one possible implementation, the frequency output module comprises a high-frequency pulse phagocytosis module, a first frequency divider and a second frequency divider, wherein the output of the high-frequency pulse phagocytosis module generates a feedback clock signal through the first frequency divider, the feedback clock signal is fed back to the high-frequency pulse phagocytosis module through the second frequency divider and is output as a second clock signal when the feedback clock signal meets the preset frequency precision requirement,
The high-frequency pulse phagocytizing module is used for phagocytizing a preset number of high-frequency clock cycles in the received first clock signal every other target cycle based on the frequency control signal output by the capacitor array control module, wherein the target cycle is the product of frequency dividing parameters of the first frequency divider and the second frequency divider, and the preset number is determined according to the frequency control signal.
In one possible implementation, the first frequency divider is an integer frequency divider and the second frequency divider is a fractional frequency divider.
In one possible implementation, the crystal oscillator adopts any one of an inverter structure and a single-ended structure.
In one possible implementation, the single-ended structure is a single-ended structure with an oscillation amplitude control module.
In a second aspect, an embodiment of the present invention provides an electronic device, including a crystal oscillator control circuit according to any one of the first aspect of the embodiment of the present invention.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
Fig. 1 is a schematic diagram of a wireless communication transmission process according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a crystal oscillator control circuit according to an embodiment of the present invention;
Fig. 3 is a schematic structural diagram of a crystal oscillating circuit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a crystal oscillator equivalent model according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing a relationship between an oscillation frequency and a load capacitance of a crystal oscillator according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a capacitor array module according to an embodiment of the present invention;
Fig. 7 is a schematic structural diagram of another capacitor array module according to an embodiment of the present invention;
Fig. 8 is a schematic structural diagram of a capacitive array control module according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram of a delay element according to an embodiment of the present invention;
fig. 10 is a schematic diagram of signal conditioning of a capacitor array module according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a frequency output module according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention will be described below with reference to the accompanying drawings, and it should be understood that the embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
In view of the fact that the requirements of high precision of an RF clock and low power consumption of an RTC clock cannot be met in the wireless communication process in the prior art, the embodiment of the invention provides a crystal oscillator control circuit, which is used for considering the cost and stability of the crystal oscillator control circuit in the wireless communication process and meeting the requirements of high precision of the RF clock and low power consumption of the RTC clock.
The following describes the scheme provided by the embodiment of the invention in detail with reference to the accompanying drawings.
As shown in fig. 2, the embodiment of the invention provides a crystal oscillator control circuit, which comprises a crystal oscillator driving module 21, a crystal oscillator 22, a capacitor array module 23, a capacitor array control module 24 and a frequency output module 25 which are sequentially connected, wherein the crystal oscillator driving module 21 is also respectively connected with the capacitor array control module 24 and the frequency output module 25,
The crystal oscillator driving module 21 is configured to provide driving energy for the crystal oscillator 22, and output a first clock signal (clk_rf) generated by the crystal oscillator 22 to the frequency output module 25 and the capacitor array control module 24;
The capacitor array module 23 is configured to change a load capacitance of the crystal oscillator 22 under control of a control signal (cap_ctl) sent by the capacitor array control module 24, and adjust an output frequency and power consumption of the crystal oscillator 22;
a capacitor array control module 24, configured to generate a control signal (cap_ctl) under the control of the first clock signal (clk_rf) output by the crystal oscillator 22, for adjusting the capacitance value of the capacitor array module 23;
The frequency output module 25 is configured to perform frequency compensation and/or frequency division processing on the first clock signal (clk_rf) output by the crystal oscillator 22 based on the frequency control signal (freq_ctl) output by the capacitor array control module 24, and output a second clock signal (clk_rtc) that meets a preset frequency accuracy requirement.
Through the scheme, the crystal oscillator control circuit is composed of the crystal oscillator driving module, the crystal oscillator, the capacitor array module, the capacitor array control module and the frequency output module. The crystal oscillator comprises a crystal oscillator driving module, a capacitor array module and a frequency output module, wherein the crystal oscillator driving module is connected with the crystal oscillator and is used for providing driving energy for the crystal oscillator to enable the crystal oscillator to maintain reliable piezoelectric oscillation characteristics and output corresponding oscillation waveforms, the capacitor array module is connected with the crystal oscillator and is used for changing the load capacitance of the crystal oscillator and adjusting the output frequency and power consumption of the crystal oscillator under the control of a control signal sent by the capacitor array control module, the capacitor array control module is connected with the capacitor array module and is used for generating the control signal under the control of a first clock signal output by the crystal oscillator and adjusting the capacitance value of the capacitor array module so as to smoothly control the output frequency and the power consumption of the crystal oscillator, and the frequency output module is connected with the crystal oscillator driving module and is used for carrying out frequency compensation and/or frequency division processing on the first clock signal output by the capacitor array control module and outputting a second clock signal meeting the preset frequency precision requirement. Compared with the prior art, in the wireless communication process, the quality of signals can be guaranteed through the high-precision RF clock, and the low-power consumption requirement of the RTC clock can be met by avoiding the sleep state from being awakened in advance.
Further, in one possible implementation, the crystal oscillator is a single external high-frequency crystal oscillator, and the crystal oscillator driving module, the capacitor array control module and the frequency output module are all disposed inside the chip.
Only one external high-frequency crystal oscillator is used, and the device works in a performance mode when the device is connected, works in a low-power consumption mode when the device is dormant, and meets the requirement of a system on the clock accuracy through preset processing such as frequency compensation. Besides the crystal oscillator is an off-chip device, other modules can be arranged inside the chip and used for controlling the frequency and the power consumption of the crystal oscillator so as to meet the high precision of the crystal oscillator in a low power consumption state.
The following describes each module in the crystal oscillator control circuit in detail with reference to the accompanying drawings.
As shown in fig. 3, a is a common implementation structure of a crystal oscillating circuit, where a is an inverter structure, and power consumption of a crystal oscillator has a positive correlation with a supply voltage and a positive correlation with a load capacitance. b and c are single ended structures, and since they take the form of a constant tail current, the power consumption is independent of the supply voltage, and is related to the oscillation amplitude and the load capacitance. d is a single-ended structure with an amplitude control module, and the amplitude control module can detect the amplitude of oscillation voltage of the crystal oscillator and give real-time control, so that the power consumption of the circuit is controlled. The power consumption of the circuit is independent of the supply voltage, but dependent on the oscillation amplitude and the load capacitance.
As shown in fig. 4, an equivalent model of the crystal oscillator is shown, where Co, rm, cm, and Lm are intrinsic parameters. C1 and C2 are external load capacitors of the crystal oscillator, can be made on a PCB or in a chip, and can adjust the oscillation frequency of the crystal oscillator by changing the size of the load capacitors. The oscillation frequency of the crystal can be represented by formula 1, where Cs can be represented by formula 2:
the relationship between the oscillation frequency and the load capacitance for a 24MHz crystal oscillator is shown in fig. 5. The power consumption of the quartz crystal itself can be represented by formula 3:
Where V is the voltage amplitude across the crystal, C3 is the sum of Cs and Co, and C is C1 or C2. It follows that the power consumption of the crystal itself is square with the load capacitance C, and if the capacitance is reduced to one fourth, the power consumption itself becomes one sixteen.
In one possible implementation, the capacitor array module comprises a plurality of capacitor assemblies and a switch assembly connected between each capacitor assembly and a ground wire, wherein each switch assembly performs a switching action according to a control signal (CAP_CTL) sent by the capacitor array control module so as to control whether the capacitor assembly connected with each switch assembly is connected with the capacitor array module or not.
In one possible implementation, the capacitance components in the capacitance array module, whose capacitance values are adjusted by an amount greater than a preset threshold, are coded by a capacitance thermometer. And a binary coding mode is adopted for the capacitor assembly of which the capacitance value of the capacitor array module is smaller than or equal to a preset threshold value in the capacitor array module.
As shown in FIG. 6, the thermometer coded capacitor array has the advantages of small influence on the oscillation waveform and good performance because only one unit capacitor is turned on or off during each adjustment, and the disadvantage of more switches needed and the need of decoding by the controller. As shown in FIG. 7, the binary coded capacitor array has the advantages of small number of required switches, only N switches for the N Bi t array, large disturbance to waveforms during capacitor adjustment and poor performance.
In one possible implementation, for a 10 bit (Bi t) capacitor array, 2 10 or 1024 switches are required if a thermometer coded capacitor array is used, but only 10 switches are required if a binary coded capacitor array is used.
In order to achieve both performance and area, the thermometer coded capacitor array and the binary coded capacitor array can be used in a fused mode, wherein the thermometer coded array is used for high-order bits, and the binary coded array is used for low-order bits. This reduces the number of switches and reduces the disturbance to the waveform during capacitance adjustment.
As shown in fig. 8, the capacitive array control module includes a two-way selector 81, a digital comparator 82 and a DOWN counter 83 connected in sequence, wherein the two-way selector 81 is used for selecting one signal from a received radio frequency CODE signal (rf_code) or a clock CODE signal (rtc_code) to output to the digital comparator 82 according to control of a preset SLEEP timing signal (sleep_state), the digital comparator 82 is used for comparing an output signal ((rf_code/rtc_code)) of the two-way selector with a control signal (cap_ctl) output by the capacitive array control module, and outputting an adjustment signal (UP/DOWN) for adjusting the control signal (cap_ctl), and the DOWN counter 83 is used for counting the adjustment signal (UP/DOWN) output by the digital comparator 82 under control of a preset first clock signal (clk_rf) and adjusting the control signal (cap_ctl) according to a counting result. In particular, the predetermined processing of the first clock signal (CLK_RF) may include one or more of delay processing by 84 delay elements and divide processing by a frequency divider 85.
The capacitive array control module operates on the principle that when the SLEEP timing signal (sleep_state) is 0, the digital comparator compares the radio frequency CODE signal (rf_code) with the control signal (cap_ctl), if the radio frequency CODE signal (rf_code) is smaller than the control signal (cap_ctl), up=0, down=1, when the clock edge arrives, the Up-down counter performs a down-1 operation, i.e. the control signal (cap_ctl) is decremented by 1 and then the next comparison is performed, if the radio frequency CODE signal (rf_code) is larger than the control signal (cap_ctl), up=1, down=0, when the clock edge arrives, the Up-down counter performs a Up-1 operation, i.e. the control signal (cap_ctl) is incremented by 1 and then the next comparison is performed, if the radio frequency CODE signal (rf_code) is equal to the control signal (cap_ctl), when the clock edge arrives, the up=0, the Up-down counter maintains the original value, and finally makes the radio frequency CODE signal (rf_code) equal to the control signal (cap_ctl) through a plurality of comparison/counting cycles. Similarly, when the SLEEP timing signal (sleep_state) is 1, the digital comparator compares the clock CODE signal (rtc_code) with the control signal (cap_ctl), and after a number of cycles of comparison/counting, the clock CODE signal (rtc_code) is finally made equal to the control signal (cap_ctl).
The clock of the bidirectional counter is derived from the crystal oscillator, so that the load capacitance is smoothly switched, the continuous and excessively fast change of the load is avoided, a frequency dividing circuit can be connected in series before the clock of the counter, and the frequency dividing ratio can be determined according to the switching time. In addition, according to the principle of phase noise injection, the signal amplitude is adjusted at the highest point or the lowest point, and the interference to the signal is minimum, so that the control clock of the counter can be delayed by the delay unit, and the phase of the control clock is shifted (for example, 90 degrees) to achieve the best effect.
The delay unit has various structures, as shown IN fig. 9, a adopts an RC low-pass filter to delay the clock input signal (clk_in), and IN fig. 9, b adopts a plurality of delay units connected IN series to achieve the purpose of delay. After delay, each time the oscillating signal reaches the peak, the capacitor array is adjusted, so that interference to the signal is reduced, and the specific adjustment process is shown in fig. 10.
In one possible implementation, the frequency output module comprises a high-frequency pulse phagocytosis module, a first frequency divider and a second frequency divider, wherein the output of the high-frequency pulse phagocytosis module generates a feedback clock signal through the first frequency divider, the feedback clock signal is fed back to the high-frequency pulse phagocytosis module through the second frequency divider and is output as a second clock signal when the feedback clock signal meets the preset frequency precision requirement,
The high-frequency pulse phagocytosis module is used for phagocytizing a preset number of high-frequency clock cycles in the received first clock signal (CLK_RF) every target period based on the frequency control signal output by the capacitor array control module, wherein the target period is the product of frequency dividing parameters of the first frequency divider and the second frequency divider, and the preset number is determined according to the frequency control signal (FREQ_CTL).
In one possible implementation, the first frequency divider is an integer frequency divider and the second frequency divider is a fractional frequency divider.
In practice, when the crystal oscillator is operated in the radio frequency mode, the frequency is precisely 24 megahertz (MHz), and precise 32.768 kilohertz (KHz) is required to be obtained, and fine fractional frequency division is required. When the crystal is operating in RTC mode, the load capacitance is reduced in order to reduce power consumption, and therefore the crystal frequency increases. The frequency output compensation module is required to compensate the output frequency, so that the RTC clock meeting the requirement is obtained.
As shown in fig. 11, the frequency output module is composed of a high-frequency pulse phagocytosis module 111, a fractional divider 112, and an integer divider 113. The working principle is that the pulse phagocytosis module 111 phagocytoses K high-frequency clock cycles every m×n radio-frequency clock cycles according to the set value of the frequency control signal (freq_ctl), the parameter of the fractional divider is M, the parameter of the integer divider is N, and the frequency division ratio can be represented by equation 4:
div_ratio=m +K/N type 4
Wherein m=732.4, n=137, 0< k < n, the adjustment accuracy is about 10ppm.
In the RF mode, the crystal oscillator frequency is precisely 24MHz, and then only k=3 needs to be set, and the second clock signal (clk_rtc) has a frequency offset of less than 0.1ppm with respect to 32.768 KHz.
In the RTC mode, assuming that the frequency is 500ppm higher due to reduced power consumption (by reducing the load capacitance), only k=53 is required to be set, the second clock signal (clk_rtc) is equal to 32768.05Hz, and the frequency offset is 1.7ppm, so as to meet the requirement of the high-precision RTC clock.
Since the pulse phagocytizing module 111 continuously phagocytises a single period of K24 MHz clocks every m×n 24MHz clock periods, that is, only one period of the second clock signal (clk_rtc) is longer in the interval of 4.18mS, and the other periods are shorter, and the average period is 1/32.768KHz. Since the sleep time of BLE is 7.5mS-4S, sleep and wake-up of BLE are not affected.
Based on the same inventive thought, the embodiment of the invention also provides electronic equipment, which comprises the crystal oscillator control circuit provided by the embodiment of the invention.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (12)
1. A crystal oscillator control circuit is characterized by comprising a crystal oscillator driving module, a crystal oscillator, a capacitor array module, a capacitor array control module and a frequency output module which are connected in sequence, wherein the crystal oscillator driving module is also connected with the capacitor array control module and the frequency output module respectively,
The crystal oscillator driving module is used for providing driving energy for the crystal oscillator and outputting a first clock signal generated by the crystal oscillator to the frequency output module and the capacitor array control module;
The capacitor array module is used for changing the load capacitance of the crystal oscillator under the control of the control signal sent by the capacitor array control module and adjusting the output frequency and the power consumption of the crystal oscillator;
The capacitive array control module is used for outputting a frequency control signal under the control of a sleep time sequence signal, wherein the frequency control signal comprises a radio frequency coding signal or a clock coding signal, and is used for generating a control signal based on the frequency control signal under the control of the first clock signal, and the control signal is used for adjusting the capacitance value of the capacitive array module;
the frequency output module is used for carrying out frequency compensation and/or frequency division processing on the first clock signal based on the frequency control signal output by the capacitor array control module and outputting a second clock signal meeting the preset frequency precision requirement.
2. The circuit of claim 1, wherein the crystal oscillator is a single external high frequency crystal oscillator, and the crystal oscillator drive module, the capacitor array control module, and the frequency output module are all disposed inside a chip.
3. The circuit of claim 1, wherein the capacitor array module comprises a plurality of capacitor assemblies and a switch assembly connected between each capacitor assembly and a ground line, wherein each switch assembly performs a switching action according to a control signal sent by the capacitor array control module to control whether the capacitor assembly connected with each switch assembly is connected to the capacitor array module.
4. The circuit of claim 1, wherein in the capacitor array module, a capacitor assembly having a capacitance value of the capacitor array module adjusted by an amount greater than a predetermined threshold value is encoded by a capacitor thermometer.
5. The circuit of claim 4, wherein the capacitor array module has binary coding for capacitor components whose capacitance is less than or equal to the predetermined threshold.
6. The circuit of claim 1, wherein the capacitive array control module comprises a two-way selector, a digital comparator, and a up-down counter connected in sequence, wherein,
The double-path selector is used for selecting one path of signal from the received radio frequency coding signal or clock coding signal to output to the digital comparator according to the control of a preset dormancy time sequence signal;
The digital comparator is used for comparing the output signal of the two-way selector with the control signal output by the capacitor array control module and outputting an adjusting signal for adjusting the control signal;
The bidirectional counter is used for counting the adjusting signal output by the digital comparator under the control of the first clock signal subjected to the preset processing and adjusting the control signal according to the counting result.
7. The circuit of claim 6, wherein the preset process comprises one or more of a frequency division process and a delay process.
8. The circuit of claim 1, wherein the frequency output module comprises a high frequency pulse phagocytosis module, a first frequency divider and a second frequency divider, wherein the output of the high frequency pulse phagocytosis module generates a feedback clock signal through the first frequency divider, the feedback clock signal is fed back to the high frequency pulse phagocytosis module through the second frequency divider and is output as a second clock signal when the feedback clock signal meets the preset frequency accuracy requirement,
The high-frequency pulse phagocytosis module is used for phagocytizing a preset number of high-frequency clock cycles in the received first clock signal every other target cycle based on the frequency control signal output by the capacitor array control module, wherein the target cycle is the product of frequency dividing parameters of the first frequency divider and the second frequency divider, and the preset number is determined according to the frequency control signal.
9. The circuit of claim 8, wherein the first frequency divider is an integer frequency divider and the second frequency divider is a fractional frequency divider.
10. The circuit of claim 1, wherein the crystal oscillator is in any one of an inverter structure and a single-ended structure.
11. The circuit of claim 10, wherein the single-ended structure is a single-ended structure with an oscillation amplitude control module.
12. An electronic device comprising a crystal oscillator control circuit according to any one of claims 1-11.
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| CN201911350992.XA CN113037215B (en) | 2019-12-24 | 2019-12-24 | Crystal oscillator control circuit and electronic equipment |
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| CN113824322B (en) * | 2021-09-30 | 2024-08-13 | 南方电网数字电网研究院有限公司 | Frequency stabilizing circuit and method for modulation switch converter |
| CN115765724A (en) * | 2022-10-31 | 2023-03-07 | 无锡华润上华科技有限公司 | Crystal oscillator starting control circuit and method, crystal oscillator device and SOC chip |
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| US6917188B2 (en) * | 2002-11-14 | 2005-07-12 | Fyre Storm, Inc. | Power converter circuitry and method |
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| CN109450378A (en) * | 2018-11-01 | 2019-03-08 | 郑州云海信息技术有限公司 | A kind of crystal oscillating circuit and clock signal generation method |
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