CN113035863B - Power integrated chip with longitudinal channel structure - Google Patents

Abstract

The invention relates to a power integrated chip incorporating a vertical channel structure, comprising: a P-type substrate region, a vertical withstand voltage region, an isolation region, a MOSFET and a diode region; the diode region includes a diode, an N-lateral drift region and a vertical region. Channel region; the P-type substrate region is located at the bottom of the chip, a vertical withstand voltage region is arranged above the P-type substrate region, a MOSFET is arranged on one side of the vertical withstand voltage region, and a diode region is arranged on the other side above the vertical withstand voltage region. The beneficial effects of the present invention are: by adding a vertical channel region and properly adjusting its channel length, the limit depth of the vertical depletion layer in the N-type layer is increased; when a high voltage drop is formed between the drain/anode and the source/reference ground , avoiding the vertical punch-through problem due to the extension of the depletion layer boundary to the diode anode. The vertical channel region improves the vertical withstand voltage capability and overall withstand voltage level of the power integrated chip, and broadens the application scope of the chip.

Description

A power integrated chip introducing vertical channel structure

technical field

The invention belongs to the field of power integrated chips, in particular to a power integrated chip introduced with a vertical channel structure.

Background technique

A schematic diagram of the structure of a conventional power integrated chip is shown in Figure 4-1. When the chip is in working mode II, there is a high voltage drop between the diode anode and the reference ground. Due to the limited thickness of the N-type layer (lateral drift layer), the layer is in a depleted state when the high voltage drop to ground occurs, and the anode and the reference ground have a problem of longitudinal punch-through. In Figure 4-2-1 and Figure 4-2-2, when the voltage drop between the drain/anode to source/reference ground does not reach the avalanche breakdown voltage, there is already a voltage drop from the anode to the reference ground The obvious longitudinal leakage current path indicates that the longitudinal direction is in a punch-through state.

Therefore, in order to improve the overall vertical withstand voltage capability of the device, it is particularly important to propose a power integrated chip incorporating a vertical channel structure.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies in the prior art, and to provide a power integrated chip incorporating a vertical channel structure.

A power integrated chip incorporating a vertical channel structure, as shown in Figure 1, includes: a P-type substrate region, a vertical withstand voltage region, an isolation region, a MOSFET and a diode region; the diode region includes a diode, an N-lateral drift region and Vertical channel region; the P-type substrate region is located at the bottom of the chip, a vertical withstand voltage region is set above the P-type substrate region, a MOSFET is set on one side of the vertical withstand voltage region, and a diode region is set on the other side above the vertical withstand voltage region, MOSFET and diode There is an isolation area between the areas; the left and right sides of the isolation area are N-lateral drift areas. The withstand voltage region is the main vertical withstand voltage region; the channel in the MOSFET is a lateral channel (planar gate); the isolation region is partially embedded in the vertical withstand voltage region, and the vertical channel region of the diode region is located on the side of the diode close to the isolation region, The vertical channel region is arranged close to the isolation region, and the vertical channel region is partially embedded in the N-lateral drift region located on the right side of the isolation region; the channel length of the vertical channel region is adjustable.

A power integrated chip incorporating a vertical channel structure, as shown in Figure 3(a), includes: a P-type substrate region, a vertical withstand voltage region, an isolation region, a MOSFET and a diode region; the diode region includes a diode, an N-transverse Drift region and vertical channel region; the P-type substrate region is located at the bottom of the chip, the vertical withstand voltage region is set above the P-type substrate region, the MOSFET is set to the left above the vertical withstand voltage region, and the diode region is set to the right above the vertical withstand voltage region , there is an isolation region between the MOSFET and the diode region; the left and right sides of the isolation region are N-lateral drift regions, and the N-lateral drift region is the main region that bears the lateral withstand voltage, and also bears the longitudinal voltage together with the vertical withstand voltage region. The vertical withstand voltage region is the main vertical withstand voltage region; the channel in the MOSFET is a lateral channel (planar gate); the isolation region is partially embedded in the vertical withstand voltage region, and the vertical channel region of the diode region is located near the isolation region of the diode On one side of the isolation region, the vertical channel region is placed close to the isolation region, and the vertical channel region is partially embedded in the N-lateral drift region located on the right side of the isolation region; the channel length of the vertical channel region is adjustable; it is also increased below the cathode of the diode The vertical extension area of the cathode is formed, so that the cathode N+ is located above the bottom of the diode groove; without increasing the width of the cell, it can not only prolong the distance between the diode cathode and the anode, but also improve the electric field distribution (the high electric field near the cathode N+ gets mitigation), thereby increasing the voltage withstand capability of the diode.

A power integrated chip incorporating a vertical channel structure, as shown in Figure 3(b), includes: a P-type substrate region, a vertical withstand voltage region, an isolation region, a MOSFET and a diode region; the diode region includes a diode, an N-transverse Drift region and vertical channel region; the P-type substrate region is located at the bottom of the chip, the vertical withstand voltage region is set above the P-type substrate region, the MOSFET is set to the left above the vertical withstand voltage region, and the diode region is set to the right above the vertical withstand voltage region , there is an isolation region between the MOSFET and the diode region; the left and right sides of the isolation region are N-lateral drift regions, and the N-lateral drift region is the main region that bears the lateral withstand voltage, and also bears the longitudinal voltage together with the vertical withstand voltage region. The vertical withstand voltage region is the main vertical withstand voltage region; the channel in the MOSFET is a lateral channel (planar gate); the isolation region is partially embedded in the vertical withstand voltage region, and the vertical channel region of the diode region is located near the isolation region of the diode On one side of the isolation region, the vertical channel region is placed close to the isolation region, and the vertical channel region is partially embedded in the N-lateral drift region located on the right side of the isolation region; the channel length of the vertical channel region is adjustable; the metal field plate of the diode anode It extends down to the vertical channel region to form a vertical field plate; the metal (Mental)-dielectric layer (Oxide)-channel region (Semiconductor) together form a structure similar to TMBS (trenched MOS structure Schottky diode); diode During blocking, the depletion layer in the channel region diffuses, which enhances the electric field shielding at the Schottky contact junction and reduces the leakage current.

A power integrated chip incorporating a vertical channel structure, as shown in Figure 3(c), includes: a P-type substrate region, a vertical withstand voltage region, an isolation region, a MOSFET and a diode region; the diode region includes a diode, an N-transverse Drift region and vertical channel region; the P-type substrate region is located at the bottom of the chip, the vertical withstand voltage region is set above the P-type substrate region, the MOSFET is set to the left above the vertical withstand voltage region, and the diode region is set to the right above the vertical withstand voltage region , there is an isolation region between the MOSFET and the diode region; the left and right sides of the isolation region are N-lateral drift regions, and the N-lateral drift region is the main region that bears the lateral withstand voltage, and also bears the longitudinal voltage together with the vertical withstand voltage region. The vertical withstand voltage region is the main vertical withstand voltage region; the channel in the MOSFET is a lateral channel (planar gate); the isolation region is partially embedded in the vertical withstand voltage region, and the vertical channel region of the diode region is located near the isolation region of the diode On one side of the isolation region, the vertical channel region is placed close to the isolation region, and the vertical channel region is partially embedded in the N-lateral drift region located on the right side of the isolation region; the channel length of the vertical channel region is adjustable; the vertical channel under the diode anode A P+ region is also added in the region close to the anode of the diode, which enhances the shielding effect at the Schottky contact junction when the diode is blocked, and helps to reduce the leakage current of the device.

A power integrated chip incorporating a vertical channel structure, as shown in Figure 3(d), includes: a P-type substrate region, a vertical withstand voltage region, an isolation region, a MOSFET and a diode region; the diode region includes a diode, an N-transverse Drift region and vertical channel region; the P-type substrate region is located at the bottom of the chip, the vertical withstand voltage region is set above the P-type substrate region, the MOSFET is set to the left above the vertical withstand voltage region, and the diode region is set to the right above the vertical withstand voltage region , there is an isolation region between the MOSFET and the diode region; the left and right sides of the isolation region are N-lateral drift regions, and the N-lateral drift region is the main region that bears the lateral withstand voltage, and also bears the longitudinal voltage together with the vertical withstand voltage region. The vertical withstand voltage region is the main vertical withstand voltage region; the isolation region is partially embedded in the vertical withstand voltage region, the vertical channel region of the diode region is located on the side of the diode close to the isolation region, and the vertical channel region is set close to the isolation region. The vertical channel region is partially embedded in the N-lateral drift region on the right side of the isolation region; the channel length of the vertical channel region is adjustable; the channel in the MOSFET is a vertical channel (trench gate), and the trench gate structure can reduce the The width of the small cell is beneficial to increase the power density.

Preferably, the MOSFETs and diodes are fabricated laterally on the same wafer and interconnected at the cell level.

Preferably, the source of the MOSFET is grounded, the drain of the MOSFET is shorted to the anode of the diode to form a shorted portion of the drain of the MOSFET and the anode of the diode, and the shorted portion of the drain of the MOSFET and the anode of the diode is located above the isolation region; the other electrodes of the MOSFET and the diode After being drawn out, it is connected to the external circuit.

Preferably, the MOSFET is a lateral MOSFET (LDMOS), and the diode is a Schottky diode.

The beneficial effects of the present invention are as follows: the present invention increases the limit depth of the vertical depletion layer in the N-type layer by adding a vertical channel region and appropriately adjusting its channel length; when the drain/anode to the source/reference ground forms a high voltage When falling, the vertical punch-through problem due to the extension of the depletion layer boundary to the diode anode is avoided. The vertical channel region improves the vertical withstand voltage capability and overall withstand voltage level of the power integrated chip, and broadens the application scope of the chip.

Description of drawings

Figure 1 is a cell structure diagram of a Boost power integrated chip introducing a vertical channel structure;

Figure 2-1 is a schematic diagram of a Boost circuit that introduces a vertical channel structure;

Figure 2-2 is a schematic diagram of the trench MOS structure Schottky diode (TMBS) structure;

Figure 2-3 shows the potential distribution (left figure) and leakage current distribution (right figure) of the Boost power integrated chip with the vertical channel structure introduced in the working mode II, corresponding to point B in Figure 2-5 (LDMOS breakdown front, not penetrated);

Figure 2-4 shows the potential distribution (left figure) and leakage current distribution (right figure) of the Boost power integrated chip with the vertical channel structure introduced in the working mode II, corresponding to point C in Figure 2-5, (LDMOS breakdown , not penetrated);

Figure 2-5 shows the comparison result of withstand voltage between the Boost power integrated chip with the vertical channel structure and the conventional Boost power integrated chip;

In Fig. 3 (a) is a schematic diagram of a Boost power integrated chip with a vertical channel structure introduced by adding a vertical extension region of the cathode under the cathode; (b) is the introduction of a vertical field plate in the short-circuit part between the drain of the MOSFET and the anode of the diode Schematic diagram of a Boost power integrated chip with a vertical channel structure; (c) is a schematic diagram of a Boost power integrated chip with a vertical channel structure and a P+ region under the anode of the diode; (d) The channel direction of the MOSFET is changed from the horizontal channel. The schematic diagram of the Boost power integrated chip introducing the vertical channel structure into the vertical channel;

Figure 4-1 is the cell structure diagram of the conventional Boost power integrated chip;

Figure 4-2-1 is the potential distribution diagram of the conventional Boost power integrated chip in working mode II;

Figure 4-2-2 is the leakage current distribution diagram of the conventional Boost power integrated chip in working mode II, corresponding to point A in Figure 2-5.

Description of reference numbers:

Source 1, gate 2, MOSFET drain and diode anode short-circuit part 3, diode cathode 4, N-lateral drift region 5, isolation region 6, vertical channel region 7, vertical withstand voltage region 8, P-type Substrate region 9 , MOSFET drain 10 , diode anode 11 , semiconductor 12 , dielectric layer 13 , metal layer 14 , MOSFET 15 , cathode vertical extension region 16 , vertical field plate 17 , trench gate structure 18 .

Detailed ways

The present invention will be further described below in conjunction with the embodiments. The following examples are illustrative only to aid in the understanding of the present invention. It should be pointed out that for those skilled in the art, without departing from the principle of the present invention, the present invention can also be modified several times, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Example 1:

A power integrated chip incorporating a vertical channel structure, as shown in Figure 1, includes: a P-type substrate region 9, a vertical withstand voltage region 8, an isolation region 6, a MOSFET and a diode region; the diode region includes a diode, a N - Lateral drift region 5 and vertical channel region 7; wherein the P-type substrate region 9 is located at the bottom of the chip, a vertical withstand voltage region 8 is arranged above the P-type substrate region 9, and a MOSFET is arranged to the left above the vertical withstand voltage region 8. A diode region is set on the right above the pressure region 8, and an isolation region 6 is provided between the MOSFET and the diode region; the left and right sides of the isolation region 6 are N-lateral drift regions 5, and the N-lateral drift region 5 is used as the main force for lateral withstand voltage. At the same time, it also shares the vertical voltage drop with the vertical withstand voltage region 8, but the vertical withstand voltage region 8 is the main vertical withstand voltage region; the channel in the MOSFET is a lateral channel (planar gate); the isolation region 6 is partially embedded in the vertical direction. Withstand voltage region 8, the vertical channel region 7 of the diode region is located on the side of the diode close to the isolation region 6, the vertical channel region 7 is arranged close to the isolation region 6, and the vertical channel region 7 is partially embedded in the N on the right side of the isolation region 6. - Lateral drift region 5; vertical channel region 7 with adjustable channel length.

As shown in Figure 2-1, the source 1 of the MOSFET is grounded, and the drain 10 of the MOSFET is shorted to the diode anode 11 to form the short-circuit part 3 between the drain and the diode anode of the MOSFET. The short-circuit part 3 between the drain and the diode anode of the MOSFET is located at Above the isolation region 6; the other electrodes of the MOSFET and the diode are drawn out and connected to the external circuit.

For the vertical punch-through problem, in this embodiment, a vertical channel region (Vertical Channel) is added at the position of the diode anode 11 . The vertical channel region increases the limit depth of the depletion layer in the N-type layer to prevent the boundary of the depletion layer from extending to the anode of the diode, thereby improving the overall vertical withstand voltage capability of the device. The vertical channel region can be formed by an etching process, and a structure similar to a TMBS (trench MOS structure Schottky diode) is directly formed with the anode, as shown in Figure 2-2. When the anode of the diode is reverse-biased and blocked, the depletion region in contact with the MOS diffuses and pinches off the Schottky contact junction, which has the effect of shielding the electric field and helps to reduce the leakage current of the Schottky contact junction.

The left picture in Figure 2-3 shows the potential distribution of the device introduced into the vertical channel region in mode II operation, where V _D =V _A ≈ V _K =1200V, the LDMOS is in a state of non-breakdown, and the device is almost There is no vertical leakage current, as shown in the right figure in Figure 2-3; corresponding to point B in Figure 2-5 (before the LDMOS breakdown, it is not broken through);

As shown in the left and right figures in Figure 2-4, when V _D =V _A ≈ V _K =1222V, the LDMOS device will cause carrier avalanche multiplication due to impact ionization, and then breakdown phenomenon will occur. Although the leakage current of the drain to the reference ground/source increases sharply, the anode to the reference ground does not have a punch-through phenomenon; corresponding to point C in Figure 2-5, (when the LDMOS breaks down, there is no punch-through);

Therefore, for the conventional structure device whose epitaxial design is T _P =10um,n _P =1e15cm ^-3 ;T _N =1.0um,n _N =5e16cm ^-3 , the highest longitudinal withstand voltage obtained by simulation is 320V, and the anode pair reference There is a vertical penetration phenomenon. A device using a vertical channel region can ensure that it has a higher vertical withstand voltage level. As shown in Figure 2-5, if the channel length is 2um, even when the LDMOS part of the chip with the new structure has broken down (point C, the voltage drop between the anode and the reference ground is 1222V), the anode can still be guaranteed to the reference ground. The state is not penetrated.

Example 2:

A power integrated chip incorporating a vertical channel structure, as shown in Figure 3(a), includes: a P-type substrate region 9, a vertical withstand voltage region 8, an isolation region 6, a MOSFET and a diode region; the diode region includes Diode, N-lateral drift region 5 and vertical channel region 7; wherein the P-type substrate region 9 is located at the bottom of the chip, the vertical withstand voltage region 8 is set above the P-type substrate region 9, and the MOSFET is set to the left above the vertical withstand voltage region 8 , a diode region is set on the right above the vertical withstand voltage region 8, and an isolation region 6 is provided between the MOSFET and the diode region; the left and right sides of the isolation region 6 are N-lateral drift regions 5, and the N-lateral drift region 5 serves as a lateral withstand region. At the same time, it also shares the vertical voltage drop with the vertical withstand voltage region 8, but the vertical withstand voltage region 8 serves as the main vertical withstand voltage region; the channel in the MOSFET is a lateral channel (planar gate); the isolation region 6 Partially embedded in the vertical withstand voltage region 8, the vertical channel region 7 of the diode region is located on the side of the diode close to the isolation region 6, the vertical channel region 7 is placed close to the isolation region 6, and the vertical channel region 7 is partially embedded on the right side of the isolation region 6 The N- lateral drift region 5 on the side; the channel length of the vertical channel region 7 is adjustable; the cathode longitudinal extension region 16 is also added under the diode cathode 4, so that the cathode N+ is located above the bottom of the diode groove; At the same time, it can not only prolong the distance between the cathode and anode of the diode, but also improve the electric field distribution (the high electric field near the cathode N+ is alleviated), thereby increasing the withstand voltage of the diode.

Example 3:

A power integrated chip incorporating a vertical channel structure, as shown in Figure 3(b), includes: a P-type substrate region 9, a vertical withstand voltage region 8, an isolation region 6, a MOSFET and a diode region; the diode region includes Diode, N-lateral drift region 5 and vertical channel region 7; wherein the P-type substrate region 9 is located at the bottom of the chip, the vertical withstand voltage region 8 is set above the P-type substrate region 9, and the MOSFET is set to the left above the vertical withstand voltage region 8 , a diode region is set on the right above the vertical withstand voltage region 8, and an isolation region 6 is provided between the MOSFET and the diode region; the left and right sides of the isolation region 6 are N-lateral drift regions 5, and the N-lateral drift region 5 serves as a lateral withstand region. At the same time, it also shares the vertical voltage drop with the vertical withstand voltage region 8, but the vertical withstand voltage region 8 serves as the main vertical withstand voltage region; the channel in the MOSFET is a lateral channel (planar gate); the isolation region 6 Partially embedded in the vertical withstand voltage region 8, the vertical channel region 7 of the diode region is located on the side of the diode close to the isolation region 6, the vertical channel region 7 is placed close to the isolation region 6, and the vertical channel region 7 is partially embedded on the right side of the isolation region 6 The N-lateral drift region 5 on the side; the channel length of the vertical channel region 7 is adjustable; the metal field plate of the diode anode 11 extends down to the vertical channel region 7 to form the vertical field plate 17; metal (Mental)-dielectric The layer (Oxide) and the channel region (Semiconductor) together form a structure similar to TMBS (trench MOS structure Schottky diode); when the diode is blocked, the depletion layer in the channel region diffuses, which will enhance the Schottky contact Electric field shielding at the junction location reduces leakage current.

Example 4:

A power integrated chip incorporating a vertical channel structure, as shown in Figure 3(c), includes: a P-type substrate region 9, a vertical withstand voltage region 8, an isolation region 6, a MOSFET and a diode region; the diode region includes Diode, N-lateral drift region 5 and vertical channel region 7; wherein the P-type substrate region 9 is located at the bottom of the chip, the vertical withstand voltage region 8 is set above the P-type substrate region 9, and the MOSFET is set to the left above the vertical withstand voltage region 8 , a diode region is set on the right above the vertical withstand voltage region 8, and an isolation region 6 is provided between the MOSFET and the diode region; the left and right sides of the isolation region 6 are N-lateral drift regions 5, and the N-lateral drift region 5 serves as a lateral withstand region. At the same time, it also shares the vertical voltage drop with the vertical withstand voltage region 8, but the vertical withstand voltage region 8 serves as the main vertical withstand voltage region; the channel in the MOSFET is a lateral channel (planar gate); the isolation region 6 Partially embedded in the vertical withstand voltage region 8, the vertical channel region 7 of the diode region is located on the side of the diode close to the isolation region 6, the vertical channel region 7 is placed close to the isolation region 6, and the vertical channel region 7 is partially embedded on the right side of the isolation region 6 The N- lateral drift region 5 on the side; the channel length of the vertical channel region 7 is adjustable; the P+ region is also added in the vertical channel region 7 under the diode anode 11 close to the diode anode 11, when the diode is blocked, Enhanced shielding at the Schottky contact junction helps reduce device leakage current.

Example 5:

A power integrated chip incorporating a vertical channel structure, as shown in Figure 3(d), includes: a P-type substrate region 9, a vertical withstand voltage region 8, an isolation region 6, a MOSFET and a diode region; the diode region includes Diode, N-lateral drift region 5 and vertical channel region 7; wherein the P-type substrate region 9 is located at the bottom of the chip, the vertical withstand voltage region 8 is set above the P-type substrate region 9, and the MOSFET is set to the left above the vertical withstand voltage region 8 , a diode region is set on the right above the vertical withstand voltage region 8, and an isolation region 6 is provided between the MOSFET and the diode region; the left and right sides of the isolation region 6 are N-lateral drift regions 5, and the N-lateral drift region 5 serves as a lateral withstand region. At the same time, it also shares the vertical pressure drop with the vertical withstand voltage region 8, but the vertical withstand voltage region 8 serves as the main vertical withstand voltage region; the isolation region 6 is partially embedded in the vertical withstand voltage region 8, and the longitudinal channel of the diode region is The region 7 is located on the side of the diode close to the isolation region 6, the vertical channel region 7 is arranged close to the isolation region 6, and the vertical channel region 7 is partially embedded in the N-lateral drift region 5 on the right side of the isolation region 6; the vertical channel region 7 The channel length of the MOSFET is adjustable; the channel in the MOSFET is a vertical channel (trench gate), and the trench gate structure can reduce the width of the cell, which is beneficial to increase the power density.

Claims (4)

1. a power integrated chip introducing a vertical channel structure is characterized in that, comprising: a P-type substrate region (9), a vertical withstand voltage region (8), an isolation region (6), a MOSFET and a diode region; the The diode region includes a diode, an N-lateral drift region (5) and a vertical channel region (7); wherein the P-type substrate region (9) is located at the bottom of the chip, and a vertical withstand voltage region ( 8), a MOSFET is set on one side of the vertical withstand voltage region (8), a diode region is set on the other side above the vertical withstand voltage region (8), and an isolation region (6) is provided between the MOSFET and the diode region; Both sides are N-lateral drift regions (5); the channel in the MOSFET is a lateral channel; the isolation region (6) is partially embedded in the vertical withstand voltage region (8), and the vertical channel region (7) of the diode region is located close to the diode On one side of the isolation region (6), the vertical channel region (7) is arranged close to the isolation region (6), and the vertical channel region (7) is partially embedded in the N-lateral drift region (5) located on the right side of the isolation region (6). ); the channel length of the vertical channel region (7) is adjustable; The metal field plate of the diode anode (11) extends downward to the longitudinal channel region (7) to form a longitudinal field plate (17). 2 . The power integrated chip incorporating a vertical channel structure according to claim 1 , wherein the MOSFET and the diode are fabricated laterally on the same wafer and are interconnected at the cell level. 3 . 3. The power integrated chip of claim 1, characterized in that: the source (1) of the MOSFET is grounded, and the drain (10) of the MOSFET is shorted to the diode anode (11) to form the drain of the MOSFET A short-circuiting part (3) with the anode of the diode; the short-circuiting part (3) between the drain of the MOSFET and the anode of the diode is located above the isolation region (6); other electrodes of the MOSFET and the diode are drawn out and connected to an external circuit. 4 . The power integrated chip incorporating a vertical channel structure according to claim 1 , wherein the MOSFET is a lateral MOSFET and the diode is a Schottky diode. 5 .

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