CN113032317A - Method and device for PCIE (peripheral component interface express) signal expansion based on server - Google Patents
Method and device for PCIE (peripheral component interface express) signal expansion based on server Download PDFInfo
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The invention discloses a PCIE signal expansion method and equipment based on a server, wherein the method is to respectively expand two main Oculink interfaces on the server into two Oculink expansion interfaces, and the expansion method of any main Oculink interface comprises the following steps: according to the PCIE signal expansion method, a main Oculink interface acquires two paths of PCIE multiplied by 4 from a server host through an Oculink cable and respectively transmits the two paths of PCIE multiplied by 4 to two PCIE repeaters, and any PCIE repeater expands the corresponding path of PCIE multiplied by 4 into two paths of PCIE multiplied by 2 and simultaneously transmits the two paths of PCIE multiplied by 2 to the corresponding Oculink expansion interface; in the reset signal extension method, a main Oculink interface transmits two paths of reset signals acquired from a server host to two Oculink extension interfaces through an NMOS drive circuit respectively; according to the clock signal extension method, two clock chips respectively transmit clock signals acquired from a main Oculink interface to corresponding Oculink extension interfaces.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a PCIE signal expansion method and equipment based on a server.
Background
In recent years, with the rapid development of intelligent applications, the application of a centralized video monitoring system is also more and more extensive, a streaming server is used as a main data processing center, the requirement on the processing capability of the streaming server is higher and higher, when the server needs to increase performance and improve the server density, some external expansion devices, such as application of an accelerator card with a standard hard disk size and using U.2 (also known as SFF-8639) as an interface, are required to be added, but due to the limitation of the structural space of a server motherboard, more expansion devices cannot be added, and therefore, a PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) adapter card needs to be designed to expand PCIE signals of the server motherboard, and the use of the acceleration devices is matched, so that the server density is improved, and the server processing capability is enhanced.
The Oculink is an interface specification supporting PCIE 4.0, and is widely applied to a server motherboard, but because the internal space of the server is limited, the configuration of the motherboard interface is limited by a certain condition, and the number of Oculink interfaces that can be used to connect external devices is also limited, a method for expanding the Oculink interface on the server motherboard is needed to meet the expansion requirement of more hardware acceleration devices.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method and device for expanding a PCIE signal based on a server, where two Oculink interfaces are expanded into four Oculink interfaces, so as to implement expansion of a PCIE signal on a server motherboard, so as to improve the diversity of external devices that can be used in a server in a matching manner, increase the server density, and enhance the processing capability of the server.
In order to achieve the above object, the present invention provides a method for expanding a signal based on a PCIE of a server, where two main Oculink interfaces on the server are respectively expanded into two Oculink expansion interfaces and are expanded into four Oculink expansion interfaces altogether, where an expansion method for expanding any one main Oculink interface into two Oculink expansion interfaces includes a PCIE signal expansion method, a reset signal expansion method, and a clock signal expansion method, where:
the PCIE signal expansion method comprises the following specific processes:
step 101: the main Oculink interface acquires a PCIE signal from a server host through an Oculink cable, and transmits the acquired two-channel PCIE multiplied by 4 to a first PCIE repeater and a second PCIE repeater respectively;
step 102: any PCIE repeater expands a corresponding one-channel PCIE x 4 into a two-channel PCIE x 2 and simultaneously transmits the two-channel PCIE x 2 to a corresponding Oculink expansion interface;
the specific process of the reset signal extension method is as follows:
step 200: the main Oculink interface transmits two paths of reset signals acquired from a server host to the two Oculink expansion interfaces through the NMOS drive circuit respectively; and
the specific process of the clock signal extension method is as follows:
step 300: the two clock chips respectively transmit the clock signals acquired from the main Oculink interface to the corresponding Oculink expansion interfaces.
In an embodiment of the present invention, the specific transmission process of step 102 is:
the first PCIE repeater expands a corresponding one-channel PCIE multiplied by 4 into a two-channel PCIE multiplied by 2 and transmits the two-channel PCIE multiplied by 2 to a first Oculink expansion interface;
the second PCIE repeater expands the corresponding one-channel PCIE × 4 into two-channel PCIE × 2, and transmits the two-channel PCIE × 2 to the second Oculink expansion interface.
In an embodiment of the present invention, the transmission process of the clock signal in step 300 specifically includes:
the main Oculink interface transmits clock signals to input ends of a first clock chip and a second clock chip respectively, then two output ends of the first clock chip input the clock signals to a first Oculink expansion interface, and two output ends of the second clock chip input the clock signals to a second Oculink expansion interface.
In order to achieve the above object, the present invention further provides a device based on PCIE signal expansion of a server, including:
a board card;
the two main Oculink interfaces are arranged on the board card and are respectively a first main Oculink interface and a second main Oculink interface;
the four PCIE repeaters are arranged on the board card and respectively comprise a first PCIE repeater, a second PCIE repeater, a third PCIE repeater and a fourth PCIE repeater, wherein the first PCIE repeater and the second PCIE repeater are connected with the first main Oculink interface, and the third PCIE repeater and the fourth PCIE repeater are connected with the second main Oculink interface;
the four Oculink expansion interfaces are arranged on the board card and respectively include a first Oculink expansion interface, a second Oculink expansion interface, a third Oculink expansion interface and a fourth Oculink expansion interface, wherein the four Oculink expansion interfaces are correspondingly connected with the four PCIE repeaters;
the NMOS drive circuits are arranged on the board card and respectively comprise a first NMOS drive circuit, a second NMOS drive circuit, a third NMOS drive circuit and a fourth NMOS drive circuit, wherein each NMOS drive circuit is respectively connected with one main Oculink interface and the corresponding Oculink expansion interface; and
the four clock chips are arranged on the board card and respectively include a first clock chip, a second clock chip, a third clock chip and a fourth clock chip, wherein each clock chip is connected with one of the main Oculink interfaces and the corresponding Oculink expansion interface.
In an embodiment of the present invention, each primary Oculink interface includes two channels PCIE × 4.
In an embodiment of the present invention, each Oculink expansion interface includes two channels PCIE × 2.
In an embodiment of the present invention, a specific connection manner between the four Oculink expansion interfaces and the four PCIE repeaters is as follows:
the first Oculink expansion interface is connected with the first PCIE repeater, the second Oculink expansion interface is connected with the second PCIE repeater, the third Oculink expansion interface is connected with the third PCIE repeater, and the fourth Oculink expansion interface is connected with the fourth PCIE repeater.
In an embodiment of the present invention, the connection between each NMOS driving circuit and one of the main Oculink interfaces and the corresponding Oculink expansion interface specifically includes:
the first NMOS drive circuit is respectively connected with the first main Oculink interface and the first Oculink extension interface, the second NMOS drive circuit is respectively connected with the first main Oculink interface and the second Oculink extension interface, the third NMOS drive circuit is respectively connected with the second main Oculink interface and the third Oculink extension interface, and the fourth NMOS drive circuit is respectively connected with the second main Oculink interface and the fourth Oculink extension interface.
In an embodiment of the present invention, each clock chip includes an input terminal and two output terminals, and a specific connection manner of each clock chip is as follows:
the input end of the first clock chip and the input end of the second clock chip are both connected to the first main Oculink interface, two output ends of the first clock chip are connected with the first Oculink expansion interface, and two output ends of the second clock chip are connected with the second Oculink expansion interface;
the input end of the third clock chip and the input end of the fourth clock chip are both connected to the second main Oculink interface, two output ends of the third clock chip are connected with the third Oculink expansion interface, and two output ends of the fourth clock chip are connected with the fourth Oculink expansion interface.
In an embodiment of the present invention, each of the main Oculink interfaces is connected to the server motherboard through an Oculink cable.
Compared with the prior art, the expansion method and the equipment based on the PCIE signal of the server can realize the expansion of the PCIE signal of the mainboard of the server on the basis of finishing the normal communication between the expansion equipment and the mainboard of the server, improve the diversity of external equipment which can be used by the server in a matching way, increase the density of the server and enhance the processing capacity of the server.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram illustrating an expansion method for expanding one Oculink interface into two according to an embodiment of the present invention;
FIG. 2 is a diagram of an apparatus according to an embodiment of the present invention.
Description of reference numerals: 101-main Oculink interface; 1021-PCIE repeater 1; 1022-PCIE repeater 2; 1031-clock chip 1; 1032-clock chip 2; 1041-Oculink expansion interface 1; 1042-Oculink expansion interface 2; 1051. 1052-NMOS drive circuit; 20-board card; 2011-main Oculink interface 1; 2012-main Oculink interface 2; 2021-PCIE repeater 1; 2022-PCIE repeater 2; 2023-PCIE repeater 3; 2024-PCIE repeater 4; 2031-clock chip 1; 2032-clock chip 2; 2033-clock chip 3; 2034-clock chip 4; 2041-Oculink expansion interface 1; 2042-Oculink expansion interface 2; 2043-Oculink expansion interface 3; 2044-Oculink expansion interface 4; 2051 — NMOS drive circuit 1; 2052 — NMOS drive circuit 2; 2053 — NMOS drive circuit 3; 2054 — NMOS drive circuit 4.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
Example one
Fig. 1 is a schematic diagram of an expansion method for expanding one Oculink interface into two in an embodiment of the present invention, and as shown in fig. 1, this embodiment provides a method for expanding a PCIE signal based on a server, where two main Oculink interfaces on the server are respectively expanded into two Oculink expansion interfaces and are jointly expanded into four Oculink expansion interfaces, where an expansion method for expanding any one main Oculink interface into two Oculink expansion interfaces includes a PCIE signal expansion method, a Reset Signal (RST) expansion method, and a clock signal (CLK) expansion method, where:
the PCIE signal expansion method comprises the following specific processes:
step 101: a main Oculink interface (Oculink Connector A) (101) acquires a PCIE signal from a server host through an Oculink Cable (Cable), and transmits the acquired two paths (Lane) PCIE multiplied by 4 to a PCIE Repeater (Repeater)1(1021) and a PCIE Repeater (Repeater)2(1022) respectively;
step 102: any PCIE Repeater (Repeater) (1021 or 1022) expands the corresponding one-Lane (Lane) PCIE × 4 into two-Lane (Lane) PCIE × 2, and transmits the two-Lane (Lane) PCIE × 2 to the corresponding Oculink expansion interface (1041 or 1042) at the same time;
in this embodiment, the specific transmission process of step 102 is as follows:
a PCIE Repeater (Repeater)1(1021) expands a corresponding one-Lane (Lane) PCIE × 4 into a two-Lane (Lane) PCIE × 2, and transmits the two-Lane PCIE × 2 to an Oculink expansion interface (Oculink Connector)1 (1041);
the PCIE Repeater (Repeater)2(1022) expands the corresponding one-Lane (Lane) PCIE × 4 into a two-Lane (Lane) PCIE × 2, and transmits the two-Lane PCIE × 2 to the Oculink expansion interface (Oculink Connector)2 (1042).
The specific process of the Reset Signal (RST) extension method is as follows:
step 200: the method comprises the following steps that a main Oculink interface (Oculink Connector A) (101) transmits two paths of Reset Signals (RST) acquired from a server host to an Oculink expansion interface 1(1041) and an Oculink expansion interface 2(1042) through an N-Metal-Oxide-Semiconductor (N-Metal-Oxide-Semiconductor) driving circuit respectively;
the specific process of the clock signal (CLK) expansion method is as follows:
step 300: the two Clock (CLK) chips (1031 and 1032) respectively transmit the clock signal (CLK) acquired from the main Oculink Connector a (101) to the corresponding Oculink expansion interface (1041 or 1042).
In this embodiment, the transmission process of the clock signal (CLK) in step 300 specifically includes:
the master Oculink Connector a (101) transmits the clock signal (CLK) to the inputs of the Clock (CLK) chip 1(1031) and the Clock (CLK) chip 2(1032), respectively, and then two outputs of the Clock (CLK) chip 1(1031) input the clock signal (CLK) to the Oculink expansion interface 1(1041) and two outputs of the Clock (CLK) chip 2(1032) input the clock signal (CLK) to the Oculink expansion interface 2 (1042).
Through the extension of this embodiment, two paths (Lane) PCIE × 4 of the main Oculink interface (101) are respectively extended to four paths (Lane) PCIE × 2 through two PCIE repeaters (Repeater), each two paths (Lane) PCIE × 2 is further integrated into one Oculink extension interface, and the two Oculink extension interfaces are extended together, and the Reset Signal (RST) and the clock signal (CLK) are also respectively extended through an NMOS driver circuit (NMOS) and a Clock (CLK) chip, so that each Oculink extension interface (1041 and 1042) can acquire the inputs of the two clock signals (CLK), the two paths of Reset Signals (RST), and the two paths (Lane) PCIE × 2. Similarly, the other main Oculink interface may also extend two Oculink extension interfaces, so that the two main Oculink interfaces are extended into four Oculink extension interfaces for access by more hardware devices.
Example two
Fig. 2 is an apparatus architecture diagram according to an embodiment of the present invention, and as shown in fig. 2, the embodiment provides an apparatus for PCIE signal expansion based on a server, so as to implement the foregoing method for PCIE signal expansion, which includes:
a board card (20);
the two main Oculink interfaces are arranged on the board card (20) and are used for being connected with a server mainboard, and the main Oculink interfaces are a main Oculink interface 1(2011) and a main Oculink interface 2(2012), respectively;
four PCIE repeaters (Repeater) disposed on the board card (20) for expanding a path of PCIE × 4 into two paths of PCIE × 2, which are PCIE repeaters 1(2021), PCIE repeaters 2(2022), PCIE repeaters 3(2023), and PCIE repeaters 4(2024), respectively, where PCIE Repeater 1(2021) and PCIE Repeater 2(2022) are connected to main Oculink interface 1(2011), and PCIE Repeater 3(2023) and PCIE Repeater 4(2024) are connected to main Oculink interface 2 (2012);
the four Oculink expansion interfaces are arranged on the board card (20) and respectively include an Oculink expansion interface 1(2041), an Oculink expansion interface 2(2042), an Oculink expansion interface 3(2043) and an Oculink expansion interface 4(2044), wherein the four Oculink expansion interfaces (2041, 2042, 2043 and 2044) are correspondingly connected with four PCIE repeaters (Repeater) (2021, 2022, 2023 and 2024);
the NMOS drive circuits (2051, 2052, 2053 and 2054) are arranged on the board card (20) and are respectively an NMOS drive circuit 1(2051), an NMOS drive circuit 2(2052), an NMOS drive circuit 3(2053) and an NMOS drive circuit 4(2054), wherein each NMOS drive circuit is respectively connected with one of the main Oculink interfaces and the corresponding Oculink extension interface;
the four clock chips are arranged on the board card (20), and are respectively a clock chip 1(2031), a clock chip 2(2032), a clock chip 3(2033) and a clock chip 4(2034), wherein each clock chip is respectively connected with one of the main Oculink interfaces (2011 or 2012) and the corresponding Oculink expansion interface (2041, 2042, 2043 or 2044).
In the embodiment, each of the main Oculink interfaces (2011 and 2012) includes two lanes (Lane) PCIE × 4.
In the embodiment, each Oculink expansion interface (2041, 2042, 2043, and 2044) includes two lanes (Lane) PCIE × 2.
In this embodiment, the specific connection mode between the four Oculink expansion interfaces (2041, 2042, 2043, and 2044) and the four PCIE repeaters (repeaters) (2021, 2022, 2023, and 2024) is as follows:
the Oculink expansion interface 1(2041) is connected with the PCIE repeater 1(2021), the Oculink expansion interface 2(2042) is connected with the PCIE repeater 2(2022), the Oculink expansion interface 3(2043) is connected with the PCIE repeater 3(2023), and the Oculink expansion interface 4(2044) is connected with the PCIE repeater 4 (2024).
In this embodiment, the connection between each NMOS driving circuit and one of the main Oculink interfaces and the corresponding Oculink expansion interface specifically includes:
the NMOS driver 1(2051) is connected to the main Oculink interface 1(2011) and the Oculink extension interface 1(2041), respectively, the NMOS driver 2(2052) is connected to the main Oculink interface 1(2011) and the Oculink extension interface 2(2042), respectively, the NMOS driver 3(2053) is connected to the main Oculink interface 2(2012) and the Oculink extension interface 3(2043), respectively, and the NMOS driver 4(2054) is connected to the main Oculink interface 2(2012) and the Oculink extension interface 2044 (2044), respectively.
In this embodiment, each clock chip (2031, 2032, 2033, and 2034) includes one input terminal and two output terminals, and the specific connection mode of each clock chip is as follows:
the input end of a clock chip 1(2031) and the input end of a clock chip 2(2032) are both connected to a main Oculink interface 1(2011), two output ends of the clock chip 1(2031) are connected with an Oculink expansion interface 1(2041), and two output ends of the clock chip 2(2032) are connected with an Oculink expansion interface 2 (2042);
the input end of the clock chip 3(2033) and the input end of the clock chip 4(2034) are both connected to the main Oculink interface 2(2012), two output ends of the clock chip 3(2033) are connected to the Oculink expansion interface 3(2043), and two output ends of the clock chip 4(2034) are connected to the Oculink expansion interface 4 (2044).
In this embodiment, each main Oculink interface is connected to the server motherboard through an Oculink cable, where the length of each Oculink cable may be customized according to a requirement, and the length of each Oculink cable is not limited in this embodiment, so as to meet a matching requirement of different interfaces according to an actual situation, and have higher flexibility.
Compared with the prior art, the expansion method and the equipment based on the PCIE signal of the server can realize the expansion of the PCIE signal of the mainboard of the server on the basis of finishing the normal communication between the expansion equipment and the mainboard of the server, improve the diversity of external equipment which can be used by the server in a matching way, increase the density of the server and enhance the processing capacity of the server.
Those of ordinary skill in the art will understand that: the figures are merely schematic representations of one embodiment, and the blocks or flow diagrams in the figures are not necessarily required to practice the present invention.
Those of ordinary skill in the art will understand that: modules in the devices in the embodiments may be distributed in the devices in the embodiments according to the description of the embodiments, or may be located in one or more devices different from the embodiments with corresponding changes. The modules of the above embodiments may be combined into one module, or further split into multiple sub-modules.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for expanding PCIE signals based on a server is characterized in that two main Oculink interfaces on the server are respectively expanded into two Oculink expansion interfaces and are expanded into four Oculink expansion interfaces in total, wherein the expansion method for expanding any one main Oculink interface into two Oculink expansion interfaces comprises a PCIE signal expansion method, a reset signal expansion method and a clock signal expansion method, wherein:
the PCIE signal expansion method comprises the following specific processes:
step 101: the main Oculink interface acquires a PCIE signal from a server host through an Oculink cable, and transmits the acquired two-channel PCIE multiplied by 4 to a first PCIE repeater and a second PCIE repeater respectively;
step 102: any PCIE repeater expands a corresponding one-channel PCIE x 4 into a two-channel PCIE x 2 and simultaneously transmits the two-channel PCIE x 2 to a corresponding Oculink expansion interface;
the specific process of the reset signal extension method is as follows:
step 200: the main Oculink interface transmits two paths of reset signals acquired from a server host to the two Oculink expansion interfaces through the NMOS drive circuit respectively; and
the specific process of the clock signal extension method is as follows:
step 300: the two clock chips respectively transmit the clock signals acquired from the main Oculink interface to the corresponding Oculink expansion interfaces.
2. The method according to claim 1, wherein the specific transmission procedure of step 102 is:
the first PCIE repeater expands a corresponding one-channel PCIE multiplied by 4 into a two-channel PCIE multiplied by 2 and transmits the two-channel PCIE multiplied by 2 to a first Oculink expansion interface;
the second PCIE repeater expands the corresponding one-channel PCIE × 4 into two-channel PCIE × 2, and transmits the two-channel PCIE × 2 to the second Oculink expansion interface.
3. The method according to claim 1, wherein the transmission process of the clock signal in step 300 specifically comprises:
the main Oculink interface transmits clock signals to input ends of a first clock chip and a second clock chip respectively, then two output ends of the first clock chip input the clock signals to a first Oculink expansion interface, and two output ends of the second clock chip input the clock signals to a second Oculink expansion interface.
4. A device based on server PCIE signal expansion, configured to implement the method of any one of claims 1 to 3, where the device includes:
a board card;
the two main Oculink interfaces are arranged on the board card and are respectively a first main Oculink interface and a second main Oculink interface;
the four PCIE repeaters are arranged on the board card and respectively comprise a first PCIE repeater, a second PCIE repeater, a third PCIE repeater and a fourth PCIE repeater, wherein the first PCIE repeater and the second PCIE repeater are connected with the first main Oculink interface, and the third PCIE repeater and the fourth PCIE repeater are connected with the second main Oculink interface;
the four Oculink expansion interfaces are arranged on the board card and respectively include a first Oculink expansion interface, a second Oculink expansion interface, a third Oculink expansion interface and a fourth Oculink expansion interface, wherein the four Oculink expansion interfaces are correspondingly connected with the four PCIE repeaters;
the NMOS drive circuits are arranged on the board card and respectively comprise a first NMOS drive circuit, a second NMOS drive circuit, a third NMOS drive circuit and a fourth NMOS drive circuit, wherein each NMOS drive circuit is respectively connected with one main Oculink interface and the corresponding Oculink expansion interface; and
the four clock chips are arranged on the board card and respectively include a first clock chip, a second clock chip, a third clock chip and a fourth clock chip, wherein each clock chip is connected with one of the main Oculink interfaces and the corresponding Oculink expansion interface.
5. The device of claim 4, wherein each primary Oculink interface comprises two lanes PCIE x 4.
6. The device of claim 4, wherein each Oculink expansion interface comprises two lanes PCIE x 2.
7. The device according to claim 4, wherein the specific connection manner between the four Oculink expansion interfaces and the four PCIE repeaters is as follows:
the first Oculink expansion interface is connected with the first PCIE repeater, the second Oculink expansion interface is connected with the second PCIE repeater, the third Oculink expansion interface is connected with the third PCIE repeater, and the fourth Oculink expansion interface is connected with the fourth PCIE repeater.
8. The device according to claim 4, wherein the connection between each NMOS driver circuit and one of the main Oculink interface and the corresponding Oculink extension interface is specifically:
the first NMOS drive circuit is respectively connected with the first main Oculink interface and the first Oculink extension interface, the second NMOS drive circuit is respectively connected with the first main Oculink interface and the second Oculink extension interface, the third NMOS drive circuit is respectively connected with the second main Oculink interface and the third Oculink extension interface, and the fourth NMOS drive circuit is respectively connected with the second main Oculink interface and the fourth Oculink extension interface.
9. The apparatus of claim 4, wherein each clock chip comprises an input terminal and two output terminals, and each clock chip is connected in a manner that:
the input end of the first clock chip and the input end of the second clock chip are both connected to the first main Oculink interface, two output ends of the first clock chip are connected with the first Oculink expansion interface, and two output ends of the second clock chip are connected with the second Oculink expansion interface;
the input end of the third clock chip and the input end of the fourth clock chip are both connected to the second main Oculink interface, two output ends of the third clock chip are connected with the third Oculink expansion interface, and two output ends of the fourth clock chip are connected with the fourth Oculink expansion interface.
10. The apparatus of claim 4, wherein each of the main Oculink interfaces is connected to the server motherboard by an Oculink cable.
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