CN113030886B - High-speed target range migration correction method - Google Patents
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Abstract
The invention relates to a high-speed target range migration correction method, which utilizes a DSP and an FPGA signal processing hardware platform and comprises the following steps: generating a transmission signal; acquiring an echo signal; down-conversion of echo signal to baseband, filtering and doing FPerforming FT treatment; performing coherent accumulation on the FFT processing signal to obtain a target Doppler frequency f d (ii) a The FPGA generates corresponding two-phase coding signals; generating a frequency value f by using a DDS core in an FPGA d +f c The compensation signal S with single frequency is subjected to down-conversion, filtering and pulse pressure processing; and the DSP reads the value after the pulse pressure processing and carries out distance measurement processing. The method is simple, easy to realize hardware, low in complexity, small in calculated amount in the processing process and easy to realize.
Description
Technical Field
The invention relates to the field of radars, in particular to search for a high-speed target and tracking distance walking compensation of a radar with a phase coding system, which can be applied to various types of radar systems and the field of radar algorithms.
Background
The existing method for correcting the distance walk of the high-speed target is mainly realized through interpolation operation or multi-dimensional parameter search, the problems of large operation amount, more complex implementation mode and the like exist, and particularly when the target has acceleration, the method is not beneficial to the rapid real-time detection of the radar on the high-speed target.
Patent "a PD radar range walk correction and coherent accumulation detection" (patent application No. 201710665228.6, patent publication No. CN 107329138A) proposes to search and obtain a shift angle of an echo data coordinate after pulse compression by traversal, perform shift transformation on each coordinate of live peeling data by using the shift angle obtained by search to correct the range walk of a high-speed moving target, and finally perform fast fourier transform of a slow time domain on the echo data after range walk correction to realize coherent accumulation detection of target energy. The invention effectively corrects the distance walk in the accumulation process, greatly improves the coherent accumulation gain, but the angle estimation value is not easy to settle and is not beneficial to being realized by engineering.
A Doppler measurement method for solving target span-separation unit walking (patent application number: CN201810694168.5, patent publication number: CN 109031274A) proposes to use a simultaneous multi-order MTD filter, solves the problem of signal-to-noise ratio loss caused by the span-separation unit walking of targets with different speeds, and uses a cross-contrast simultaneous multi-order MTD filter to realize accurate measurement of target speeds; because different filter banks have different accumulation time, the signal-to-noise ratio loss caused by the span unit caused by the target motion can be reduced, and the probability of detecting the small target can be improved under the condition that no signal-to-noise ratio loss can be achieved in a partial speed range. It is not implemented by using engineering.
The document "high-speed target coherent accumulation method based on improved Keystone transform" (modern radar, volume 38, 4 of 2016) proposes a Keystone transform method based on scale transform, which effectively solves the problem of distance walk of high-speed target signals, improves coherent accumulation performance of weak echo signals, effectively inhibits the effect of 'semi-blind speed point', and improves coherent accumulation effect. However, the algorithm has long running time and large data amount calculation amount, and is not suitable for engineering realization.
The document "a method for piecewise compensation of distance walking" (fire control radar technology "vol.46, no. 2, 2017) proposes that envelope compensation is implemented by adjusting matching coefficients according to echo characteristics of a moving target, and the amount of calculation is reduced by piecewise compensation. The order of the matched filtering required by the algorithm is increased according to the number of sampling points corresponding to the maximum time shift possibly occurring in the envelope, and the complexity of the system is increased.
The traditional range migration correction method is divided into three categories: (1) The envelope shift interpolation method is used for reconstructing the complex envelope of the sampling signal by using an interpolation algorithm and then carrying out pulse-to-pulse shift processing on the envelope signal to realize envelope alignment. In the traditional envelope shift interpolation method, under the condition of more sampling values, the interpolation operation greatly increases the operation amount of shift. (2) The frequency domain correction method is to multiply the delay factor on the frequency domain to compensate the envelope walking difference between each pulse, and in the narrow-band system, the frequency domain pulse computation amount and complexity are larger than the time domain pulse compression. (3) The Keystone transform method needs to perform fourier transform on a signal after pulse compression in a fast time dimension and then perform scale transform on a frequency domain signal in a slow time dimension, and thus the amount of calculation is large under the condition of a large number of accumulated pulses.
Disclosure of Invention
The invention breaks the barrier of the traditional range migration compensation, utilizes a DSP (digital signal processor) and an FPGA (field programmable gate array) signal processing hardware platform and aims to solve the problems of detection of a high-speed target by a radar under the condition of no prior information of the target speed, tracking of the target after range compensation and measurement of the range and the speed.
In order to achieve the aim, the invention provides a high-speed target range migration correction method, which comprises the following specific steps: utilize DSP and FPGA signal processing hardware platform, include the following steps:
s1: setting flag fft _ flag =1 in DSP and sending to FPGA, where the FPGA generates carrier frequency f c A pulse transmitting signal with a specific pulse width;
s2: sampling an echo signal of a transmitting signal after being reflected by a target, and carrying out down-conversion to a baseband, filtering and FFT processing on the echo signal in an FPGA;
s3: the DSP reads the signal after FFT processing in an EDMA mode in a ping-pong manner and performs CFAR detection;
s4: the DSP performs coherent accumulation on the signals after CFAR detection to obtain a target Doppler frequency fd, and calculates a target speed v, a distance compensation value, a target speed direction v _ dir and a set flag fft _ flag =0; the DSP converts the Doppler compensation value fd + f c The target speed direction v _ dir, the distance compensation value and fft _ flag =0 are transmitted to the FPGA;
s5: the FPGA counts the pulse repetition period of each echo signal, and the FPGA moves the position of a signal processing threshold according to the distance compensation value to ensure that data in each pulse repetition period in a frame of data are in the same distance unit, so that the signal sampled every time is positioned at the same position of the signal processing threshold;
s6: the FPGA receives an instruction fft _ flag =0 of the DSP, and the FPGA controls to generate a corresponding two-phase coding signal;
s7: sampling echo signals, and generating a frequency value f by using a DDS (direct digital synthesizer) core in an FPGA (field programmable gate array) d +f c The FPGA internal multiplier is used for carrying out down-conversion on the signal with the single frequency to obtain a down-conversion signal, and then the down-conversion signal is subjected to filtering and pulse pressure processing;
s8: and the DSP reads the value after the pulse pressure processing in the step S7 and carries out distance measurement processing.
Wherein the calculated target speed in the step S4 is
Wherein λ is the echo signal wavelength; the range compensation value is v · PRT, where PRT is the pulse repetition period of the echo signal.
The pulse pressure processing method in the step S7 specifically includes the following steps:
s71, setting the nth transmission signal as S (t, n):
wherein, c n As a pseudo-random sequence, c n E { -1,1}, N is the length of the pseudorandom sequence, T 1 Is the chip width of the pseudo-random sequence, f 0 Is a carrier frequency, n is a positive integer, u 0 (t) is a rectangular sub-pulse function,
s72: the echo signal is r (t, n):
wherein n is a positive integer, an initial position R 0 Echo delay of τ n ＝2(R 0 + nvT)/c, T is the transmitting pulse repetition period of the radar;
s73: calculating the speed v of the high-speed moving target by the DSP, sending a DSP distance compensation value vT to the FPGA, and carrying out distance walking compensation on each repetition frequency signal by the FPGA;
the resulting compensation signal is:
compared with the background technology, the invention has the following advantages:
1. the invention utilizes the combination of time and frequency domains for processing, and can achieve better compensation effect when the radar target of the phase coding system moves at high speed and reaches 2000 m/s;
2. in the invention, under the condition of unknown speed information, the FPGA carries out FFT processing on an echo signal, the DSP reads data after FFT, the speed ambiguity is solved by a lookup table method to obtain Doppler compensation frequency and accurately measure speed, and the FPGA carries out Doppler compensation and range migration correction on a target signal after reading so as to accurately measure the distance;
the DSP adds the calculated Doppler frequency fd and the carrier frequency fc to be sent to the FPGA, and the FPGA utilizes the DDS core to generate a down-conversion signal;
the FPGA generates down-conversion signals by utilizing a DDS core, multiplies the down-conversion signals by echo signals, and performs speed compensation while performing down-conversion;
5, the FPGA carries out range migration correction by using a mode of a speed v obtained by calculation of the DSP and a moving signal processing threshold of a pulse repetition period;
6. the data processing method is simple, is easy to realize by hardware, and provides possibility for real-time processing.
7. The invention has lower complexity, smaller calculation amount in the processing process and easy realization.
Drawings
FIG. 1 is a flow chart of the steps of a high-speed target range migration correction method of the present invention;
FIG. 2 shows the 256 coherent accumulation values of PRT before distance compensation at 2000 m/s;
FIG. 3 shows 256 coherent accumulation values of PRT after distance compensation at 2000 m/s.
Detailed Description
The present invention provides a method for correcting high-speed target range migration, which is further described in detail below with reference to the accompanying drawings and the detailed description.
As shown in fig. 1, the present invention provides a method for correcting a high-speed target range migration, comprising the following steps:
s1: after the power-on reset is finished, setting a flag fft _ flag =1 in the DSP, and sending the flag fft _ flag =1 to the FPGA, wherein the FPGA generates a transmitting signal with a carrier frequency of 60.5MHz and a pulse width of 100 us;
s2: sampling an echo signal (the echo signal is an intermediate frequency signal, and the carrier frequency is 60 MHz) by using a 40MHz clock, performing down-conversion to a baseband in an FPGA, filtering and performing FFT (fast Fourier transform algorithm);
specifically, 60MHz is used for down-conversion in FPGA, and the down-conversion method specifically comprises the following steps: the DDS core in the FPGA is used for generating a sine wave with a single frequency of 60MHz, and a multiplier core of the FPGA is used for multiplying the sine wave with the single frequency of 60MHz by an echo signal for down-conversion. And filtering and extracting the data after the down-conversion to 2MHz through the FIR core of the FPGA. And performing FFT processing on the filtered and extracted data through an FFT core, and ping-pong storing the data after the FFT processing in an SRAM.
S3: the DSP reads the data after FFT processing in an EDMA mode and performs constant false alarm probability (CFAR) detection;
s4: after the CFAR detects the signals, 256 echo signals are accumulated, the 256 signals are subjected to coherent accumulation, then a table look-up method is used for carrying out velocity ambiguity resolution, and the target Doppler frequency f is obtained d The Doppler compensation value (f) to be generated d + 60) MHz to FPGA, using formula
Calculating a target speed, wherein lambda is the wavelength of the echo signal; calculating a distance compensation value v.PRT, wherein PRT is the pulse repetition period of the echo signal; calculating a target speed direction v _ dir and setting a flag fft _ flag =0, and calculating a distance compensation value, the target speed direction v _ dir and a doppler compensation value (f) d + 60) MHz and flag fft flag =0 are passed toFPGA；
S5: counting each PRT (pulse repetition period) in the FPGA, wherein the FPGA moves the position of a signal processing threshold according to a distance walking value, ensures that data in each PRT in one frame of data (256 PRTs) are in the same distance unit, and ensures that the signal sampled each time is at the same position of the signal processing threshold;
s6: after the FPGA receives the flag fft _ flag =0, the FPGA controls to generate a two-phase coding signal;
s7: sampling echo signals, and generating a frequency f by using a DDS (direct digital synthesizer) core in an FPGA (field programmable gate array) d +60 single-frequency signals, and down-converting the sampled echo signals by using an FPGA internal multiplier; specifically, the FPGA multiplies a single frequency signal generated by the DDS by an echo signal by using a multiplier core, performs down-conversion and Doppler compensation, performs filtering and pulse pressure processing on data subjected to down-conversion and Doppler compensation, and stores the data subjected to pulse pressure processing in an SRAM (static random access memory);
s8: and the DSP reads the pulse pressure signal after the pulse pressure processing in the SRAM in the step S7, performs CFAR detection and then performs distance measurement processing.
The pulse pressure processing method in the step S7 specifically includes the following steps:
s71: let the nth transmit signal be s (t, n):
wherein, c n As a pseudo-random sequence, c n E { -1,1}, N is the length of the pseudorandom sequence, T 1 For the chip width of the pseudorandom sequence, f 0 Is a carrier frequency, n is a positive integer, u 0 (t) is a rectangular sub-pulse function,
s72: the target echo signal of the pulse is r (t, n):
wherein n is a positive integer, an initial position R 0 Echo delay of τ n ＝2(R 0 + nvT)/c, T is the emission pulse repetition period of the radar, and c is the speed of light;
s73: and the DSP accurately calculates the speed v, sends the distance walk vT to the FPGA, and the FPGA carries out distance walk compensation on each repetition frequency signal.
The resulting compensation signal is:
as shown in FIGS. 2 and 3, for the coherent accumulation values of the high-speed moving target before and after the distance compensation, the coordinate before the distance compensation is (99, 620,2.752e + 005), and the coordinate after the distance compensation is (99, 556,2.911e + 005).
In summary, compared with the background art, the invention has the following advantages:
the invention utilizes the combination of time and frequency domains to process, and can achieve better compensation effect when the radar target of the phase coding system moves at high speed and reaches 2000 m/s;
in the condition that speed information is unknown, the FPGA carries out FFT processing on an echo signal, the DSP reads data after FFT, the speed ambiguity is resolved through a lookup table method to obtain Doppler compensation frequency and accurately measure speed, and the FPGA carries out Doppler compensation and range migration correction on a target signal after reading so as to accurately measure the distance;
the DSP adds the calculated Doppler frequency fd and the carrier frequency fc to be sent to the FPGA, and the FPGA utilizes the DDS core to generate a down-conversion signal;
the FPGA generates a down-conversion signal by utilizing a DDS core, multiplies the down-conversion signal by an echo signal, and performs speed compensation while performing down-conversion;
the FPGA carries out range migration correction by using a speed v obtained by calculation of a DSP and a moving signal processing threshold of a pulse repetition period;
the data processing method is simple, is easy to realize by hardware, and provides possibility for real-time processing.
The invention has lower complexity, smaller calculation amount in the processing process and easy realization.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (3)
1. A high-speed target range migration correction method utilizes a DSP and an FPGA signal processing hardware platform, and is characterized by comprising the following steps:
s1: setting flag fft _ flag =1 in DSP and sending to FPGA, wherein carrier frequency f generated by FPGA c A pulse emission signal of a specific pulse width;
s2: sampling an echo signal of a transmitting signal after being reflected by a target, and carrying out down-conversion to a baseband, filtering and FFT processing on the echo signal in an FPGA;
s3: the DSP reads signals after FFT processing in an EDMA mode in a ping-pong manner and performs CFAR detection;
s4: the DSP performs coherent accumulation on the signals after CFAR detection to obtain a target Doppler frequency f d Calculating a target speed v, a distance compensation value, a target speed direction v _ dir and a set flag fft _ flag =0; the Doppler compensation value f is converted by the DSP d +f c Transmitting the target speed direction v _ dir, the distance compensation value and fft _ flag =0 to the FPGA;
s5: the FPGA counts the pulse repetition period of each echo signal, and the FPGA moves the position of a signal processing threshold according to the distance compensation value to ensure that data in each pulse repetition period in a frame of data are in the same distance unit, so that the signal sampled each time is positioned at the same position of the signal processing threshold;
s6: the FPGA receives an instruction fft _ flag =0 of the DSP, and the FPGA controls to generate a corresponding two-phase coding signal;
s7: sampling echo signals, and generating frequency by using DDS (direct digital synthesizer) core in FPGA (field programmable gate array)Value of f d +f c The FPGA internal multiplier is used for carrying out down-conversion on the signal with the single frequency to obtain a down-conversion signal, and then the down-conversion signal is subjected to filtering and pulse pressure processing;
s8: and the DSP reads the value after the pulse pressure processing in the step S7 and carries out distance measurement processing.
2. The high-speed target range migration correction method of claim 1, wherein the target velocity calculated in step S4 is
Wherein λ is the echo signal wavelength; the range compensation value is v · PRT, where PRT is the pulse repetition period of the echo signal.
3. The high-speed target range migration correction method of claim 1, wherein the pulse pressure processing method of step S7 specifically comprises the steps of:
s71, setting the nth transmission signal as S (t, n):
wherein, c n As a pseudo-random sequence, c n E { -1,1}, N is the length of the pseudorandom sequence, T 1 Is the chip width of the pseudo-random sequence, f 0 Is a carrier frequency, n is a positive integer, u 0 (t) is a rectangular sub-pulse function,
s72: echo signal r (t, n):
wherein n is a positive integer, an initial position R 0 Echo delay of τ n ＝2(R 0 + nvT)/c, wherein T is the repetition period of the emission pulse of the radar, and c is the speed of light;
s73: calculating the speed v of the high-speed moving target by the DSP, sending a distance compensation value vT to the FPGA by the DSP, and carrying out distance walking compensation on each repetition frequency signal by the FPGA;
the resulting compensation signal is:
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