CN113014243B - Method for realizing level mismatch ratio optimization of high-speed SST driver in PAM4 mode - Google Patents

Abstract

A method for optimizing the level mismatch ratio of the SST driver in PAM4 mode, which converts all input digital signals in binary form into thermometer codes; then records the level mismatch ratio of the output eye diagram, and converts the PAM4 eye diagram output by the transmitter The upper and lower levels of the middle eye are adjusted to the ideal level through digital loop control, thereby improving the output level mismatch ratio. The present invention improves the level mismatch ratio of the output eye diagram by means of group power supply, and optimizes the RLM value to 99.2%; automatically adjusts the power supply voltages of different groups by way of digital loop control, reducing area overhead and power consumption, Moreover, the calibration is performed in a low-speed loop, which can be applied to a transmitter with a higher-speed SST structure.

Description

Optimal implementation method of level mismatch ratio of high-speed SST driver in PAM4 mode

technical field

The invention relates to a technology in the communication field, in particular to a method for realizing the optimization of the level mismatch ratio of a high-speed SST driver in a PAM4 mode.

Background technique

Source-series-terminated (SST, Source-Series-Terminated) drivers and current-mode logic (CML) drivers are two mainstream driver structures. The SST driver has more advantages in power consumption, the static power consumption is only 1/4 of the corresponding CML driver, even in the case of full balance, the power consumption is only 1/2 of the CML structure and under the same power supply voltage A larger differential output swing can be achieved. In order to ensure impedance matching under PVT, SST is usually composed of switch resistors, poly resistors and MOS arrays. The impedance provided by the MOS array working in the linear region will change with the change of its drain-source voltage when it is balanced, and the output is PAM4 mode. When the level mismatch ratio (RLM, Ratio of Level Mismatch) becomes worse, the mismatched RLM value means that one of the three eyes of the PAM4 eye diagram will become smaller, which means that after passing through the same attenuated channel, the small The eye will be closed first, greatly increasing the bit error rate, so a good RLM value means a lower bit error rate. The prior art adopts the form of parasitic resistance to improve the linearity of the overall output voltage, but it is difficult to precisely control its value due to the uncertainty of the parasitic resistance of the power distribution network. In addition, by using the auxiliary DAC to connect additional branches in parallel to compensate the impedance provided by the pull-up and pull-down branches due to the increase of the drain-source voltage, the auxiliary DAC uses an additional look-up table to control according to the input pattern, but the look-up table will be A large amount of additional power consumption and area overhead are caused, and the timing of the lookup table of the auxiliary DAC is difficult to guarantee as the speed increases. At present, there is no RLM value optimization method that can be applied to the PAM4 mode of the SST driver at high speed.

Contents of the invention

Aiming at the above-mentioned deficiencies in the prior art, the present invention proposes a method for optimizing the level mismatch ratio of a high-speed SST driver in PAM4 mode, which solves the problem of level mismatch ratio when the SST driver is applied in PAM4 mode.

The present invention is achieved through the following technical solutions:

The invention relates to a method for optimizing the level mismatch ratio of an SST driver in PAM4 mode, converting all input digital signals in binary form into thermometer codes; then recording the level mismatch ratio of the output eye diagram, and converting the PAM4 signal output by the transmitter The upper and lower levels of the middle eye of the eye diagram are adjusted to the ideal level through digital loop control, thereby improving the output level mismatch ratio.

The SST driver includes: three groups of evenly divided SST slices connected to each other, wherein: the upper and lower groups are powered by the same voltage group, and the middle group is powered by another group of voltages.

The middle eye refers to the middle one of the three eye diagrams output by the transmitter in the PAM4 mode.

The digital code is converted into a thermometer code and applied in a low-speed transmitter by means of digital logic synthesis. Digital logic is used to synthesize a binary code into a logic circuit converted into a thermometer code. It is built in an analog manner at high speed. The ultimate goal is to ensure The timing of the decoding circuit is accurate. This form of converting the final slice into a thermometer also facilitates layout matching.

technical effect

The present invention overall solves the problem of signal-to-noise ratio difference caused by the RLM difference of the low-power SST driver under high-speed transmission, so that it is difficult to meet the requirement of the bit error rate required by the transmission protocol.

Compared with the prior art, the present invention realizes the slicing of the SST driver with thermometer code, divides them into three groups and adopts two groups of different power supply voltages to calibrate the RLM value in PAM4 mode, and the calibration is realized through a low-speed digital loop , improve the level mismatch ratio of the output eye diagram by grouping power supply, and realize the optimization of 99.2% of the level mismatch ratio; automatically adjust the power supply voltage of different groups by means of digital loop control, reducing the area cost and power consumption The above-mentioned digital calibration loop is calibrated at a low speed. After the calibration is completed, the two sets of level values are given to the actual working SST driver. The calibration is separated from the normal working mode and can be applied to higher-speed SST structures. transmitter.

Description of drawings

Fig. 1 is a circuit simplified diagram of the output voltage of the SST driver;

Figure 2 is a comparison diagram before and after level mismatch ratio calibration;

In the figure: a is the PAM4 output eye diagram before calibration; b is the PAM4 output eye diagram after calibration;

Fig. 3 is a schematic diagram of the structure of the embodiment.

Detailed ways

其中：

V_OC为开路电压，G_in为内阻导纳，G_load为负载导纳，G_up为上拉支路导纳，G_down为下拉支路导纳，V_DD为供电电压，该电压为R-DAC(电阻型数模转换器)或C-DAC(电容型数模转换器)产生。As shown in Figure 1, the source series-terminated driver model applied in this embodiment includes the pull-up branch admittance and pull-down branch admittance set between the supply voltage and the ground point, and the load between them admittance, the load admittance of the output voltage

in:

V _OC is the open circuit voltage, G _in is the internal resistance admittance, G _load is the load admittance, G _up is the pull-up branch admittance, G _down is the pull-down branch admittance, V _DD is the supply voltage, and this voltage is R -DAC (Resistive Digital-to-Analog Converter) or C-DAC (Capacitive Digital-to-Analog Converter) generation.

对于单端校准好，由于SST工作的对称性，那么差分输出电压也就为理想的

The ideal level of the source series-terminated driver refers to: for a single-ended voltage, the four ideal levels of the output are respectively

For single-ended calibration, due to the symmetry of SST work, the differential output voltage is ideal

V₀至V₃分别为从下往上的PAM4眼图的四个电平值。The level mismatch ratio RLM=((3×ES ₁ ), (3×ES ₂ ), (2-3×ES ₁ ), (2-3×ES ₂ )), wherein:

V ₀ to V ₃ are the four level values of the PAM4 eye diagram from bottom to top.

This embodiment relates to the implementation method of the level mismatch ratio optimization of the above-mentioned source series-terminated driver, which specifically includes: first recording the level mismatch ratio of the output eye diagram; then, before the transmitter works, through the switch calibration; , start the transmitter and record the level mismatch ratio of the transmitter output eye diagram; the data of each group level output in the obtained PAM4 mode is calculated according to the definition of the level mismatch ratio (RLM) in the PAM4 mode, Get the comparison results, as shown in Figure 2.

The conversion of the digital code into the thermometer code is realized by means of digital logic synthesis.

As shown in Figure 3, this embodiment relates to a system for implementing the above method, including: two SST drivers, a comparator, a low dropout voltage regulator regulator and a finite state machine, wherein: in each SST driver Contains three groups of slices, the input terminals of the first SST driver receive 110 and 001 respectively, the node input to the comparator is fixed, the first node 1 of the second SST driver is input to the other end of the comparator, and the comparator outputs the comparison result to a finite The state machine adjusts the upper and lower group slices of the first SST driver to make the output level to an ideal value. After the preliminary calibration is completed, the output node of the second SST driver is switched from the first node 1 to the third node 3, and the input of the first SST driver Switch to 000 on one side and 111 on the other side, and the comparator outputs the comparison result to the finite state machine to adjust the output power of the low dropout voltage regulator of the middle group slice of the first SST driver to complete the calibration.

The input of the P tube and the N tube of one side branch of the SST driver are consistent, and the input of the other side branch and the left side branch are pseudo-differential forms of 01.

The comparator is a low-speed high-precision analog comparator.

The finite state machine is realized through digital code synthesis.

As shown in FIG. 2 , graph a shows that the level mismatch ratio of the output eye diagram before calibration is 94%, and graph b shows that the level mismatch ratio of the output eye diagram after calibration is 99.2%.

After specific practical experiments, under the specific environment setting of the calibration loop, the values of V ₀ to V ₃ are obtained as -398.5mV, -133.3mV, 133.5mV, 400.2mV respectively. Substituting into the RLM value to calculate: V _mid = 0.85mV, ES ₁ = 0.3359, ES ₂ = 0.3322, RLM = ((3×ES ₁ ), (3×ES ₂ ), (2-3×ES ₁ ), ( 2−3×ES ₂ ))=0.992.

Compared with the prior art, the transmitter of the device at a high rate of 32Gb/s realizes RLM value calibration in the PAM4 mode.

The above specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principle and purpose of the present invention. The scope of protection of the present invention is subject to the claims and is not limited by the above specific implementation. Each implementation within the scope is bound by the invention.

Claims (5)

1. A method for realizing optimization of level mismatch ratio of an SST driver in a PAM4 mode is characterized in that all input binary digital signals are converted into thermometer codes; then recording the level mismatch ratio of the output eye pattern, and adjusting the upper and lower levels of the middle eye of the PAM4 eye pattern output by the transmitter to an ideal level through digital loop control, thereby improving the output level mismatch ratio;

the level mismatch ratio RLM = ((3 × ES) ₁ )，(3×ES ₂ )，(2-3×ES ₁ )，(2-3×ES ₂ ) In which:

V ₀ to V ₃ The four level values of the PAM4 eye diagram are from bottom to top respectively;

the ideal level is: the differential output voltage after single-end calibration is

2. The method for realizing the SST driver level mismatch ratio optimization in the PAM4 mode as claimed in claim 1, wherein the SST driver comprises: three groups of evenly divided SST slices connected to each other, wherein: the upper and lower groups are powered by the same group of voltage, and the middle group is powered by the other group of voltage.

3. The method for realizing the optimization of the SST driver level mismatch ratio in the PAM4 mode as claimed in claim 1, wherein the center eye refers to: the transmitter outputs one of the three eye patterns in the PAM4 mode.

4. The method for realizing the optimization of the level mismatch ratio of the SST driver in the PAM4 mode as claimed in claim 1, wherein the conversion, that is, the application of digital coding into thermometer codes in a low-speed transmitter is realized in a digital logic synthesis mode, a logic circuit for converting binary codes into thermometer codes is synthesized by using digital logic, and the logic circuit is built in an analog mode at a high speed so as to ensure the accurate time sequence of a decoding circuit.

5. An SST driver level mismatch ratio optimization implementation circuit in PAM4 mode, for implementing the method as claimed in any one of claims 1-4, comprising: two SST drivers, a comparator, a low dropout regulator and a finite state machine, wherein: each SST driver comprises three groups of slices, wherein the input end of a first SST driver receives 001 and 110 respectively, the node input to a comparator is fixed, the first node of a second SST driver is input to the other end of the comparator, the comparator outputs a comparison result to a finite state machine to adjust the upper and lower groups of slices of the first SST driver to enable the output level to reach an ideal value, the output node of the second SST driver is switched to a third node from the first node after preliminary calibration is completed, the input of the first SST driver is switched to 000 on one side and 111 on the other side, and the comparator outputs the comparison result to the finite state machine to adjust the output power supply of the low-dropout regulator of the middle group of slices of the first SST driver to complete calibration.

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