CN113009516A

CN113009516A - Independent double-channel navigation enhanced satellite receiver

Info

Publication number: CN113009516A
Application number: CN202110421147.8A
Authority: CN
Inventors: 刘杰; 彭理; 汤长江; 吴强; 李辰运; 汪恒冉; 张宇
Original assignee: Beijing University of Technology
Current assignee: Beijing University of Technology
Priority date: 2021-04-19
Filing date: 2021-04-19
Publication date: 2021-06-22
Anticipated expiration: 2041-04-19
Also published as: CN113009516B

Abstract

The valve discloses an independent dual-channel navigation augmentation satellite receiver. It consists of navigation antenna 01, navigation antenna 02, L-type matching circuit, two-stage band-pass filter circuit, three-stage low-noise amplifier circuit, RX3701 and baseband processing circuit. The electromagnetic wave signals received by the navigation antenna 01 and the navigation antenna 02 respectively pass through the three-stage low-noise amplifier circuit and the two-stage band-pass filter circuit and then enter the multi-mode and multi-frequency radio frequency receiving circuit. After the signal is processed by the radio frequency receiving circuit, it passes through the OUT1 and The two output channels of OUT2 respectively output the 4-bit I/Q signal processed by each channel to the baseband processing circuit. The LEO signal demodulation is performed on the respective 4-bit I/Q signals of the input OUT1 and OUT2 channels through the software modules on the ARM0, ARM1 and FPGA processors of the ZYNQ7045 in the baseband processing circuit. The final receiver sends the calculated information to the computer through Gigabit Ethernet for processing.

Description

Independent double-channel navigation enhanced satellite receiver

Technical Field

The invention relates to the technical field of satellite navigation and the field of microwave circuit design, in particular to an independent double-channel navigation enhanced satellite receiver.

Background

The existing satellite receiver is mainly used for receiving positioning signals of a Global Positioning System (GPS) or a Beidou navigation system, and under the special condition that both the GPS and the Beidou navigation system are interfered, the satellite receiver cannot realize target positioning, so that an independent dual-channel satellite receiver needs to be designed, wherein one receiving channel is used for receiving a special satellite positioning signal, and a single-satellite positioning function can be realized. Meanwhile, in order to enable the current satellite to have higher information rate and broadcast more precise correction information, the special satellite receiving channel can also provide a navigation enhancement function for a Global Positioning System (GPS) or a Beidou navigation system. The navigation enhancement channel can provide satellite clock error, satellite orbit parameters, ionosphere correction parameters and load conditions, and is beneficial to improving positioning precision and accelerating positioning convergence time.

Disclosure of Invention

The invention aims to provide an independent dual-channel navigation enhanced satellite receiver. The receiver supports independent dual-channel multi-mode reception and has high sensitivity and strong anti-interference capability. Under the condition that a Global Positioning System (GPS) and a Beidou navigation system are interfered, the receiver can still receive a special satellite positioning signal through one of the receiving channels, so that single-satellite positioning is realized. The receiver also has strong baseband processing capability, so that the receiver not only can reduce the time required by positioning convergence, but also can support the functions of multimode receiving demodulation, decoding, direct output of positioning information, time service and the like. The receiver has small size, simple input interface and output interface capable of being connected to computer via network cable.

The technical scheme adopted by the invention for solving the technical problems is as follows: an independent two-channel navigation enhanced satellite receiver is designed under the size of 100mm 70mm 30mm, and has two receiving channels of RX1 and RX2, wherein each receiving channel consists of an independent navigation antenna, an L-shaped matching circuit, a two-stage band-pass filter circuit, a three-stage low-noise amplifier circuit, a radio frequency receiving chip RX3701 and a baseband processing circuit.

According to the independent dual-channel navigation enhanced satellite receiver, the RX3701 radio frequency chip is taken as a core to design a multi-mode multi-frequency radio frequency receiving circuit, and the receiver can realize independent dual-channel multi-mode receiving. The receiver uses two receiving channels RX1 and RX2 of an RX3701 radio frequency chip, wherein one receiving channel receives signals of a Global Positioning System (GPS) and a Beidou navigation system, and the other receiving channel receives special satellite signals with the frequency band of 1600.995MHz +/-5.115 MHz. The special satellite receiving channel can realize that the receiver still has the capability of single-satellite positioning under the condition that a Global Positioning System (GPS) and a Beidou navigation system are interfered. In addition, a two-stage filter circuit is designed at the receiving front end of each receiving channel of the receiver, so that the receiver is ensured to have strong anti-interference capability, and other equipment is prevented from interfering the receiver when receiving satellite signals. Each stage of filter can select filters of different frequency bands to be welded according to actual needs, so that signals of different frequency bands are received. A filter SF2186E is adopted, the central frequency is 1268.52MHz, the out-of-band rejection is-40 dB, and the bandwidth is 20.46 MHz; a filter SAFFB1G20AA0F0A is adopted, the center frequency is 1201.5MHz, the out-of-band rejection is-30 dB, and the bandwidth is 20.46 MHz; a filter SAFFB1G56AC0F0A with a center frequency of 1561.1MHz and an out-of-band rejection of-45 dB with a bandwidth of 20.46MHz was used. Meanwhile, a receiving front end of each receiving channel of the receiver is also provided with a three-level low-noise amplifier circuit so as to improve the receiving sensitivity of the receiver. Wherein, the gain of the first-stage low-noise amplifier circuit is 20dB, and the noise coefficient is 0.67; the gain of the second-stage low-noise amplifier circuit is 20dB, and the noise coefficient is 0.67; the gain of the third-stage low-noise amplifier circuit is 21.7dB, and the noise coefficient is 1.2. Therefore, the gain of 61.7dB can be realized by the three-stage low-noise discharging circuit. Besides, the P1dB of the rf receiving chip RX3701 itself is-30 dB, and a low noise amplifier with a gain of 40dB is integrated therein. Therefore, the receiving ensures that the sensitivity of receiving satellite signals is less than or equal to-150 dBm through the three-level low-noise amplifier gain and the gain of the RX3701 radio frequency chip,the sensitivity of reception is improved. The core processor of the baseband processing circuit of the receiver adopts a ZYNQ7045 processor of the sailingsi, a dual-core ARM Cortex-A9 processor is arranged in the core processor, and a 28nm technology-based processor is integrated

The 7-programmable logic FPGA processor supports single-precision and double-precision floating point operation, has the running speed of up to 1GHz, also has 900 special-purpose customized low-power consumption DSP Slice, 35 ten thousand logic units and 2020 DSP modules inside the FPGA processor, and can provide the processing performance exceeding 2662 GMAC. Signals can be tracked and captured through various software modules on the ZYNQ7045, and time service and positioning information can be generated. Wherein, the software module on the ARM0 processor in the ZYNQ7045 mainly comprises a signal processing module, a signal guiding module, a navigation processing module, an auxiliary information processing module and an interface module; the software module on the ARM1 processor mainly comprises a single star positioning module and an interface module; the software module on the FPGA processor mainly comprises a general quick capture module, a related channel module, a time management module and an interface module. The baseband processing circuit of the independent dual-channel navigation enhanced satellite receiver improves the baseband processing capacity of the receiver, reduces the positioning convergence time, and simultaneously ensures that the receiver can support multimode receiving demodulation and decoding and can directly output useful information such as positioning, time service and the like. Finally, the information solved by the receiver can be directly transmitted to the computer from the receiver through a network cable.

Drawings

FIG. 1 is a general block diagram of the present invention

FIG. 2 is a block diagram of a band-pass filter circuit according to the present invention

FIG. 3 is a block diagram of baseband processing circuitry

FIG. 4 is a functional block diagram of software modules and functional blocks of processors on ZYNQ7045

FIG. 5 is a block diagram of the receiver

Detailed Description

In fig. 1, an independent dual-channel navigation enhanced satellite receiver is composed of a navigation antenna 01, a navigation antenna 02, an L-type matching circuit, a two-stage band-pass filter circuit, a three-stage low-noise amplifier circuit, a radio frequency receiving chip RX3701, and a baseband processing circuit.

In the above embodiment, as shown in fig. 1, the navigation antenna 01 and the navigation antenna 02 may be separately connected to two input terminals of the receiver through coaxial lines, and the input terminals of the receiver adopt IPEX connectors, which are simple and easy to interconnect. The antenna signal is connected to the multistage band-pass filter and the multistage low-noise amplifier from the IPEX seat at the input end of the receiver to carry out amplification and filtering on the signal. Taking the receiving of the left RX1 channel of the receiver as an example, a signal of the navigation antenna 01 enters the input end of the first-stage band-pass filter circuit of the left RX1 channel from the receiver input end IPEX seat, the output end of the first-stage band-pass filter circuit is connected to the input end of the first-stage low-noise discharge circuit through an L-type matching circuit, the output end of the first-stage low-noise discharge circuit is connected to the input end of the second-stage band-pass filter circuit through an L-type matching circuit, the output end of the second-stage band-pass filter circuit is connected to the input end of the second-stage low-noise discharge circuit through an L-type matching circuit, the output end of the third-stage low-noise discharge circuit is connected to the RX1 receiving channel of the multi-mode multi-frequency radio frequency receiving chip RX3701 through a limiter diode, and then is transmitted to the ZYNQ7045 from the output channel OUT1 of RX3701, and finally is output to.

In the above specific embodiment, the signal of the navigation antenna 01 is amplified and filtered by the receiving front-end three-stage low-noise amplifier circuit and the two-stage band-pass filter circuit of the left RX1 receiving channel, and then output from the output end of the third-stage low-noise amplifier circuit of the RX1 receiving channel, and then connected to the input receiving channel RX1 of the RX3701 in the multi-mode multi-band rf receiving circuit after passing through the limiter diode, the signal processed by the multi-mode multi-band rf receiving circuit is output from the output channel OUT1 of the multi-mode multi-band rf receiving circuit in the form of 4-bit I/Q signal, the output channel OUT1 of the rf receiving chip is connected to DC3.3V BANK of the FPGA processor of ZYNQ7045 in the baseband processing circuit through a 50-ohm coplanar waveguide transmission line to perform information solution; the navigation antenna 02 signal is amplified and filtered by a receiving front-end three-stage low noise amplifier circuit and a two-stage band-pass filter circuit of a right RX2 receiving channel, the signal is output from an output end of a third-stage low noise amplifier circuit of an RX2 receiving channel, then the signal is connected to an input receiving channel RX2 of an RX3701 in the multi-mode multi-frequency radio frequency receiving circuit after passing through a limiting diode, the signal processed by the multi-mode multi-frequency radio frequency receiving circuit is output in a form of 4-bit I/Q signals from an output channel OUT2 of the multi-mode multi-frequency radio frequency receiving circuit, and an output channel OUT2 of a radio frequency receiving chip is also connected to DC3.3V BANK of an FPGA processor of ZYNQ7045 in a baseband processing circuit through a 50-ohm coplanar waveguide transmission line so as to. LEO signal demodulation is carried OUT on input 4-bit I/Q signals of OUT1 and OUT2 channels through various software modules on an ARM0, an ARM1 and an FPGA processor on a ZYNQ7045 in a baseband processing circuit. Finally, ZYNQ7045 in the baseband processing circuit transmits the resolved information to PHY chip 88E1111 through SGMII interface of SerDes Bank on FPGA processor, 88E1111 outputs the information transmitted by FPGA to RJ45 connector through MDIO interface, thereby directly connecting to computer through network cable.

Claims

1. An independent two-channel navigation enhanced satellite receiver comprises a navigation antenna 01, a navigation antenna 02, an L-shaped matching circuit, a two-stage band-pass filter circuit, a three-stage low-noise amplifier circuit, an RX3701 circuit and a baseband processing circuit; the receiver can support independent dual-channel multi-mode reception and has high sensitivity and strong anti-interference capability; the receiver receives a special satellite positioning signal through one of the receiving channels under the condition that a Global Positioning System (GPS) or a Beidou navigation system is interfered, so that a single satellite positioning function is realized; the receiver also has strong baseband processing capability; electromagnetic wave signals received by the navigation antenna 01 and the navigation antenna 02 respectively pass through the three-level low-noise amplifier circuit and the two-level band-pass filter circuit and then enter the multi-mode multi-frequency radio frequency receiving circuit, and after the signals are processed by the radio frequency receiving circuit, 4-bit I/Q signals obtained by processing each channel are respectively output to the baseband processing circuit through two output channels of OUT1 and OUT2 of RX 3701. LEO signal demodulation is carried OUT on the input 4-bit I/Q signals of the OUT1 channel and the OUT2 channel through ARM0, ARM1 of ZYNQ7045 in a baseband processing circuit and a software module on an FPGA processor. And finally, the receiver sends the resolved information to a computer for processing through a gigabit Ethernet.

2. The standalone dual channel GNSS receiver of claim 1, wherein the standalone dual channel GNSS receiver is provided with an standalone dual channel receiver circuit with RX3701 RF chip as core; the receiver utilizes two receiving channels RX1 and RX2 of RX3701 to carry out signal reception; the RX1 receiving channel receives satellite signals of a global positioning system GPS or a Beidou navigation system, and the RX2 channel can receive special satellite signals with the frequency range of 1600.995MHz +/-5.115 MHz; the special satellite receiving channel RX2 of the receiver can realize that the receiver still has the capability of single-satellite positioning under the condition that a Global Positioning System (GPS) or a Beidou navigation system is interfered; two-stage filter circuits are designed at the receiving front ends of the RX1 and RX2 receiving channels, so that the receiver is ensured to have strong anti-interference capability, and other equipment is prevented from interfering the receiver when the receiver receives satellite signals; each stage of filter can select filters of different frequency bands for welding according to actual needs, so that signals of different frequency bands are received; a filter SF2186E is adopted, the central frequency is 1268.52MHz, the out-of-band rejection is-40 dB, and the bandwidth is 20.46 MHz; a filter SAFFB1G20AA0F0A is adopted, the center frequency is 1201.5MHz, the out-of-band rejection is-30 dB, and the bandwidth is 20.46 MHz; a filter SAFFB1G56AC0F0A is adopted, the center frequency is 1561.1MHz, the out-of-band rejection is-45 dB, and the bandwidth is 20.46 MHz; meanwhile, three-stage low-noise amplifier circuits are designed at the receiving front ends of RX1 and RX2 receiving channels of the receiver, the gain of the first-stage low-noise amplifier circuit is 20dB, and the noise coefficient is 0.67; the gain of the second-stage low-noise amplifier circuit is 20dB, and the noise coefficient is 0.67; the gain of the third-stage low-noise amplifier circuit is 21.7dB, and the noise coefficient is 1.2; the gain realized by the three-level low-noise discharging circuit reaches 61.7dB, the P1dB of the radio frequency receiving chip RX3701 is-30 dB, and in addition, a low-noise amplifier with the gain reaching 40dB is integrated in the RX3701 chip; therefore, the three-level low-noise amplification gain and the gain of the RX3701 radio frequency chip ensure that the sensitivity of the receiver for receiving satellite signals is less than or equal to-150 dBm, and the receiving sensitivity is improved.

3. The standalone dual channel navigation augmentation satellite receiver of claim 1, wherein: ZYNQ7045 is selected as a processor in a baseband processing circuit, a dual-core ARM processor is arranged in the processor, and a programmable logic FPGA processor is integrated; ZYNQ7045 of the receiver is used for mounting a 1GByte DDR3 cache for data storage and working main frequency of 1333MHz, and in addition, 32Mbyte QSPI Flash is mounted for guiding starting; the ARM end is provided with a single-ended 33.33MHz active crystal oscillator, the FPGA end is provided with a single-ended 50.00MHz active crystal oscillator and a differential 125.00MHz active crystal oscillator, and the FPGA end is used for time sequence design of a software module; meanwhile, 4-bit I/Q data which are respectively and independently output by two output channels OUT1 and OUT2 of an RX3701 radio frequency chip are received through an FPGA end DC3.3V BANK, and signal processing, signal guiding and auxiliary information processing are carried OUT through an ARM0 processor of ZYNQ 7045; the ARM1 processor performs single-satellite positioning calculation; the FPGA processor performs fast capture, and performs demodulation and de-spread on related channels to acquire an accumulated amount; the receiver realizes different functions by mutually matching software modules on the ZYNQ7045, thereby reducing the positioning convergence time, ensuring that the receiver supports multimode receiving demodulation and decoding, and directly outputting positioning.

4. The standalone dual channel navigation augmentation satellite receiver of claim 1, wherein: the receiver has small overall size, simple input interface and direct output interface access to the computer; the size of the whole receiver is controlled to be 100mm 70mm 30mm, the double-channel input of the receiver adopts an IPEX connector and is connected to an antenna through a coaxial line, ZYNQ7045 in a baseband processing circuit of the receiver transmits finally calculated information to a PHY chip 88E1111 through an SGMII interface of a SerDes Bank on an FPGA processor of the receiver, and the signal transmitted by the FPGA is converted by 88E1111 and then is output to an RJ45 connector through an MDIO interface of the PHY chip, so that the signal is directly connected to a computer through a network cable for processing.