CN112994835A - Block interleaving processing method and system - Google Patents
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Abstract
本发明提供一种块交织处理方法及系统，包括以下步骤：将M×N的数据块在块内按照预设交织方式进行交织，所述预设交织方式为跨行交织、跨列交织、行循环移位交织、列循环移位交织、跨行交织和行循环移位交织组合、跨列交织和行循环移位交织组合、跨行交织和列循环移位交织组合、跨列交织和列循环移位交织组合中的一种；按照预设读出方式读出交织后的数据块；所述预设读出方式为跨行读出、跨列读出、位置索引逐行读出和位置索引逐列读出中的一种。本发明的块交织处理方法及系统能够在不增加通信开销的同时，有效提高块交织性能。
The present invention provides a block interleaving processing method and system, comprising the following steps: interleaving M×N data blocks in a block according to a preset interleaving manner, where the preset interleaving manner is cross-row interleaving, cross-column interleaving, and row looping Shift interleaving, column cyclic shift interleaving, cross row interleaving and row cyclic shift interleaving combined, cross column interleaving and row cyclic shift interleaving combination, cross row interleaving and column cyclic shift interleaving, cross column interleaving and column cyclic shift interleaving One of the combinations; read out the interleaved data block according to a preset readout mode; the preset readout mode is cross-row readout, cross-column readout, position index row-by-row readout and position index readout column-by-column one of the. The block interleaving processing method and system of the present invention can effectively improve the block interleaving performance without increasing the communication overhead.
Description
Technical Field
The present invention relates to the field of wireless communications technologies, and in particular, to a block interleaving method and system.
Background
In a wireless communication system, especially a wireless broadcasting system, in order to improve the fault tolerance of the system, it is necessary to achieve error-free transmission at the receiving end as much as possible. In general, time interleaving techniques are employed to combat the problem of channel interference. Because the probability of errors occurring in adjacent information units at the same time is generally high, block errors are easily formed and are not easy to correct. Therefore, time interleaving, which is a task of scrambling adjacent information units as much as possible for transmission, becomes an important link for solving the stability and data accuracy of a communication system.
The block interleaving changes the distribution of data under a certain rule, increases the distance between adjacent original data and reduces the probability of continuous errors. The block interleaving inputs a data block of M × N, where the number of rows M represents the number of cells of a code block and the number of columns N represents the number of code blocks. Minimum value S of sum of distances of data belonging to the same code block before and after interleavingminAs a performance indicator of block interleaving.
In the prior art, common block interleaving schemes include the following:
(1) random interleaving
Since random interleaving uses a specific random scrambling pattern for interleaving, it is limited by the size of the interleaving block and the storage of a specific ordering pattern.
(2) Row in row out
The performance of the column-in-row block interleaving scheme is limited by the number of columns.
(3) Diagonal interleaving
The diagonal interleaving adopts the mode of reading in by columns and interleaving by the mode of reading out the diagonal, and the minimum span of scrambling is limited by the number of columns.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a block interleaving method and system, which can effectively improve the block interleaving performance without increasing the communication overhead.
To achieve the above and other related objects, the present invention provides a block interleaving method, comprising: interleaving the M multiplied by N data blocks in a block according to a preset interleaving mode, wherein the preset interleaving mode is one of cross-row interleaving, cross-column interleaving, row cyclic shift interleaving, column cyclic shift interleaving, a combination of cross-row interleaving and row cyclic shift interleaving, a combination of cross-column interleaving and row cyclic shift interleaving, a combination of cross-row interleaving and column cyclic shift interleaving, and a combination of cross-column interleaving and column cyclic shift interleaving; reading out the interleaved data block according to a preset reading mode; the preset reading mode is one of line-crossing reading, column-crossing reading, position index line-by-line reading and position index line-by-column reading.
In one embodiment of the present invention, when interleaving across rows, the row sequence number after arrangement is
Where d is the interleaving interval, a1＝1，0＜d≤M，0＜Q≤M-1。
In an embodiment of the present invention, when interleaving across rows, the sequence number of the arranged rows is
Where d is the interleaving interval, a1＝1，0＜d≤N，0＜Q≤N-1。
In one embodiment of the present invention, during the cyclic shift of the rows, the shift number per row is Ci＝bimod N, where bi＝bi-1+ p, p is the interleaving interval, b1＝0，1≤p＜M，0≤Ci≤N。
In one embodiment of the present invention, during the circular shifting of the rows, the shift number of each row is Ci＝bimod M, where bi＝bi-1+ p, p is the interleaving interval, b1＝0，1≤p＜M，0≤Ci≤M。
In an embodiment of the present invention, when reading across rows, the row sequence number read out is
Where d is the read interval, a1＝1，0＜d≤M，0＜Q≤M-1。
In one embodiment of the present invention, when reading across columns, the sequence number of the column read is
Where d is the read interval, a1＝1，0＜d≤N，0＜Q≤N-1。
In an embodiment of the present invention, when the position index is read out row by row, the read-out position is Ri＝[(A*i)mod M，(B*i)mod N]And according to the order vector R ═ R1，R2，...，RM]And sequentially reading, wherein A is more than 0 and less than or equal to M, B is more than 0 and less than or equal to N, i represents a row number, and i is more than or equal to 1 and less than or equal to M.
In one embodiment of the present invention, when the position index is read out row by row, the read-out position is Rj＝[(A*j)mod M，(B*j)mod N]And according to the order vector R ═ R1，R2，...，RN]And sequentially reading, wherein A is more than 0 and less than or equal to M, B is more than 0 and less than or equal to N, and j represents the column number j is more than or equal to 1 and less than or equal to N.
Correspondingly, the invention provides a block interleaving processing system, which comprises an interleaving module and a reading module;
the interleaving module is used for interleaving the MXN data blocks in a block according to a preset interleaving mode, wherein the preset interleaving mode is one of cross-row interleaving, cross-column interleaving, row cyclic shift interleaving, column cyclic shift interleaving, a combination of cross-row interleaving and row cyclic shift interleaving, a combination of cross-column interleaving and row cyclic shift interleaving, a combination of cross-row interleaving and column cyclic shift interleaving, and a combination of cross-column interleaving and column cyclic shift interleaving;
the reading module is used for reading the interleaved data block according to a preset reading mode; the preset reading mode is one of line-crossing reading, column-crossing reading, position index line-by-line reading and position index line-by-column reading.
As described above, the block interleaving method and system of the present invention have the following advantages:
(1) the communication overhead is not increased;
(2) the minimum distance limit value between the data after interleaving is increased, and the block interleaving performance is improved;
(3) the interleaving in code blocks and the interleaving among code blocks can be realized, and the performance of the communication system for resisting channel fading is further improved.
Drawings
FIG. 1 is a flow chart of a block interleaving method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a cross-row interleaving and a cross-row reading in the block interleaving method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a block interleaving method according to another embodiment of the present invention in which interleaving is performed by cyclically shifting rows and position indexes are read out row by row;
fig. 4 is a schematic structural diagram of a block interleaving processing system according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The block interleaving processing method and the system can effectively improve the block interleaving performance through a certain interleaving and reading method without increasing communication overhead.
As shown in fig. 1, in an embodiment, the block interleaving processing method of the present invention includes the following steps:
step S1, interleaving the mxn data blocks in a block according to a preset interleaving manner, where the preset interleaving manner is one of cross-row interleaving, cross-column interleaving, row cyclic shift interleaving, column cyclic shift interleaving, a combination of cross-row interleaving and row cyclic shift interleaving, a combination of cross-column interleaving and row cyclic shift interleaving, a combination of cross-row interleaving and column cyclic shift interleaving, and a combination of cross-column interleaving and column cyclic shift interleaving.
Specifically, the data block is configured to contain M × N data, where the row number M represents the number of cells of a code block, the column number N represents the number of code blocks, M ≧ 1, and N ≧ 1.
When interleaving the data blocks, any one of the following methods may be adopted:
(1) cross-row interleaving
Specifically, when interleaving across rows, the row sequence numbers of the data blocks are reordered, and the data blocks are adjusted based on the ordered row sequence numbers, thereby completing the interleaving of the data blocks.
In one embodiment of the present invention, when interleaving across rows, the row sequence number after arrangement is
Where d is the interleaving interval, a1＝1，0＜d≤M，0＜Q≤M-1。
When a is to be notedi-1When > M-d, the order is convoluted from line Q.
(2) Cross-column interleaving
Specifically, when the column-crossing interleaving is performed, the column sequence numbers of the data blocks are reordered, and the data blocks are adjusted based on the ordered column sequence numbers, so that the interleaving of the data blocks is completed.
In an embodiment of the present invention, when interleaving across rows, the sequence number of the arranged rows is
Where d is the interleaving interval, a1＝1，0＜d≤N，0＜Q≤N-1。
When a is to be notedi-1When > M-d, the order is convoluted from the Q-th column.
(3) Row cyclic shift interleaving
Specifically, when the line cyclic shift interleaving is performed, a certain line cyclic shift is performed for each line, thereby completing the interleaving of the data block.
In one embodiment of the present invention, during the cyclic shift of the rows, the shift number per row is Ci＝bimod N, where bi＝bi-1+ p, p is the interleaving interval, b1＝0，1≤p＜M，0≤Ci≤N。
(4) Column cyclic shift interleaving
Specifically, during the column cyclic shift interleaving, a certain column cyclic shift is performed for each column, thereby completing the interleaving of the data block.
In one embodiment of the present invention, during the circular shifting of the rows, the shift number of each row is Ci＝bimod M, where bi＝bi-1+ p, p is the interleaving interval, b1＝0，1≤p＜M，0≤Ci≤M。
(5) Cross-row interleaving and row cyclic shift interleaving combination
Specifically, the interleaving is performed by a combination of row-crossing interleaving and row cyclic shift interleaving, that is, the row-crossing interleaving is performed first, and then the row cyclic shift interleaving is performed.
(6) Cross-column interleaving and row cyclic shift interleaving combination
Specifically, the interleaving is performed by combining the column-crossing interleaving and the row cyclic shift interleaving, that is, the column-crossing interleaving is performed first, and then the row cyclic shift interleaving is performed.
(7) Cross-row interleaving and column cyclic shift interleaving combination
Specifically, a mode of combining row-crossing interleaving and column cyclic shift interleaving is adopted for interleaving, that is, row-crossing interleaving is performed first, and then column cyclic shift interleaving is performed.
(8) Cross-column interleaving and column cyclic shift interleaving combination
Specifically, the interleaving is performed by combining the cross-column interleaving and the column cyclic shift interleaving, that is, the cross-column interleaving is performed first, and then the column cyclic shift interleaving is performed.
Step S2, reading out the interleaved data block according to a preset reading mode; the preset reading mode is one of line-crossing reading, column-crossing reading, position index line-by-line reading and position index line-by-column reading.
Specifically, when reading out a data block, the following four ways are included:
(1) cross-row readout
Specifically, when the line-crossing reading is performed, the line sequence numbers of the interleaved data blocks are reordered, and the data is sequentially read based on the ordered line sequence numbers.
In an embodiment of the present invention, when reading across rows, the row sequence number read out is
Where d is the read interval, a1＝1，0＜d≤M，0＜Q≤M-1。
The read interval and the interleave interval may be equal or different, and may be set according to user requirements. When a isi-1When the read signal is larger than M-d, the read signal is read in a convolution manner from the Q-th row.
(2) Cross-column readout
Specifically, when the column crossing reading is performed, the column sequence numbers of the interleaved data blocks are reordered, and the data is sequentially read based on the ordered column sequence numbers.
In one embodiment of the present invention, when reading across columns, the sequence number of the column read is
Where d is the read interval, a1＝1，0＜d≤N，0＜Q≤N-1。
Need to make sure thatThe read interval and the interleave interval may be equal or different, and may be set according to user requirements. When a isi-1When the read signal is larger than M-d, the read signal is read in a convolution manner from the Q-th column.
(3) Position index line-by-line readout
Specifically, when the position index is read out row by row, the position index is sequentially read out according to the sequence of the row sequence numbers in a mode of simultaneously spacing rows and columns.
In an embodiment of the present invention, when the position index is read out row by row, the read-out position is Ri＝[(A*i)mod M，(B*i)mod N]And according to the order vector R ═ R1，R2，...，RM]And sequentially reading, wherein A is more than 0 and less than or equal to M, B is more than 0 and less than or equal to N, i represents a row number, and i is more than or equal to 1 and less than or equal to M. The values of a and B may be non-integer or integer.
(4) Position index column-by-column readout
Specifically, when the position index is read column by column, the position index is sequentially read according to the sequence of the column sequence numbers in a manner of simultaneously spacing rows and columns.
In one embodiment of the present invention, when the position index is read out row by row, the read-out position is Rj＝[(A*j)mod M，(B*j)mod N]And according to the order vector R ═ R1，R2，...，RN]And sequentially reading, wherein A is more than 0 and less than or equal to M, B is more than 0 and less than or equal to N, and j represents the column number j is more than or equal to 1 and less than or equal to N. The values of a and B may be non-integer or integer.
The block interleaving processing method of the present invention is further explained by the following specific embodiments.
Example one
In this embodiment, a cross-row interleaving and a cross-row readout mode are adopted to perform block interleaving processing.
As shown in fig. 2, the 10 × 6 data blocks are subjected to block interleaving processing. Wherein, the block is sorted by the interleaving interval d-2, and Q-a is takeni+1, and then, row readout is performed at a readout interval d of 3. When the block is processed with cross-row interleaving sorting, the row sequence number is [1, 3, 5, 7, 9, 2, 4, 6, 8, 10 after sorting]Read according to [1, 4, 7, 10, 2, 5, 8, 3, 6, 9 ]]The rows are read out sequentially.
Example two
In this embodiment, the block interleaving process is performed by using a line cyclic shift interleaving and a line-by-line reading of the position index.
As shown in fig. 3, the 10 × 6 data blocks are subjected to block interleaving processing. The block is cyclically shifted to the left line at an interleaving interval p of 2, and then the position index is read out line by line at a position a of 1 and at a position B of 1. When cyclic shift is performed in a block, b is [0, 2, 4, 6, 8, 10, 12,14,16, 18], the cyclic shift value C is [0, 2, 4, 0, 2, 4, 0, 2, 4, 0], the order of reading is (1, 1), (2, 2), (3, 3), (4, 4), (5, 5), (6, 6), (7, 1), (8, 2), (9, 3), (10, 4), and the sequence of reading is (1, 2), (2, 3), …, (10, 5) starting from the first row again.
As shown in fig. 4, in an embodiment, the block interleaving processing system of the present invention includes an interleaving module 41 and a readout module 42.
The interleaving module 41 is configured to interleave the mxn data blocks in a block according to a preset interleaving manner, where the preset interleaving manner is one of cross-row interleaving, cross-column interleaving, row cyclic shift interleaving, column cyclic shift interleaving, a combination of cross-row interleaving and row cyclic shift interleaving, a combination of cross-column interleaving and row cyclic shift interleaving, a combination of cross-row interleaving and column cyclic shift interleaving, and a combination of cross-column interleaving and column cyclic shift interleaving.
The readout module 42 is connected to the interleaving module 41 for; reading out the interleaved data block according to a preset reading mode; the preset reading mode is one of line-crossing reading, column-crossing reading, position index line-by-line reading and position index line-by-column reading.
It should be noted that the division of the modules of the above apparatus is only a logical division, and the actual implementation may be wholly or partially integrated into one physical entity, or may be physically separated. And the modules can be realized in a form that all software is called by the processing element, or in a form that all the modules are realized in a form that all the modules are called by the processing element, or in a form that part of the modules are called by the hardware. For example: the x module can be a separately established processing element, and can also be integrated in a certain chip of the device. In addition, the x-module may be stored in the memory of the apparatus in the form of program codes, and may be called by a certain processing element of the apparatus to execute the functions of the x-module. Other modules are implemented similarly. All or part of the modules can be integrated together or can be independently realized. The processing element described herein may be an integrated circuit having signal processing capabilities. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in the form of software. These above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), one or more microprocessors (DSPs), one or more Field Programmable Gate Arrays (FPGAs), and the like. When a module is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. These modules may be integrated together and implemented in the form of a System-on-a-chip (SOC).
In summary, the block interleaving processing method and system of the present invention do not increase communication overhead; the minimum distance limit value between the data after interleaving is increased, and the block interleaving performance is improved; the interleaving in code blocks and the interleaving among code blocks can be realized, and the performance of the communication system for resisting channel fading is further improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1341295A (en) * | 1999-01-11 | 2002-03-20 | 诺泰网络有限公司 | Block interleaving for turbo coding |
| KR20030065662A (en) * | 2002-01-30 | 2003-08-09 | 삼성전자주식회사 | the interleaver and the method thereof in HDR transmitter |
| CN101227195A (en) * | 2007-01-17 | 2008-07-23 | 华为技术有限公司 | Interweave apparatus, de-interweave apparatus and uses thereof |
| US20090207946A1 (en) * | 2008-02-14 | 2009-08-20 | Via Technologies, Inc. | Grouping bits interleaving apparatus and method thereof |
| CN101944972A (en) * | 2010-09-20 | 2011-01-12 | 华为技术有限公司 | Coding and decoding method, device and communication system |
| CN102377516A (en) * | 2011-06-22 | 2012-03-14 | 钜泉光电科技(上海)股份有限公司 | Data processing method and device |
| CN102420674A (en) * | 2011-11-01 | 2012-04-18 | 上海华为技术有限公司 | Sub-block interleaving method and parallel sub-block interleaver |
| EP3017575A1 (en) * | 2013-07-05 | 2016-05-11 | Samsung Electronics Co., Ltd. | Transmitter apparatus and signal processing method thereof |
| US20170310423A1 (en) * | 2016-04-26 | 2017-10-26 | Electronics And Telecommunications Research Instit | Apparatus for time interleaving and method using the same |
-
2019
- 2019-12-02 CN CN201911214313.6A patent/CN112994835A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1341295A (en) * | 1999-01-11 | 2002-03-20 | 诺泰网络有限公司 | Block interleaving for turbo coding |
| KR20030065662A (en) * | 2002-01-30 | 2003-08-09 | 삼성전자주식회사 | the interleaver and the method thereof in HDR transmitter |
| CN101227195A (en) * | 2007-01-17 | 2008-07-23 | 华为技术有限公司 | Interweave apparatus, de-interweave apparatus and uses thereof |
| US20090207946A1 (en) * | 2008-02-14 | 2009-08-20 | Via Technologies, Inc. | Grouping bits interleaving apparatus and method thereof |
| CN101944972A (en) * | 2010-09-20 | 2011-01-12 | 华为技术有限公司 | Coding and decoding method, device and communication system |
| CN102377516A (en) * | 2011-06-22 | 2012-03-14 | 钜泉光电科技(上海)股份有限公司 | Data processing method and device |
| CN102420674A (en) * | 2011-11-01 | 2012-04-18 | 上海华为技术有限公司 | Sub-block interleaving method and parallel sub-block interleaver |
| EP3017575A1 (en) * | 2013-07-05 | 2016-05-11 | Samsung Electronics Co., Ltd. | Transmitter apparatus and signal processing method thereof |
| US20170310423A1 (en) * | 2016-04-26 | 2017-10-26 | Electronics And Telecommunications Research Instit | Apparatus for time interleaving and method using the same |
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