CN112993135B - Manufacturing method of display panel, display panel and display device - Google Patents

Abstract

The present invention relates to a manufacturing method of a display panel, a display panel and a display device. The method for manufacturing a display panel adopted in the present application provides a first substrate and a second substrate, the first substrate includes a growth substrate, an epitaxial structure and a first metal layer stacked in sequence, and the second substrate includes a circuit substrate and a circuit substrate stacked on the circuit substrate the second metal layer; the first metal layer is activated, and the second metal layer is activated; the first metal layer after the activation treatment and the second metal layer after the activation treatment are bonded, so that the growth substrate, The epitaxial structure, the first metal layer, the second metal layer and the circuit substrate are stacked in sequence; the growth substrate is peeled off. The bonding process of the present application is performed at room temperature, which avoids the delamination problem caused by thermal mismatch due to the large difference in thermal expansion coefficients between the circuit substrate and the growth substrate in the current high-temperature bonding process.

Description

Manufacturing method of display panel, display panel and display device

technical field

The present invention relates to the field of display technology, and in particular, to a manufacturing method of a display panel, a display panel, and a display device including the display panel.

Background technique

In recent years, with the continuous development of display technology, the transfer of epitaxial structures to circuit substrates through transfer technology has always been a research hotspot in the field of display technology.

At present, the epitaxial structure on the growth substrate is generally transferred to the circuit substrate through the wafer bonding technology. However, the traditional wafer bonding technology often selects metal to bond at 400 °C, and the thermal expansion coefficient of the circuit substrate and the growth substrate is different. Obviously, the delamination problem caused by thermal mismatch often occurs in the high-temperature bonding process, which affects the display quality.

Therefore, how to realize the low-temperature transfer of the epitaxial structure on the growth substrate to the circuit substrate to avoid delamination caused by thermal mismatch in high-temperature bonding is an urgent problem to be solved.

SUMMARY OF THE INVENTION

In view of the above-mentioned deficiencies of the prior art, the purpose of the present application is to provide a method for fabricating a display panel, a display panel, and a display device including the display panel, aiming to solve the problem that when the epitaxial structure on the growth substrate is transferred to the circuit substrate at high temperature, Due to the obvious difference in thermal expansion coefficient between the circuit substrate and the growth substrate, the delamination problem caused by thermal mismatch occurs in the high-temperature bonding process.

In a first aspect, the present application provides a method for fabricating a display panel, comprising: providing a first substrate and a second substrate, wherein the first substrate includes a growth substrate, an epitaxial structure, and a first metal layered in sequence. layer, the second substrate includes a circuit substrate and a second metal layer stacked on the circuit substrate; activation treatment is performed on the first metal layer, and activation treatment is performed on the second metal layer; bonding activation The processed first metal layer and the activated second metal layer, so that the growth substrate, the epitaxial structure, the first metal layer, the second metal layer and the circuit The substrates are stacked in sequence; the growth substrates are peeled off.

In the present application, by arranging the first metal layer and the second metal layer, and performing surface activation treatment on the first metal layer and the second metal layer, the activated first metal layer and the second metal layer are in contact with each other at room temperature. The atomic diffusion phenomenon makes the first metal layer and the second metal layer adhere to each other to realize bonding, so as to transfer the epitaxial structure to the circuit substrate. The bonding process of the present application is carried out at room temperature, which avoids the delamination problem caused by thermal mismatch due to the large difference in thermal expansion coefficient between the circuit substrate and the growth substrate in the current high-temperature bonding process, which is beneficial to the display performance of the display panel. improvement.

Optionally, the first metal layer includes a first surface facing away from the growth substrate, and the second metal layer includes a second surface facing away from the circuit substrate; and performing activation treatment on the first metal layer Including activating the first surface; activating the second metal layer including activating the second surface; bonding the activated first metal layer and the activated The second metal layer includes bonding the first surface and the second surface. The method of surface activation treatment may include ion beam activation. During the surface activation treatment, the first surface and the second surface are first subjected to activation, the metal atoms of the first surface and the second surface are activated, and the first surface and the second surface are activated. When in contact with each other, the activated metal atoms diffuse to achieve bonding.

Optionally, the first metal layer includes a first metal sublayer, a second metal sublayer, and a third metal sublayer that are stacked in sequence, and the first metal sublayer is stacked on the epitaxial structure; the The second metal layer includes a fourth metal sublayer, a fifth metal sublayer and a sixth metal sublayer that are stacked in sequence, and the sixth metal sublayer is stacked on the circuit substrate; During the activation process with the second metal layer, the third metal sublayer and the fourth metal sublayer are completely etched away, and the second metal sublayer and the fifth metal sublayer are bonded connect. In the process of performing surface activation treatment on the first metal layer and the second metal layer, the third metal sublayer and the fourth metal sublayer on the surface layer can be completely etched away. For example, when the degree of etching is controlled by the surface activation treatment time, the partial etching is to ensure that the third metal sub-layer remaining in the valley is not higher than the peak of the wave to ensure that the second metal sub-layer and the fifth metal sub-layer The layers can be in contact with each other, so the partial etching controls the activation process conditions (such as time) more strictly, which increases the difficulty of operation, while the full etching can choose a longer activation etching time, without considering the third metal sublayer and the third metal sublayer. The residual state of the four metal sub-layers has greater process flexibility and is convenient for operation.

Optionally, the first metal layer includes a first metal sublayer, a second metal sublayer, and a third metal sublayer that are stacked in sequence, and the first metal sublayer is stacked on the epitaxial structure; the The second metal layer includes a fourth metal sublayer, a fifth metal sublayer and a sixth metal sublayer that are stacked in sequence, and the sixth metal sublayer is stacked on the circuit substrate; During the activation process of the second metal layer, the third metal sub-layer is partially etched away to expose the second metal sub-layer, and the fourth metal sub-layer is partially etched away to expose all the metal sub-layers. the fifth metal sublayer, the remaining third metal sublayer is bonded to the remaining fourth metal sublayer, and the exposed second metal sublayer is bonded to the exposed fifth metal sublayer combined connection.

During the surface activation process of the first metal layer and the second metal layer, the third metal sublayer and the fourth metal sublayer on the surface layer will be etched away. The metal sublayer and the fourth metal sublayer are not completely etched (that is, a part of the third metal sublayer remains on the first metal layer, and a part of the fourth metal sublayer remains on the second metal layer). and the control of the surface roughness of the fifth metal sublayer, so that the second metal sublayer and the fifth metal sublayer have greater roughness, so that the surfaces of the second metal sublayer and the fifth metal sublayer have peaks and valleys, During the activation process, part of the third metal sublayer and the fourth metal sublayer on the surfaces of the second metal sublayer and the fifth metal sublayer can be retained. During the bonding process, the second metal sublayer and the fifth metal sublayer The partially remaining third metal sublayer and the fourth metal sublayer on the surface are bonded to each other and the second metal sublayer and the fifth metal sublayer are bonded to each other. Since the second metal sublayer and the fifth metal sublayer and the residual The double bonding of the third metal sublayer and the remaining fourth metal sublayer increases the bonding strength.

Specifically, the first metal layer and the second metal layer are three-layer metal structures with the same structure, the first metal sublayer and the third metal sublayer of the first metal layer and the fourth metal sublayer of the second metal layer and The sixth metal sublayer can be titanium. Since titanium has a certain bonding effect, the bonding effect is not ideal when the second metal sublayer is directly deposited on the epitaxial structure or the fifth metal sublayer is directly deposited on the circuit substrate. A layer of titanium metal is arranged on the epitaxial structure (that is, the first metal sublayer and the sixth metal sublayer are titanium metal), which can play the role of bonding the second metal sublayer and the epitaxial structure and the fifth metal sublayer and the circuit substrate , to increase the bond strength between layers. The third metal sublayer and the fourth metal sublayer are titanium metal. On the one hand, titanium metal will protect the second metal sublayer and the fifth metal sublayer, avoiding the second metal sublayer and the fifth metal sublayer. When the surface is directly exposed to the environment, an organic film layer or other impurities are formed or adhered to the surface. The organic film layer will cause the activation of the surface of the second metal sublayer and the fifth metal sublayer to be difficult to handle. A part of the titanium metal of the third metal sublayer and the fourth metal sublayer is reserved, so that the double bonding effect of the second metal sublayer and the fifth metal sublayer and the remaining third metal sublayer and the fourth metal sublayer is increased. bond strength.

The second metal sublayer of the first metal layer and the fifth metal sublayer of the second metal layer may be one of platinum, gold, copper, and aluminum. Metals such as platinum, gold, copper, and aluminum are easy to activate, and the activated platinum atoms, gold atoms, copper atoms or aluminum atoms are prone to atomic diffusion to achieve bonding.

Optionally, specifically, during the partial etching process, the surface of the second metal sub-layer facing the third metal sub-layer includes a first wave crest and a first wave trough, and the fifth metal sub-layer faces the third metal sub-layer. The surface of the fourth metal sub-layer includes a second wave peak and a second wave trough, and in the process of activating the first metal layer and the second metal layer, the third metal sub-layer is partially etched away, The fourth metal sublayer is partially etched to expose the first crest and part of the first trough of the second metal sub-layer and leave part of the third metal sub-layer in the rest of the first trough removed to expose the second crest and part of the second trough of the fifth metal sub-layer and part of the fourth metal sub-layer remains in the remaining second trough, the exposed first crest and The exposed part of the first wave trough is bonded to the exposed second wave crest and the exposed part of the second wave trough, and the third metal sublayer remaining in the first wave trough is connected to the second wave trough. The fourth metal sublayer remaining in the valley is bonded and connected. The double bonding of the exposed second metal sublayer and the exposed fifth metal sublayer and the remaining third and fourth metal sublayers increases the bond strength.

Optionally, the step of fabricating the display panel further includes: etching the display panel after peeling off the growth substrate, depositing a passivation layer on the etched outer surface; depositing indium tin oxide on the passivation layer (Indium TinOxide, ITO) layer; perform high temperature annealing treatment on the ITO layer. The passivation layer can be a silicon dioxide passivation layer, in the process of annealing ITO at high temperature (at this time, the growth substrate has been peeled off, and there is no delamination problem caused by the large difference in thermal expansion coefficient between the growth substrate and the circuit substrate at high temperature) , the bonding layer is also in a high temperature environment, and the first metal layer and the second metal layer after low temperature bonding can be further bonded and strengthened to enhance the bonding strength.

In a second aspect, based on the same inventive concept, the present application further provides a display panel, characterized in that it includes a plurality of epitaxial structures and a second substrate, and the epitaxial structure array is arranged on the second substrate; Each of the epitaxial structures includes an epitaxial structure and a first metal layer stacked in sequence, the second substrate includes a circuit substrate and a second metal layer stacked on the circuit substrate, the first metal layer and the second metal layer are stacked on the circuit substrate. The second metal layer is bonded and connected, wherein the first metal layer is activated and the second metal layer is activated.

In the present application, the first metal layer and the second metal layer are bonded at room temperature. Specifically, atomic diffusion occurs when the first metal layer and the second metal layer are in contact with each other at room temperature, so that the first metal layer and the second metal layer are in contact with each other at room temperature. The two metal layers are bonded to each other to realize bonding, so as to transfer the epitaxial structure to the circuit substrate. The bonding process of the present application is carried out at room temperature, which avoids the delamination problem caused by thermal mismatch due to the large difference in thermal expansion coefficient between the circuit substrate and the growth substrate in the current high-temperature bonding process, which is beneficial to the display performance of the display panel. improvement.

Optionally, the circuit substrate includes a plurality of grooves, and the bottom of each groove is provided with a first electrode; the second metal layer is laminated on the plurality of the circuit substrates and fills the groove and the groove. The first electrode is in contact; the first metal layer and the second metal layer are bonded to form a conductor, and the epitaxial structure is electrically connected to the first electrode through the conductor. The first electrode is a positive electrode, the first electrode can be an aluminum electrode, the first metal layer and the second metal layer are conductors, and the epitaxial structure is electrically connected to the first electrode through the conductors to realize the conduction of the circuit and avoid the need to set other The operation of the conductive structure to electrically connect the epitaxial structure and the first electrode simplifies the process and reduces the cost.

Optionally, a side of the epitaxial structure away from the first metal layer is provided with a second electrode, and the epitaxial structure is electrically connected to the second electrode. The two sides of the epitaxial structure are respectively electrically connected with the first electrode and the second electrode to realize the conduction of the circuit.

Optionally, the epitaxial structure includes a P-type epitaxial layer, a multiple quantum well layer, and an N-type epitaxial layer that are stacked in sequence, the P-type epitaxial layer is located on the first metal layer, and the P-type epitaxial layer passes through the layer. The conductor is electrically connected to the first electrode, the N-type epitaxial layer is electrically connected to the second electrode, and the holes of the P-type epitaxial layer and the electrons of the N-type epitaxial layer are in the multiple layers. Quantum well layer recombination produces photons, which are used to emit light. The P-type epitaxial layer is electrically connected to the first electrode through the bonded first metal layer and the second metal layer, and the N-type epitaxial layer is directly electrically connected to the second electrode. The display panel of the present application may adopt a common cathode design. The second electrode is an ITO conductive layer.

Optionally, the roughness of the second metal sub-layer and the fifth metal sub-layer are both 1 nm-10 nm. The roughness of the second metal sublayer and the fifth metal sublayer will affect the bonding process. The roughness of the second metal sublayer and the fifth metal sublayer is greater than 10 nm, and the roughness is too large. The surface undulation of the metal sub-layer is large, the contact area of the second metal sub-layer and the fifth metal sub-layer when they are butt-bonded to each other is small, which affects the bonding strength, and the roughness of the second metal sub-layer and the fifth metal sub-layer It is less than 1nm, which is not conducive to the adhesion of other materials.

Optionally, in a direction perpendicular to the plane where the display panel is located, the thicknesses of the first metal sub-layer and the sixth metal sub-layer are both 20 nm-100 nm. The thickness of the first metal sub-layer and the sixth metal sub-layer is less than 20 nm, the adhesion is weak, the thickness of the first metal sub-layer and the sixth metal sub-layer is greater than 100 nm, the ohmic contact resistance is high, and the thickness of the display panel is increased, It is not conducive to the thinning of the display panel.

Optionally, in a direction perpendicular to the plane where the display panel is located, the thicknesses of the second metal sub-layer and the fifth metal sub-layer are both 50 nm-150 nm. When the thickness of the second metal sublayer and the fifth metal sublayer is less than 50 nm, due to the low conductivity of platinum metal in the second metal sublayer and the fifth metal sublayer, the second metal sublayer and the fifth metal sublayer are too thin. When the thickness is thin, the resistance of the second metal sublayer and the fifth metal sublayer is large, and the thermal effect is obvious.

Optionally, in a direction perpendicular to the plane where the display panel is located, the thicknesses of the third metal sub-layer and the fourth metal sub-layer before etching are both 10 nm-50 nm. When the thickness of the third metal sublayer and the fourth metal sublayer is less than 10 nm, the thickness is too thin, the distribution of the third metal sublayer and the fourth metal sublayer is not uniform, and there may be some areas where the third metal sublayer and the fourth metal sublayer are not deposited. In the case of four metal sublayers, when the thicknesses of the third metal sublayer and the fourth metal sublayer are greater than 50 nm, the thickness is too thick, which affects the activation effect of the second metal layer.

In a third aspect, based on the same inventive concept, the present application further provides a display device, including the display panel provided by any of the above-mentioned optional embodiments.

Description of drawings

FIG. 1 is a schematic structural diagram of a display panel of the present application applied to a display device;

2 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present application;

3a to 3d are schematic structural diagrams of the display panel after each step in FIG. 2 is performed;

4a to 4c are schematic diagrams of a partially etched bonding structure according to an embodiment of the present application;

FIG. 5 is a schematic diagram of bonding after partial etching provided by another embodiment of the present application;

6 is a flowchart of a method for manufacturing a display panel after epitaxial structure transfer provided by an embodiment of the present application;

7a to 7f are schematic structural diagrams of the display panel after each step in FIG. 6 is performed.

Description of reference numbers:

10-display panel; 20-display device; 110-first substrate; 120-second substrate; 111-growth substrate; 112-epitaxial structure; 113-first metal layer; 121-circuit substrate; 122-second metal layer ; 1131 - first surface; 1221 - second surface; 1132 - first metal sublayer; 1133 - second metal sublayer; 1134 - third metal sublayer; 1222 - fourth metal sublayer; 1223 - fifth metal Sublayer; 1224-sixth metal sublayer; 1141-first peak; 1142-first valley; 1143-second peak; 1144-second valley; 1121-P-type epitaxial layer; 1122-multiple quantum well layer; 1123 - N-type epitaxial layer; 116 - passivation layer; 117 - ITO conductive layer; 118 - first electrode; 119 - conductor; 1211 - groove; 130 - epitaxial structure.

Detailed ways

In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the related drawings. The preferred embodiments of the present application are shown in the accompanying drawings. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that a thorough and complete understanding of the disclosure of this application is provided.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the present application are for the purpose of describing particular embodiments only, and are not intended to limit the present application.

At present, the epitaxial structure on the growth substrate is generally transferred to the circuit substrate through the wafer bonding technology. However, the traditional wafer bonding technology often selects metal to bond at 400 °C, and the thermal expansion coefficient of the circuit substrate and the growth substrate is different. Obviously, the delamination problem caused by thermal mismatch often occurs in the high-temperature bonding process, which affects the display quality.

Based on this, the present application hopes to provide a solution that can solve the above technical problems, the details of which will be described in the subsequent embodiments.

The present application provides a manufacturing method of a display panel, a display panel, and a display device including the display panel. Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a display panel applied to a display device. The display panel 10 is located in a display device 20, and the display device 20 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a navigator, and the like.

First, the present application provides a method for manufacturing a display panel. As shown in FIG. 2 , the method for manufacturing a display panel in an embodiment specifically includes the following steps:

T10, providing a first substrate and a second substrate.

Referring to FIGS. 3 a and 3 b , the first substrate 110 includes a growth substrate 111 , an epitaxial structure 112 and a first metal layer 113 stacked in sequence, and the second substrate 120 includes a circuit substrate 121 and a second metal layer stacked on the circuit substrate 121 122, the epitaxial structure 112 is etched to form a light emitting diode.

T20, performing activation treatment on the first metal layer and performing activation treatment on the second metal layer.

T30, bonding the activated first metal layer and the activated second metal layer.

Referring to FIG. 3 c , after bonding the first metal layer 113 and the second metal layer 122 , the growth substrate 111 , the epitaxial structure 112 , the first metal layer 113 , the second metal layer 122 and the circuit substrate 121 are stacked in sequence.

T40, peeling off the growth substrate.

Referring to FIG. 3d , after the growth substrate 111 is peeled off, the epitaxial structure 112 is transferred to the circuit substrate 121 .

In the present application, by providing the first metal layer 113 and the second metal layer 122, and performing surface activation treatment on the first metal layer 113 and the second metal layer 122, the activated first metal layer 113 and the second metal layer 122 are at room temperature Atomic diffusion occurs when they are in contact with each other, so that the first metal layer 113 and the second metal layer 122 are bonded to each other to achieve bonding, so as to transfer the epitaxial structure 112 to the circuit substrate 121 . The bonding process of the present application is performed at room temperature, which avoids the delamination problem caused by thermal mismatch due to the large difference in the thermal expansion coefficients of the circuit substrate 121 and the growth substrate 111 in the current high-temperature bonding process, which is beneficial to the display panel. 10 shows improved performance.

3a and 3b, the first metal layer 113 includes a first surface 1131 facing away from the growth substrate 111, and the second metal layer 122 includes a second surface 1221 facing away from the circuit substrate 121; Activation treatment at 113 includes activation treatment for the first surface 1131; activation treatment for the second metal layer 122 includes activation treatment for the second surface 1221; bonding the activated first metal layer 113 with the activated second metal layer 113; The second metal layer 122 includes bonding the first surface 1131 and the second surface 1221 . The surface activation treatment method may include ion beam activation. During the surface activation treatment, the first surface 1131 and the second surface 1221 are first subjected to activation, the metal atoms of the first surface 1131 and the second surface 1221 are activated, and the first surface 1131 and the second surface 1221 are activated first. When the 1131 and the second surface 1221 are in contact with each other, the activated metal atoms diffuse to achieve bonding.

4a and 4b, the first metal layer 113 and the second metal layer 122 of the present application are three-layer metal structures with the same structure, and the first metal layer 113 includes a first metal sub-layer 1132 and a second metal sub-layer 1132 and a second metal layer that are stacked in sequence. The sub-layer 1133 and the third metal sub-layer 1134, wherein the first metal sub-layer 1132 is stacked on the epitaxial structure 112; the second metal layer 122 includes a fourth metal sub-layer 1222, a fifth metal sub-layer 1223 and The sixth metal sub-layer 1224 , wherein the sixth metal sub-layer 1224 is stacked on the circuit substrate 121 .

In a possible implementation manner, the first metal sublayer 1132, the second metal sublayer 1133, and the third metal sublayer 1134 may be sequentially deposited on the epitaxial structure 112 by electron beam evaporation technology. The five metal sub-layers 1223 and the sixth metal sub-layer 1224 can be sequentially deposited on the circuit substrate 121 by electron beam evaporation technology.

The first metal sublayer 1132 and the third metal sublayer 1134 of the first metal layer 113 and the fourth metal sublayer 1222 and the sixth metal sublayer 1224 of the second metal layer 122 may be titanium. The first metal sub-layer 1132 and the sixth metal sub-layer 1224 are titanium. Since titanium has a certain bonding effect, the second metal sub-layer 1133 is directly deposited on the epitaxial structure 112 or the fifth metal sub-layer 1223 is directly deposited on the circuit substrate 121 When the bonding effect is not ideal, by disposing a layer of titanium metal on the circuit substrate 121 and the epitaxial structure 112 (that is, the first metal sub-layer 1132 and the sixth metal sub-layer 1224 are titanium metal), the second metal sub-layer can be bonded. The role of the layer 1133 and the epitaxial structure 112 and the fifth metal sub-layer 1223 and the circuit substrate 121 increases the bonding strength between layers. The third metal sublayer 1134 and the fourth metal sublayer 1222 are titanium metal. On the one hand, titanium metal will protect the second metal sublayer 1133 and the fifth metal sublayer 1223 to avoid the When the fifth metal sublayer 1223 is directly exposed to the environment, the surface forms or adheres to an organic film layer or other impurities. The organic film layer will cause the activation of the surfaces of the second metal sublayer 1133 and the fifth metal sublayer 1223 to be difficult to handle. In one aspect, a part of the titanium metal of the third metal sublayer 1134 and the fourth metal sublayer 1222 may be retained during the activation process, so that the second metal sublayer 1133 and the fifth metal sublayer 1223 and the remaining third metal sublayer 1134 The double bonding with the remaining fourth metal sublayer 1222 increases the bonding strength.

The second metal sub-layer 1133 of the first metal layer 113 and the fifth metal sub-layer 1223 of the second metal layer 122 may be one of platinum, gold, copper, and aluminum. Metals such as platinum, gold, copper, and aluminum are easy to activate, and the activated platinum atoms, gold atoms, copper atoms or aluminum atoms are prone to atomic diffusion to achieve bonding.

There are two different bonding schemes in the process of bonding and connecting the first metal layer 113 and the second metal layer 122 of the present application, which specifically include:

In the first solution, during the surface activation treatment of the first metal layer 113 and the second metal layer 122, the third metal sublayer 1134 and the fourth metal sublayer 1222 are completely etched away, and the second metal sublayer 1133 Bonding and connection with the fifth metal sublayer 1223 .

In the process of performing the surface activation treatment on the first metal layer 113 and the second metal layer 122, the third metal sublayer 1134 and the fourth metal sublayer 1222 on the surface layer can be completely etched away. The requirements for etching are small. For example, when the degree of etching is controlled by the surface activation treatment time, part of the etching is to ensure that the third metal sub-layer 1134 remaining in the valley is not higher than the peak to ensure that the second metal sub-layer is 1133 and the fifth metal sub-layer 1223 can be in contact with each other, so the control of activation process conditions (such as time) for partial etching is relatively strict, which increases the difficulty of operation, while for complete etching, a longer activation etching time can be selected without considering The residual state of the third metal sub-layer 1134 and the fourth metal sub-layer 1222 has greater process flexibility and is convenient for operation.

4a, 4b, 4c and 5, in the process of performing the surface activation treatment on the first metal layer 113 and the second metal layer 122, the third metal sub-layer 1134 is partially etched away, The second metal sub-layer 1133 is exposed, and the fourth metal sub-layer 1222 is partially etched away to expose the fifth metal sub-layer 1223. The remaining third metal sub-layer 1134 is bonded to the remaining fourth metal sub-layer 1222. The exposed second metal sub-layer 1133 is bonded to the exposed fifth metal sub-layer 1223 .

During the surface activation process of the first metal layer 113 and the second metal layer 122, the third metal sublayer 1134 and the fourth metal sublayer 1222 on the surface layer will be etched away. By controlling the surface activation process, The third metal sublayer 1134 and the fourth metal sublayer 1222 may not be completely etched (ie, a part of the third metal sublayer 1134 remains on the first metal layer 113 , and a part of the fourth metal sublayer remains on the second metal layer 122 ) 1222), by controlling the surface roughness of the second metal sub-layer 1133 and the fifth metal sub-layer 1223, the second metal sub-layer 1133 and the fifth metal sub-layer 1223 have greater roughness, so that the second metal sub-layer 1133 and the fifth metal sub-layer 1223 have greater roughness. The surfaces of the layer 1133 and the fifth metal sublayer 1223 have peaks and valleys, and part of the third metal sublayer 1134 and the fourth metal sublayer on the surfaces of the second metal sublayer 1133 and the fifth metal sublayer 1223 can be retained during the activation process. Layer 1222, during the bonding process, the third metal sublayer 1134 and the fourth metal sublayer 1222 remaining on the surfaces of the second metal sublayer 1133 and the fifth metal sublayer 1223 are bonded to each other and corresponding to the second metal sublayer 1134 and the fourth metal sublayer 1222 The metal sublayer 1133 and the fifth metal sublayer 1223 are bonded to each other, due to the double bonding effect of the second metal sublayer 1133 and the fifth metal sublayer 1223 and the remaining third metal sublayer 1134 and the fourth metal sublayer 1222 Increased bond strength.

It can be understood that, referring to FIG. 4a, FIG. 4b, FIG. 4c and FIG. 5, during the partial etching process, the surface of the second metal sub-layer 1133 facing the third metal sub-layer 1134 includes a first wave peak 1141 and a first wave trough 1142, The surface of the fifth metal sub-layer 1223 facing the fourth metal sub-layer 1222 includes a second wave peak 1143 and a second wave trough 1144. During the activation treatment of the first metal layer 113 and the second metal layer 122, the third metal sub-layer Part 1134 is etched away to expose the first crest 1141 and part of the first trough 1142 of the second metal sub-layer 1133 and part of the third metal sub-layer 1134 remains in the remaining first troughs 1142, and the fourth metal sub-layer 1222 is partially etched removed to expose the second crest 1143 and part of the second trough 1144 of the fifth metal sub-layer 1223 and part of the fourth metal sub-layer 1222 remains in the remaining second trough 1144, the exposed first crest 1141 and the exposed part of the first trough 1142 is bonded and connected to the exposed second wave peak 1143 and the exposed part of the second wave valley 1144, and the third metal sub-layer 1134 remaining in the first wave valley 1141 is bonded and connected to the fourth metal sub-layer 1222 remaining in the second wave valley 1144. .

The growth substrate 111 can be a sapphire substrate, and the sapphire substrate can be removed by using a laser lift-off technology, the removal process is simple, the removal is clean, and residues are not easy to exist. In other embodiments, the growth substrate 111 may also be a gallium nitride substrate, a silicon substrate, a silicon carbide substrate, or the like, and a chemical etching method may be used to peel off the growth substrate. After the growth substrate 111 is peeled off, the epitaxial structure 112 is transferred to the circuit substrate 121 .

After peeling off the growth substrate 111 , referring to FIG. 6 , the steps of fabricating the display panel 10 further include:

S110, performing an etching process on the epitaxial structure.

Referring to FIG. 7a and FIG. 7b, the epitaxial structure 112 is directionally etched on the N-type epitaxial layer 1123 side of the epitaxial structure 112 by using a colloidal crystal or a photoresist as a mask.

S120 , etching the bonded first metal layer and the second metal layer.

Referring to FIG. 7c, after the epitaxial structure 112 is etched, the bonded first metal layer 113 and the second metal layer 122 are continuously etched to form independent sub-pixels (ie, the epitaxial structure 130). In other words, the epitaxial structure 112 between adjacent independent sub-pixels and the bonded first metal layer 113 and the second metal layer 122 are etched. The epitaxial structure 112 is electrically connected to the first electrode 118 through the bonded first metal layer 113 and the second metal layer 122 .

Generally speaking, the total thickness of the epitaxial structure 112 is 4.6um-5um. In addition, due to the use of low temperature, the thicknesses of the first metal layer 113 and the second metal layer 122 after bonding are relatively thin. Simple, this avoids the over-etching effect of plasma gas on the N-type epitaxial layer 1123 caused by etching the gold layer with a thickness of 2um in the traditional technical route, so that the performance of the display panel is not affected.

S130, depositing a passivation layer on the etched outer surface.

Referring to FIG. 7d, the passivation layer 116 may be silicon dioxide, and the deposition method may be chemical vapor deposition or the like.

S140, performing partial etching processing on the passivation layer.

Referring to FIG. 7e, the passivation layer 116 is partially etched by inductively coupled plasma etching to expose the cathode electrode region (not shown in FIG. 7e) and part of the N-type epitaxial layer 1123 on the circuit.

S150, depositing an indium tin oxide (Indium Tin Oxide, ITO) conductive layer on the passivation layer, and performing high temperature annealing treatment on the ITO conductive layer.

Referring to FIG. 7f , the ITO conductive layer can be deposited by chemical vapor deposition. Through the common cathode design, the ITO forms a transparent conductive network, which connects the N-type epitaxial layers 1123 of all sub-pixels and the cathode electrode of the circuit.

In the process of annealing ITO at high temperature (at this time, the growth substrate has been peeled off, and there is no delamination problem caused by the large difference in thermal expansion coefficient between the growth substrate and the circuit substrate at high temperature), the bonded first metal layer 113 and the first metal layer 113. The second metal layer 122 is also in a high temperature environment, and the first metal layer 113 and the second metal layer 122 bonded at room temperature can be further bonded and strengthened to enhance the bonding strength.

Secondly, based on the same inventive concept, the present application provides a display panel, and the specific structure of the display panel is as follows:

As shown in FIG. 7c, FIG. 7c is a schematic structural diagram of the display panel after etching. The display panel 10 includes a plurality of epitaxial structures 130 (the epitaxial structures 130 are the etched epitaxial structures 112 and the first metal layer 113 ) and a second substrate 120 , and the epitaxial structures 130 are arranged in an array on the second substrate 120 , each epitaxial structure 130 includes an epitaxial structure 112 and a first metal layer 113 stacked in sequence, and the second substrate 120 includes a circuit substrate 121 (the circuit substrate 121 may be a glass substrate or a silicon substrate, etc.) and stacked on the circuit substrate 121 The second metal layer 122, the first metal layer 113 and the second metal layer 122 are bonded and connected, wherein the first metal layer 113 is subjected to activation treatment and the second metal layer 122 is subjected to activation treatment.

The circuit substrate 121 includes a plurality of grooves 1211, the bottom of each groove 1211 is provided with a first electrode 118, the second metal layer 122 is laminated on the plurality of circuit substrates 121, and the filling groove 1211 is in contact with the first electrode 118. A metal layer 113 and a second metal layer 122 are bonded to form a conductor 119 , and the epitaxial structure 112 is electrically connected to the first electrode 118 through the conductor 119 . A second electrode (ie, the ITO conductive layer 117 ) is provided on the side of the epitaxial structure 112 away from the first metal layer 113 , and the epitaxial structure 112 is electrically connected to the second electrode.

Specifically, referring to FIG. 7f, the epitaxial structure 112 includes a P-type epitaxial layer 1121, a multiple quantum well layer 1122, and an N-type epitaxial layer 1123 that are stacked in sequence. The P-type epitaxial layer 1121 is located on the first metal layer 113, and the P-type epitaxial layer The holes of the layer 1121 and the electrons of the N-type epitaxial layer 1123 recombine in the multiple quantum well layer 1122 (ie, the light-emitting layer), and after the recombination, photons are generated and light is emitted. The N-type epitaxial layer 1123 is electrically connected to the second electrode (ie the ITO conductive layer 117 ), and the P-type epitaxial layer 1121 is connected to the first metal layer 113 and the second metal layer 122 (ie the conductor 119 ) through the bonded first metal layer 113 and the second metal layer 122 (ie the conductor 119 ). The electrical connection of the electrodes 118 realizes the conduction of the circuit, avoids the operation of providing other conductive structures to electrically connect the epitaxial structure 112 and the first electrode 118, simplifies the process, and reduces the cost.

Specifically, the P-type epitaxial layer 1121 may be P-GaN, the N-type epitaxial layer 1123 may be N-GaN, the first electrode may be a positive electrode, and the first electrode may be an aluminum electrode.

The roughness of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 is crucial to the bonding process, and the roughness of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 are both 1 nm-10 nm. The roughness of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 will affect the bonding process. The roughness of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 is greater than 10 nm. The surface undulations of the layer 1133 and the fifth metal sub-layer 1223 are relatively large, and the contact area of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 is small when they are butt-bonded to each other, which affects the bonding strength. The second metal sub-layer 1133 When the roughness of the second metal sublayer 1133 and the fifth metal sublayer 1223 is relatively large, the roughness can be reduced by fine polishing; the roughness of the second metal sublayer 1133 and the fifth metal sublayer 1223 is less than 1 nm, which is not conducive to the adhesion of other materials.

The first metal layer 113 and the second metal layer 122 of the present application are multi-layer metal structures, and the thicknesses of the first metal layer 113 and the second metal layer 122 can be nano-sized, specifically:

In the direction perpendicular to the plane of the display panel, the thicknesses of the first metal sub-layer 1132 and the sixth metal sub-layer 1224 are both 20 nm-100 nm. The thickness of the first metal sublayer 1132 and the sixth metal sublayer 1224 is less than 20 nm, and the adhesion is weak; the thickness of the first metal sublayer and the sixth metal sublayer 1224 of 1132 is greater than 100 nm, the ohmic contact resistance is high, and the display is increased. The thickness of the panel is not conducive to the thinning of the display panel.

In the direction perpendicular to the plane of the display panel, the thicknesses of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 are both 50 nm-150 nm. When the thicknesses of the second metal sublayer 1133 and the fifth metal sublayer 1223 are less than 50 nm, due to the low conductivity of platinum metal in the second metal sublayer 1133 and the fifth metal sublayer 1223, the second metal sublayer 1133 and the fifth metal sublayer 1223 When the five metal sublayers 1223 are too thin, the resistance of the second metal sublayer 1133 and the fifth metal sublayer 1223 is large and the thermal effect is obvious; when the thickness of the second metal sublayer 1133 and the fifth metal sublayer 1223 is greater than 150 nm, due to the thickness Too thick is not conducive to etching.

In the direction perpendicular to the plane of the display panel, the thicknesses of the third metal sub-layer 1134 and the fourth metal sub-layer 1222 before etching are both 10 nm-50 nm. When the thickness of the third metal sub-layer 1134 and the fourth metal sub-layer 1222 is less than 10 nm, the thickness is too thin, the distribution of the third metal sub-layer 1134 and the fourth metal sub-layer 1222 is not uniform, and there may exist the second metal sub-layer 1133 and the fourth metal sub-layer 1222. If the third metal sublayer 1134 and the fourth metal sublayer 1222 are not deposited on the partial area of the five metal sublayers 1223, the second metal sublayer 1133 and the fifth metal sublayer 1223 cannot be fully protected; the third metal sublayer 1223 cannot be fully protected; When the thickness of the layer 1134 and the fourth metal sub-layer 1222 is greater than 50 nm, the thickness is too thick, which affects the activation effect of the second metal layer.

The present application provides that the first metal layer 113 and the second metal layer 122 are bonded at room temperature. Specifically, atomic diffusion occurs when the first metal layer 113 and the second metal layer 122 are in contact with each other at room temperature, so that the first metal layer 113 and the second metal layer 122 are in contact with each other at room temperature. The metal layer 113 and the second metal layer 122 are bonded to each other to achieve bonding, so as to transfer the epitaxial structure 112 to the circuit substrate 121 . The bonding process of the present application is carried out at room temperature, which avoids the delamination problem caused by thermal mismatch due to the large difference in thermal expansion coefficient between the circuit substrate and the growth substrate in the current high-temperature bonding process, which is beneficial to the display of the display panel 10 Performance improvements. In the present application, after the epitaxial structure 112 is transferred, the epitaxial structure 112 is etched, so that the alignment process in the prior art is not required, and the alignment accuracy of the epitaxial structure transfer in the prior art is reduced.

It should be understood that the application of the present invention is not limited to the above examples. For those of ordinary skill in the art, improvements or transformations can be made according to the above descriptions, and all these improvements and transformations should belong to the protection scope of the appended claims of the present invention.

Claims (10)

1. A method of making a display panel, comprising: A first substrate and a second substrate are provided, wherein the first substrate includes a growth substrate, an epitaxial structure and a first metal layer stacked in sequence, the epitaxial structure is used to generate photons, and the second substrate includes a circuit substrate and a stacked layer a second metal layer on the circuit substrate; The first metal layer includes a first metal sublayer, a second metal sublayer and a third metal sublayer that are stacked in sequence, the first metal sublayer is stacked on the epitaxial structure, and the second metal layer It includes a fourth metal sub-layer, a fifth metal sub-layer and a sixth metal sub-layer that are stacked in sequence, the sixth metal sub-layer is stacked on the circuit substrate; the first metal sub-layer, the third metal sub-layer The metal sublayer, the fourth metal sublayer and the sixth metal sublayer are titanium, and the second metal sublayer and the fifth metal sublayer are one of platinum, gold, copper, and aluminum; performing activation treatment on the first metal layer, and performing activation treatment on the second metal layer; bonding the activated first metal layer and the activated second metal layer, so that the growth substrate, the epitaxial structure, the first metal layer, the second metal layer and the The circuit substrates are stacked in sequence; The growth substrate is peeled off. 2 . The method for manufacturing a display panel according to claim 1 , wherein the first metal layer includes a first surface facing away from the growth substrate, and the second metal layer includes a first surface facing away from the circuit substrate. 3 . the second surface; Activating the first metal layer includes: activating the first surface; activating the second metal layer includes: activating the second surface; The bonding of the activated first metal layer and the activated second metal layer includes: bonding the first surface and the second surface. 3 . The manufacturing method of the display panel according to claim 1 , wherein in the process of activating the first metal layer and the second metal layer, the third metal sublayer and the The fourth metal sublayer is completely etched away, and the second metal sublayer is bonded and connected to the fifth metal sublayer. 4 . The manufacturing method of the display panel according to claim 1 , wherein in the process of activating the first metal layer and the second metal layer, the third metal sub-layer is partially etched. 5 . removed to expose the second metal sub-layer, the fourth metal sub-layer is partially etched away to expose the fifth metal sub-layer, the remaining third metal sub-layer and the remaining fourth metal sub-layer The metal sub-layer is bonded and connected, and the exposed second metal sub-layer is bonded and connected with the exposed fifth metal sub-layer. 5 . The method for manufacturing a display panel according to claim 4 , wherein a surface of the second metal sub-layer facing the third metal sub-layer comprises a first wave crest and a first wave trough, and the fifth metal sub-layer comprises a first wave crest and a first wave trough. 6 . The surface of the sub-layer facing the fourth metal sub-layer includes a second wave crest and a second wave trough. During the activation treatment of the first metal layer and the second metal layer, the third metal sub-layer is partially etched away to expose the first crest and part of the first valley of the second metal sub-layer and part of the third metal sub-layer and the fourth metal sub-layer remain in the rest of the first valley The layer is partially etched away to expose the second peak and part of the second valley of the fifth metal sub-layer and a part of the fourth metal sub-layer remains in the remaining second valley, and the exposed The first wave crest and the exposed part of the first wave trough are bonded and connected to the exposed second wave crest and the exposed part of the second wave trough, and the third metal sub-layer remaining in the first wave trough is connected to the exposed second wave crest and the exposed part of the second wave trough. The fourth metal sub-layer remaining in the second valley is bonded and connected. 6. A display panel, characterized in that it comprises a plurality of epitaxial structures and a second substrate, the epitaxial structures are arrayed on the second substrate; An epitaxial structure and a first metal layer, the epitaxial structure is used to generate photons, the second substrate includes a circuit substrate and a second metal layer stacked on the circuit substrate, and the first metal layer includes layers stacked in sequence. a first metal sub-layer, a second metal sub-layer and a third metal sub-layer, the first metal sub-layer is stacked on the epitaxial structure, and the second metal layer includes a fourth metal sub-layer that is stacked in sequence, a fifth metal sublayer and a sixth metal sublayer, the sixth metal sublayer is stacked on the circuit substrate; the first metal sublayer, the third metal sublayer, and the fourth metal sublayer and the sixth metal sublayer is titanium, the second metal sublayer and the fifth metal sublayer are one of platinum, gold, copper, and aluminum; the first metal layer and the second metal sublayer are The metal layer is bonded and connected, wherein the first metal layer is activated and the second metal layer is activated. 7 . The display panel of claim 6 , wherein the circuit substrate comprises a plurality of grooves, the bottom of each groove is provided with a first electrode; the second metal layer is stacked on the plurality of grooves. 8 . contacting the first electrode on the circuit substrate and filling the groove; The first metal layer and the second metal layer are bonded to form a conductor, and the epitaxial structure is electrically connected to the first electrode through the conductor. 8 . The display panel of claim 7 , wherein a side of the epitaxial structure away from the first metal layer is provided with a second electrode, and the epitaxial structure is electrically connected to the second electrode. 9 . 9 . The display panel according to claim 8 , wherein the epitaxial structure comprises a P-type epitaxial layer, a multi-quantum well layer and an N-type epitaxial layer that are stacked in sequence, and the P-type epitaxial layer is located in the first On a metal layer, the P-type epitaxial layer is electrically connected to the first electrode through the conductor, the N-type epitaxial layer is electrically connected to the second electrode, and the holes of the P-type epitaxial layer are electrically connected to the first electrode. The electrons of the N-type epitaxial layer recombine in the multiple quantum well layer to generate photons, and the photons are used to emit light. 10. A display device, comprising the display panel according to any one of claims 6 to 9.

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