CN112988431B - Reliability evaluation method and system for different exceptions of SRAM (static random Access memory) type FPGA (field programmable Gate array) - Google Patents

Abstract

The invention discloses reliability evaluation and a system for different exceptions of an SRAM type FPGA, wherein the method comprises S100, selecting and configuring a memory position, carrying out fault injection test, and counting an error address and an exception bit number; s200, classifying the influence of different abnormalities on the system function, and S300, classifying and evaluating different conditions. The system includes a memory for storing a computer program; a processor for implementing the method for reliability assessment of different anomalies of an SRAM type FPGA as described above when executing said computer program. The method solves the problem of quantitative evaluation when the single event upset causes different influences on the system function, provides a new solution for the reliability evaluation of the accurate and comprehensive radiation-resistant reinforcement design, and has better feasibility and popularization value.

Description

Reliability evaluation method and system for different abnormality of SRAM type FPGA

technical field

The invention relates to the field of circuit reliability evaluation, in particular to a reliability evaluation method and system for different abnormalities of an SRAM type FPGA.

Background technique

Since the 21st century, under the background of the sharp increase in the demand for space signal processing capability and the shortening of the development cycle of space missions, space electronic instruments have put forward high demands for high-performance, short-cycle, low-cost processors and large-scale integrated circuits. Among them, the most critical is to solve the problem of reliable operation of semiconductor integrated circuits in spacecraft in the space radiation environment full of high-energy particles. Compared with traditional aerospace-grade devices, SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) has the characteristics of high information density, high performance, low development cost and reprogrammability, and has application value in the space field. getting bigger. When the high-energy particle radiation in space enters the semiconductor device, it will produce the Single Event Effect (SEE), which will lead to the abnormal function of the device and threaten the normal operation of the spacecraft in orbit. Among the single event effects, the single event upset (Single Event Upset, SEU) is the most serious harm to the FPGA circuit. After the FPGA circuit is mapped to the bottom configuration unit of the FPGA through the layout and wiring, the resources used contain different configuration bit information, and the single event flip in different configuration areas has different effects on the circuit function, so it is determined that the single event fault occurs in the FPGA circuit. Degree. In order to reduce or even eliminate the harm of single-event upsets to system reliability, a critical step is to conduct a comprehensive and efficient assessment of the impact of single-event effects.

At present, the main index used in the reliability evaluation of SRAM-type FPGAs in conventional methods is the flip cross section, and the parameters are generally obtained through high-energy particle irradiation tests. The flip cross section can be divided into static flip cross section and dynamic flip cross section. The static flip cross section is defined as the ratio of the number of single particle events to the total number of incident particles per unit area at normal incidence, indicating that single particle flip occurs when a single particle is incident on a unit area of the device. The probability of an event, which depends entirely on the process and design of the device itself, has nothing to do with the loading circuit. Compared with the static flip section, the dynamic flip section introduces an additional sensitivity factor, which is defined as the ratio of the sensitive bits to the total number of bits in the configuration memory, indicating that the dynamic flip characteristics of the circuit are not only related to the process and design of the device itself , also related to the circuit loaded above.

Each storage unit in the configuration memory of the FPGA controls the state of a specific programmable resource. Therefore, for any FPGA-based design, not all SEUs will cause the failure of the system function, and some SEUs may not affect the system function. . There are two reasons for this phenomenon: the first is the limited resource occupation of the design, the control bits corresponding to those unoccupied programmable logic resources generally have no effect on the system function, the second is that the circuit may take three Modular redundancy reinforcement design, although SEU occurs in some positions, it will not appear at the output end of the system after passing through the majority voter. The existence of this special phenomenon makes it impossible to comprehensively and accurately evaluate the reliability of the SRAM-type FPGA ruggedized design based on the evaluation index based on the flipped cross section.

SUMMARY OF THE INVENTION

The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the present invention proposes a reliability evaluation method and system for different anomalies of SRAM-type FPGA, which can comprehensively and accurately evaluate the reliability of SRAM-type FPGA reinforcement design.

The method for evaluating the reliability of SRAM-type FPGAs with different abnormalities according to the embodiment of the first aspect of the present invention includes the following steps;

S100, select the location of the configuration memory, perform a fault note error test, and count the error address and the number of abnormal bits;

S200. Classify according to the impact of different abnormalities on system functions, specifically:

The first type of exception: system function interruption can be recovered by readback refresh;

The second type of exception: system function interruption cannot be recovered by readback refresh, but can be recovered by software reset;

The third type of exception: system function interruption can only be recovered by power-on and reset.

S300, classifying and evaluating different situations, specifically:

Calculate the configuration data exception rate P _ij of the internal configuration structure j in the i-th abnormal situation of the FPGA;

Find the flip rate e _j of the internal configuration structure j of this model FPGA in a specific scenario;

Calculate the failure rate λ _i of the i-th type of abnormal situation according to the abnormal rate P _ij of the configuration data and the flip rate e _j ;

According to the failure rate λ _i , the reliability of the i-th type of abnormality is calculated.

The reliability evaluation method for different anomalies of an SRAM-type FPGA according to an embodiment of the present invention has at least the following technical effects: in the embodiment of the present invention, firstly, through the fault-injection test, the error addresses and the number of abnormal bits are counted, and then the system functions are evaluated according to different anomalies. Finally, based on the abnormal rate and flip rate of the classified configuration data, the failure rate and reliability of the FPGA circuit are calculated, and the degree of improvement of the system performance by the anti-single event design method is relatively evaluated through the classified test results. , which solves the problem of quantitative evaluation when single-event flipping has different effects on system functions, provides a new solution for accurate and comprehensive reliability evaluation of anti-radiation reinforcement design, and has good feasibility and promotion value. By evaluating various single-event protection design methods and measures, it provides a basis for the device selection of SRAM-type FPGAs.

According to some embodiments of the present invention, the calculation formula of the abnormality rate P _ij of the configuration data in the step S301 is:

Among them, b _ij is the number of abnormal bits of the internal configuration structure j in the i-th abnormal situation of the FPGA obtained by the fault note error test statistics, and b _total is the total number of configuration bits of the FPGA of this model.

According to some embodiments of the present invention, the calculation formula of the failure rate λ _i in the step S302 is:

According to some embodiments of the present invention, the calculation formula of the reliability R _i is:

where λ _i (t) is the failure rate function,

According to the second aspect of the present invention, the SRAM-type FPGA reliability evaluation system for different anomalies includes: a memory for storing a computer program; a processor for implementing the above-mentioned SRAM-type FPGA when the computer program is executed Reliability assessment methods for different anomalies.

The reliability evaluation system for different anomalies of SRAM-type FPGAs according to the embodiment of the present invention has at least the following technical effects: the embodiment of the present invention first passes the fault-injection test, counts the error addresses and the number of abnormal bits, and then adjusts the system functions according to different anomalies. Finally, based on the abnormal rate and flip rate of the classified configuration data, the failure rate and reliability of the FPGA circuit are calculated, and the degree of improvement of the system performance by the anti-single event design method is relatively evaluated through the classified test results. , which solves the problem of quantitative evaluation when single-event flipping has different effects on system functions, provides a new solution for accurate and comprehensive reliability evaluation of anti-radiation reinforcement design, and has good feasibility and promotion value. By evaluating various single-event protection design methods and measures, it provides a basis for the device selection of SRAM-type FPGAs.

Additional aspects and advantages of the present invention will be set forth, in part, from the following description, and in part will be apparent from the following description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, wherein:

Fig. 1 is the schematic flow chart of the reliability evaluation method of different abnormality of SRAM type FPGA in the embodiment of the present invention;

Fig. 2 is the variation curve of the reliability of the first type of abnormal situation in the embodiment of the present invention;

3 is a schematic block diagram of a three-mode redundant error-injection test platform in an embodiment of the present invention;

FIG. 4 is a flowchart of an error-injection test in an embodiment of the present invention.

Detailed ways

The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, only used to explain the present invention, and should not be construed as a limitation of the present invention.

In the description of the invention, it should be understood that the azimuth descriptions, such as up, down, front, rear, left, right, etc., indicate the azimuth or positional relationship based on the azimuth or positional relationship shown in the accompanying drawings, only for the purpose of It is convenient to describe the present invention and to simplify the description, rather than indicating or implying that the device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention.

In the description of the invention, the meaning of several is one or more, the meaning of multiple is two or more, greater than, less than, exceeding, etc. are understood as not including this number, above, below, within, etc. are understood as including this number. If it is described that the first and the second are only for the purpose of distinguishing technical features, it cannot be understood as indicating or implying relative importance, or indicating the number of the indicated technical features or the order of the indicated technical features. relation.

In the description of the present invention, unless otherwise clearly defined, words such as setting, installation, connection should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

Referring to Figure 1, a reliability evaluation method for different anomalies of SRAM-type FPGAs includes the following steps

S100, select the location of the configuration memory, perform a fault note error test, and count the error address and the number of abnormal bits;

S200. Classify according to the impact of different anomalies on system functions, and specifically divide them into the following three types of anomalies;

The first type of exception: system function interruption can be recovered by readback refresh;

The second type of exception: system function interruption cannot be recovered by readback refresh, but can be recovered by software reset;

The third type of exception: system function interruption can only be recovered by power-on and reset;

S300, classifying and evaluating different situations, as follows:

S301. Calculate the configuration data abnormality rate P _ij of the internal configuration structure j in the i-th abnormal situation of the FPGA, and the calculation formula of the configuration data abnormal rate P _ij is:

Among them, b _ij is the number of abnormal bits of the internal configuration structure j in the i-th abnormal situation of the FPGA obtained by the fault note error test statistics, b _total is the total number of configuration bits of the FPGA of this model, and the data refer to the chip data of the corresponding model manual.

S302 , look up the flip rate e _j of the internal configuration structure j of the FPGA of this model in a specific scenario on the chip data sheet, and the unit is h/(device·upset);

S303. Calculate the failure rate λ _i of the i-th type of abnormal situation, and its unit is 1/year (units are uniformly converted into years), and the calculation formula of the failure rate λ _i is:

S304. Calculate the reliability R _i of the i-th type of abnormal situation, and the calculation method is as follows

The failure rate function λ _i (t) is defined as:

Available

Among them, Q _i (t) represents the failure probability of the i-th type of abnormal situation, R _i represents the reliability of the i-th type of abnormal situation, and t represents the time.

The following is a detailed description of the Xilinx XQR2V3000 FPGA:

Through the internal configuration access port (ICAP) fault injection test, there are 104 abnormal bits in the configuration logic block (CLB). Table 1 provides the Virtex-Ⅱ device frame number, frame length and total number of configuration bits provided by the chip manual.

Table 1

According to the calculation in Table 1, it can be seen that the total number of configuration bits of this type of FPGA is 9582848, which belongs to the first type of abnormal situation. Therefore, the configuration data abnormality rate p ¹¹ is calculated as follows:

As shown in Table 2, the flip rate of the XQR2V6000 FPGA in the geosynchronous orbit working scenario provided by the chip manual.

Table 2

XQR2V6000—36000km Mean Time to Error Units Configuration Memory 1.8 Hours Block Memory 11.8 Hours POR-SEFI 221 Years SMAP-SEFI 181 Years

Since the architecture of the XQR2V6000 FPGA is similar to that of the XQR2V3000 FPGA, it can be seen from Table 2 that the CLB turnover rate of the XQR2V6000 FPGA in the geosynchronous orbit (GEO) is 1.8h/(device·upset), then the CLB failure rate of the XQR2V3000 FPGA is λ ₁ is calculated as follows:

Therefore, the reliability R ₁ of the first type of abnormal situation can be obtained as:

R ₁ =e ^-0.023t

As shown in Figure 2, according to the experimental results, the failure rate of the CLB of the XQR2V3000 FPGA in the geosynchronous orbit is about 0.023 (1/year), indicating that this method can be used for software-based radiation hardening design Relative assessment of method reliability.

The principle block diagram and test flow chart of the three-mode redundancy error-injection test platform are shown in Figure 3 and Figure 4, respectively, in which FPGA1, as the error-injection object of bit-by-bit flipping, is mainly responsible for running the three-mode redundancy reinforcement prototype FPGA program, and FPGA2 runs For single-mode FPGA programs, FPGA3 is responsible for comparing the functional differences between FPGA1 and FPGA2. Once the function is abnormal due to fault injection, after waiting for a certain period of time, if the function comparison results are still inconsistent, the output function to the DSP will be abnormally interrupted. At this time, the fault injection error is considered unrecoverable, and the fault injection will take effect; if the function comparison results are consistent, The fault injection error is considered to be reversible, and the fault injection error does not take effect at this time. FPGA4 is to load the FPGA chip, it is mainly responsible for controlling the Slave SelectMap interface to load FPGA1-3 globally, and also realizes the local dynamic refresh and error note for FPGA1 which adopts the three-mode redundancy design. DSP controls and configures the function start and stop of FPGA1 and FPGA2, outputs comparison results and debugging information through the serial port, and controls the start of dynamic refresh of FPGA1 through FPGA4, and traverses the automatic test of fault injection except BRAM resources. Once the DSP detects that the function is abnormally interrupted, it stops the function comparison, locks the current automatic error injection frame position and assigns the automatic error injection start frame address, and refreshes FPGA1 globally before the next fault injection, and refreshes all resources except BRAM. Correct configuration frame data. Then restart the error injection from the last error report position, and so on, until all resources except BRAM are traversed.

The embodiment of the present invention also relates to a reliability evaluation system for different anomalies of an SRAM-type FPGA, including: a memory for storing a computer program; and a processor for implementing the above-mentioned SRAM-type FPGA different when executing the computer program Exceptional reliability assessment methods.

To sum up, the advantages of the embodiments of the present invention are:

(1) Solve the problem of quantitative evaluation when the single event flip has different effects on the system function, and provides a new solution for the accurate and comprehensive reliability evaluation of the software-based radiation hardening design method;

(2) According to the influence of different anomalies on the system function, a new classification standard is proposed;

(3) Starting from the definition of failure rate function, the relationship between reliability and failure rate is deduced;

(4) By directly modifying the FPGA configuration data through program loading and fault injection, fault injection can be implemented and tests can be run on the chip to simulate single event effects in space;

(5) The number and specific positions of abnormal bits in the configuration structure can be obtained;

(6) By evaluating various single-event protection design methods and measures, it provides reference and reference for the device selection of SRAM-type FPGAs.

The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments. Within the scope of knowledge possessed by those of ordinary skill in the technical field, various modifications can be made without departing from the purpose of the present invention. kind of change.

Claims (5)

1. a different abnormal reliability assessment method of SRAM type FPGA, is characterized in that, comprises the following steps; S100. Perform a fault injection test on the FPGA, and count the number of error addresses and abnormal bits; S200. Classify according to the influence of different exceptions of the FPGA on the system function, specifically: The first type of exception: system function interruption can be recovered by readback refresh; The second type of exception: system function interruption cannot be recovered by readback refresh, but it can be recovered by software reset; The third type of exception: system function interruption can only be recovered by power-on and reset; S300, classifying and evaluating different abnormal situations, and the specific steps are: Calculate the configuration data abnormality rate P _ij of the internal configuration structure j of the FPGA in the i-th type of abnormal situation, i is 1, 2 or 3; Find the flip rate e _j of the internal configuration structure j of this model FPGA in a specific scenario; Calculate the failure rate λ _i of the i-th type of abnormal situation according to the abnormal rate P _ij of the configuration data and the flip rate e _j ; According to the failure rate λ _i , the reliability of the i-th type of abnormality is calculated. 2. the different abnormal reliability assessment method of SRAM type FPGA according to claim 1, is characterized in that: the calculation formula of described configuration data abnormal rate P _ij is

Among them, b _ij is the number of abnormal bits of the internal configuration structure j in the i-th abnormal situation of the FPGA obtained by the fault note error test statistics, and b _total is the total number of configuration bits of the FPGA of this model. 3. the different abnormal reliability assessment method of SRAM type FPGA according to claim 1, is characterized in that: the calculation formula of described failure rate λ _i is

4. the different abnormal reliability evaluation method of SRAM type FPGA according to claim 1, is characterized in that: the calculation formula of described reliability R _i is

where λ _i (t) is the failure rate function,

5. a different abnormal reliability evaluation system of SRAM type FPGA, is characterized in that, comprises: memory for storing computer programs; The processor is configured to, when executing the computer program, implement the reliability evaluation method for different exceptions of the SRAM-type FPGA according to any one of claims 1 to 4.

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