CN112988076A - Flash memory control method, storage device and controller - Google Patents

Abstract

The present invention provides a flash memory control method, a flash memory storage device and a flash memory controller. The method includes: instructing a flash memory module to perform a data consolidation operation to copy first data in a first physical unit into at least one second physical unit; after copying the first data and after erasing all data before the first physical unit, performing a programming operation on the first physical unit to change the data storage state of at least part of the storage units in the first physical unit from the first state to the second state; and After programming the first physical unit, an erase operation is performed on the first physical unit. Therefore, the data writing quality after the memory cells are erased can be improved.

Description

Flash memory control method, storage device and controller

Technical Field

The present invention relates to a memory control technology, and more particularly, to a flash memory control method, a flash memory storage device, and a flash memory controller.

Background

Portable electronic devices such as mobile phones and notebook computers have grown rapidly in these years, and the demand of consumers for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable electronic devices as exemplified above.

The memory cells in the rewritable non-volatile memory module are used for storing data by injecting charges into the memory cells. However, the charge injected into the memory cell may be lost as the data storage time increases, the data access operation increases, and/or the temperature changes. The lost charge may be countered by an erase voltage when the memory cell is subsequently erased, and the erase efficiency of the memory cell may be reduced. When new data needs to be written into the erased memory cells, the data writing quality may be poor due to the data in the memory cells not being erased completely.

Disclosure of Invention

The invention provides a flash memory control method, a flash memory storage device and a flash memory controller, which can improve the data writing quality of a memory unit after being erased.

An exemplary embodiment of the present invention provides a flash memory control method, which includes: instructing a flash memory module in a flash memory storage device to perform a data union operation to copy first data in a first physical unit of a plurality of physical units of the flash memory module to at least one second physical unit of the plurality of physical units; after copying the first data in the first physical unit to the at least one second physical unit and before performing the erasing operation on the first physical unit, performing a programming operation on the first physical unit again to change the data storage state of at least part of the memory cells in the first physical unit from a first state to a second state; and performing the erase operation on the first physical cell after programming the first physical cell.

An exemplary embodiment of the present invention further provides a flash memory storage device, which includes a connection interface unit, a flash memory module and a flash memory controller. The connection interface unit is used for connecting to a host system. The flash memory module includes a plurality of physical units. The flash memory controller is connected to the connection interface unit and the flash memory module. The flash memory controller is configured to perform a data union operation to copy first data in a first physical unit of the plurality of physical units to at least a second physical unit of the plurality of physical units. The flash memory controller is further configured to perform a program operation on the first physical unit after copying the first data in the first physical unit to the at least one second physical unit and before performing an erase operation on the first physical unit, so as to change the data storage state of at least some memory cells in the first physical unit from a first state to a second state. The flash memory controller is further configured to perform the erase operation on the first physical cell after programming the first physical cell.

An exemplary embodiment of the present invention further provides a flash memory controller for controlling a flash memory module. The flash memory module includes a plurality of physical units. The flash memory controller includes a host interface, a memory interface, and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the flash memory module. The memory management circuit is connected to the connection interface unit and the flash memory module. The memory management circuit is configured to perform a data union operation to copy first data in a first physical unit of the plurality of physical units to at least one second physical unit of the plurality of physical units. The memory management circuit is further configured to perform a programming operation on the first physical unit after copying the first data in the first physical unit to the at least one second physical unit and before performing an erasing operation on the first physical unit, so as to change the data storage state of at least some memory cells in the first physical unit from a first state to a second state. The memory management circuit is further configured to perform the erase operation on the first physical unit after programming the first physical unit.

In an exemplary embodiment of the present invention, the programming operation includes: programming the first entity unit according to preset data.

In an exemplary embodiment of the present invention, the programming operation includes: the first physical unit is programmed according to a preset programming mode.

In an exemplary embodiment of the present invention, the predetermined programming pattern includes a single-level cell pattern.

In an exemplary embodiment of the present invention, the programming operation includes: at least one memory cell in the first physical cells is converted from an erased state to a programmed state.

In an exemplary embodiment of the invention, the programming operation is configured to ensure that each of the memory cells in the first physical cell is in a programmed state before erasing the first physical cell.

Based on the above, after the first data is copied from the first physical cell to the second physical cell in the flash memory module and before the erase operation is performed on the first physical cell, the first physical cell may be programmed to change the data storage state of at least a portion of the memory cells in the first physical cell. After changing the data storage state of the memory cell, an erase operation may be performed on the first physical cell. Therefore, the data writing quality of the memory unit in the first entity unit after being erased can be improved.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;

FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIG. 7 is a diagram illustrating a data merging operation according to an exemplary embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating programming and associating a first physical unit to an idle region according to an example embodiment of the invention;

FIG. 9A is a graph illustrating a threshold voltage distribution of memory cells in a first physical cell in accordance with an exemplary embodiment of the present invention;

FIG. 9B is a graph illustrating a threshold voltage distribution of memory cells in a programmed first physical cell in accordance with an exemplary embodiment of the present invention;

FIG. 10 is a flowchart illustrating a method for controlling a flash memory according to an exemplary embodiment of the invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 may be connected to a system bus (system bus) 110.

In an example embodiment, the host system 11 may be connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, the host system 11 may be connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 over the system bus 110.

In an exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the main board 20 may be connected to the memory storage device 10 by wire or wirelessly.

In an example embodiment, the memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, Near Field Communication (NFC) memory storage, wireless fidelity (WiFi) memory storage, Bluetooth (Bluetooth) memory storage, or Bluetooth low energy memory storage (e.g., iBeacon) based memory storage based on various wireless Communication technologies. The motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an example embodiment, the host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the invention. Referring to fig. 3, in an exemplary embodiment, the host system 31 may be a digital camera, a video camera, a communication device, an audio player, a video player, a tablet computer, or the like. The memory storage device 30 may be any of various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In an exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Memory (Flash) interface standard, the CP interface standard, the CF interface standard, the Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is connected to the connection interface unit 402 and the rewritable nonvolatile memory module 406. The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may include a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a two Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell is the subordinate physical programming cell, and the Most Significant Bit (MSB) of a cell is the subordinate physical programming cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In an exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, and an error checking and correcting circuit 508.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In an exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In an exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is connected to the memory management circuitry 502. The memory management circuitry 502 may communicate with the host system 11 through a host interface 504. The host interface 504 is used for receiving and recognizing commands and data transmitted from the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 502 through the host interface 504. In addition, the memory management circuitry 502 may transfer data to the host system 11 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 506 is connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

An error checking and correcting circuit (also referred to as a decoding circuit) 508 is coupled to the memory management circuit 502 and is used to perform error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510 and a power management circuit 512. The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10.

In an example embodiment, the memory storage device 10 of fig. 4 is also referred to as a flash memory device, the rewritable non-volatile memory module 406 is also referred to as a flash memory module, and the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module. In an example embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6, the memory management circuit 502 can logically group the physical units 610(0) to 610(C) in the rewritable nonvolatile memory module 406 into a storage area 601, an idle (spare) area 602, and a system area 603. The entity units 610(0) to 610(a) in the storage area 601 store data (e.g., user data from the host system 11 in fig. 1). For example, entity units 610(0) -610 (A) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610(a +1) to 610(B) in the idle region 602 are not yet used to store data (e.g., valid data). The physical units 610(B +1) -610 (C) in the storage 603 are used to store management information (also referred to as system data), such as a logical-to-physical mapping table, a bad block management table, a device model, or other types of management information.

When data is to be stored, the memory management circuit 502 may select one physical unit from the physical units 610(a +1) to 610(B) of the idle region 602 and store the data from the host system 11 or at least one physical unit in the storage region 601 into the selected physical unit. At the same time, the selected physical unit may be associated to the storage area 601. In addition, if a physical unit in the storage area 601 does not store valid data (i.e. only stores invalid data), the physical unit can be re-associated to the idle area 602.

In an exemplary embodiment, each physical unit belonging to the idle region 602 is also referred to as a non-idle (non-spare) physical unit, and each physical unit belonging to the sub-region 601 is also referred to as an idle physical unit. In addition, a physical cell may include one or more physical erase cells.

Memory management circuitry 502 may configure logic 612(0) -612 (D) to map physical locations 610(0) -610 (A) in memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a Logical Address may include one or more Logical Block Addresses (LBAs) or other Logical management units. In another exemplary embodiment, a logic cell may correspond to a logic program cell, a logic erase cell, or be composed of a plurality of continuous or discontinuous logic addresses. In addition, each of logic cells 612(0) -612 (D) may be mapped to one or more physical cells. It should be noted that, in an exemplary embodiment, the memory management circuit 502 may not configure the logical unit mapped to the system area 603 to prevent the management information stored in the system area 603 from being modified by the user.

The memory management circuit 502 may record the mapping relationship between the logical units and the physical units (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. The logical-to-physical mapping table is stored in a physical unit of the system area 603. When host system 11 is going to read data from memory storage device 10 or write data to memory storage device 10, memory management circuit 502 may perform data access operations with respect to memory storage device 10 according to the logical-to-physical mapping table.

In an exemplary embodiment, valid data is the latest data belonging to a logical unit, and invalid data is not the latest data belonging to any logical unit. For example, if the host system 11 stores a new data item in a logical unit to overwrite the old data originally stored in the logical unit (i.e. update the data belonging to the logical unit), the new data item stored in the storage area 601 is the latest data belonging to the logical unit and will be marked as valid, and the overwritten old data item may still be stored in the storage area 601 but marked as invalid.

In an exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the entity unit storing the old data belonging to the logical unit is removed, and the mapping relationship between the logical unit and the entity unit storing the latest data belonging to the logical unit is established. However, in another exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the physical unit storing the old data belonging to the logical unit can still be maintained.

When the memory storage device 10 is shipped from a factory, the total number of physical units belonging to the idle area 602 is a preset number (e.g., 30). In operation of memory storage device 10, more and more physical units are selected from idle region 602 and associated with storage region 601 to store data (e.g., user data from host system 11). Therefore, the total number of physical units belonging to the idle region 602 gradually decreases as the memory storage device 10 is used.

In the operation of the memory storage device 10, the memory management circuit 502 may continuously update the total number of physical units belonging to the idle region 602. The memory management circuit 502 may perform the data union operation according to the number of physical units (i.e., the total number of idle physical units) in the idle region 602. For example, the memory management circuit 502 can determine whether the total number of physical units belonging to the idle region 602 is less than or equal to a threshold (also referred to as a first threshold). The first threshold value is, for example, a value of 2 or more (e.g., 10), but the invention is not limited thereto. If the total number of physical units belonging to the idle region 602 is less than or equal to the first threshold, the memory management circuit 502 may perform a data union operation. In an example embodiment, the data consolidation operation is also referred to as a garbage collection (garbage collection) operation.

In a data consolidation operation, the memory management circuit 502 may select at least one physical unit (also referred to as a source block) from the memory area 601 and attempt to copy valid data from the selected physical unit to another physical unit (also referred to as a target block). The physical unit for storing the copied valid data is selected from the idle area 602 and can be associated to the storage area 601. If valid data stored in a physical unit has been copied to the target block, the physical unit may be associated with the idle region 602 and may be erased for the next use.

In an exemplary embodiment, the operation of re-associating a physical unit from the storage area 601 back to the idle area 602 (or the operation of erasing a physical unit) is also referred to as releasing an idle physical unit. By performing the data union operation, one or more idle sdus are released and the total number of sdus belonging to the idle region 602 is gradually increased.

After the completion operation is started, the completion operation may be stopped if the entity unit belonging to the idle region 602 meets a specific condition. For example, the memory management circuit 502 may determine whether the total number of physical units belonging to the idle region 602 is greater than or equal to a threshold (hereinafter also referred to as a second threshold). For example, the second threshold value may be greater than or equal to the first threshold value. If the total number of physical units belonging to the idle region 602 is greater than or equal to the second threshold, the memory management circuit 502 may stop the data rounding operation. It should be noted that stopping the data merging operation refers to ending the currently executing data merging operation. After stopping a data consolidation operation, if the total number of the physical units belonging to the idle region 602 is again less than or equal to the first threshold, a next data consolidation operation may be performed again to attempt to release new idle physical units.

Fig. 7 is a diagram illustrating a data merging operation according to an exemplary embodiment of the present invention. Referring to FIG. 7, in the data merge operation, entities 711(0) to 711(E) (also referred to as first entities) may be selected as source block 710, and entities 721(0) to 721(F) (also referred to as second entities) may be selected as target block 720. For example, entity units 711(0) -711 (E) may be selected from storage 601 of FIG. 6, and entity units 721(0) -721 (F) may be selected from idle 602 of FIG. 6. The total number of physical units 711(0) -711 (E) and the total number of physical units 721(0) -721 (F) can be any number, and the invention is not limited thereto.

In a data merge operation, data 701 (also referred to as first data) may be collected by physical units 711(0) -711 (E) of the slave source block 710 and copied (e.g., written) to physical units 721(0) -721 (F) of the slave target block 720. Copied data 701 may include valid data originally stored in entity units 711(0) -711 (E).

In an example embodiment, in a data merge operation, in response to data (i.e., valid data) stored in a physical unit in the source block 710 being copied into the target block 720, the memory management circuit 502 may mark the data in the physical unit as invalid. In addition, in response to all valid data stored in a physical unit in source block 710 having been copied to target block 720, memory management circuitry 502 may associate the physical unit with idle region 602 of FIG. 6. The physical unit associated with the idle zone 602 may become a new idle physical unit. Before writing new data into the new idle physical unit next time, the idle physical unit needs to be erased to clear the old data therein.

In an example embodiment, after copying the data 701 (i.e., the first data) in the first physical unit to the second physical unit and before erasing the first physical unit, the memory management circuit 502 may perform the programming operation on the first physical unit again to overwrite at least a portion of the data in the first physical unit. For example, the overwritten data may include invalid data in the first physical unit.

In an example embodiment, a programming operation performed on a first physical cell after copying data 701 (i.e., first data) in the first physical cell to a second physical cell and before erasing the first physical cell may be used to change the data storage state of at least some of the memory cells in the first physical cell from one state (also referred to as a first state) to another state (also referred to as a second state). For example, assuming that a memory cell in the first physical cell is in a first state (e.g., erased state) before being erased, the programming operation can be used to change the memory cell from the first state (e.g., erased state) to a second state (e.g., non-erased state).

In the programming operation, the memory management circuit 502 can send a programming command sequence (or a write command sequence) to the rewritable nonvolatile memory module 406 to instruct the rewritable nonvolatile memory module 406 to program the memory cells in the first physical cells. According to the sequence of programming commands (or the sequence of writing commands), the rewritable nonvolatile memory module 406 may apply a programming voltage (or a writing voltage) to the memory cells of the first physical cells to rewrite the old data (i.e., the invalid data) in the memory cells. It should be noted that, in an exemplary embodiment, before erasing the memory cells, the old data (i.e., the invalid data) in the memory cells is rewritten to adjust at least a portion of the memory cells in the erased state to a non-erased state (also referred to as a programmed state), so as to improve the data writing quality when writing new data into the memory cells after erasing the memory cells.

In an example embodiment, the programming operation may also be automatically performed by the rewritable nonvolatile memory module 406 without being triggered by a programming command sequence (or a writing command sequence) from the memory management circuit 502. For example, in an exemplary embodiment, after the rewritable nonvolatile memory module 406 receives the erase command sequence indicating to erase the first physical unit from the memory management circuit 502, the rewritable nonvolatile memory module 406 may perform the programming operation on the first physical unit in response to the erase command sequence before actually erasing the first physical unit, so as to adjust at least a part of the memory cells in the erased state to be in the non-erased state. After determining that all the memory cells in the first physical cell are in the non-erase state (i.e., after performing the programming operation), the rewritable non-volatile memory module 406 can automatically and continuously perform the erase operation indicated by the erase command sequence to erase the first physical cell. In other words, in an example embodiment, even if the memory management circuit 502 does not send the program command sequence (or the write command sequence) to indicate the program operation, the rewritable nonvolatile memory module 406 can automatically perform the program operation on the first physical unit before performing the erase operation on the first physical unit, thereby improving the data writing quality of the subsequent first physical unit.

In an example embodiment, after performing the program operation on the first physical cell (i.e., overwriting invalid data in the first physical cell), the memory management circuit 502 may perform an erase operation on the first physical cell. For example, in the erase operation, the memory management circuit 502 can send an erase command sequence to the rewritable non-volatile memory module 406 to instruct the rewritable non-volatile memory module 406 to apply an erase voltage to the memory cells in the first physical cells to erase the data in the memory cells.

FIG. 8 is a schematic diagram illustrating programming and associating a first physical unit to an idle region according to an example embodiment of the invention. Referring to FIG. 8, continuing with the example embodiment of FIG. 7, after all valid data stored in physical units 711(0) -711 (E) (i.e., the first physical unit) of source block 710 are copied to target block 720, all data in physical units 711(0) -711 (E) are marked as invalid (i.e., as invalid data). Then, before associating entity units 711(0) -711 (E) with idle region 602, entity units 711(0) -711 (E) are programmed to overwrite the data (i.e., invalid data) in entity units 711(0) -711 (E). After programming physical cells 711(0) -711 (E), physical cells 711(0) -711 (E) may be associated with idle region 602 and may be subsequently erased.

It is noted that although the example embodiment of fig. 8 is illustrated as programming the first physical unit and then associating the first physical unit with the idle region 602. However, in another exemplary embodiment, the first physical unit may be associated with the idle region 602 before programming the first physical unit, or the first physical unit may be associated with the idle region 602 while programming the first physical unit, as long as it is ensured that the first physical unit is programmed before erasing the first physical unit.

In an example embodiment, if the first physical unit is not subjected to the programming operation, the memory management circuit 502 may suspend (or temporarily disallow) the association of the first physical unit to the idle region 602. In an example embodiment, if the first physical cell is not subjected to the program operation, the memory management circuit 502 may suspend (or temporarily disallow) the erase operation on the first physical cell. In an example embodiment, the memory management circuit 502 associates (or allows) only the first physical cell that has performed the program operation to the idle region 602. In an example embodiment, the memory management circuit 502 only (or only allows) the erase operation to be performed on the first physical cells on which the program operation has been performed.

In an exemplary embodiment, if all of the first physical cells to be erased are in a programmed state (i.e., programmed state), the data writing quality of writing new data into the memory cells after erasing the memory cells can be relatively better. On the other hand, if all the memory cells in the first physical cell to be erased are not in the programmed state, the data writing quality when writing new data into the memory cells after erasing the memory cells subsequently may be relatively poor.

In an example embodiment, the programming operation performed prior to erasing the first physical cells may be used to convert at least one memory cell of the first physical cells from an erased state to the programmed state. Alternatively, from another perspective, the programming operation performed on the first physical cell before erasing the first physical cell can be used to ensure that each memory cell in the first physical cell is in the programmed state before erasing the first physical cell. Therefore, after the memory cells in the first physical unit are actually erased, the data writing quality when new data are written into the memory cells can be improved.

In an example embodiment, in the programming operation performed before erasing the first physical unit, the memory management circuit 502 may instruct the rewritable non-volatile memory module 406 to program the first physical unit according to a predetermined data. For example, the default data may be meaningless data or dummy data (dummy data). For example, this default data is not user data stored by a host system (e.g., host system 11 of FIG. 1) or system data of memory storage device 10 itself. After programming the first physical cell according to the predetermined data, the data in the first physical cell is still invalid and can wait to be erased.

In an example embodiment, in the programming operation performed before erasing the first physical cell, the memory management circuit 502 may instruct the rewritable non-volatile memory module 406 to program the first physical cell according to a preset programming mode. For example, the predetermined programming pattern may include a Single Level Cell (SLC) pattern or other programming patterns. The predetermined programming pattern may be the same as or different from the programming pattern previously used to write the user data (i.e., the valid data) to the first physical unit.

FIG. 9A is a graph illustrating a threshold voltage distribution of memory cells in a first physical cell according to an exemplary embodiment of the invention. Referring to fig. 9A, it is assumed that a first physical unit only stores invalid data (or does not store valid data), and the threshold voltage distributions of a plurality of memory cells in the first physical unit are shown as distribution 91. In distribution 91, the current state of a portion of the memory cells in the first physical cell is the erased state (Er), and the current state of another portion of the memory cells in the first physical cell is the programmed state (P).

FIG. 9B is a graph illustrating threshold voltage distributions of memory cells in a programmed first physical cell in accordance with one example embodiment of the present invention. Referring to fig. 9B, continuing with the example embodiment of fig. 9A, after the program operation is performed on the first physical cell, the memory cell having the erase state (Er) originally in the first physical cell can be removed from the erase state (Er). For example, a memory cell that is out of the erased state (Er) can be converted to have the programmed state (P).

It is noted that fig. 9A and 9B illustrate the programming operation in a Single Level Cell (SLC) mode as an example. However, in another exemplary embodiment, the program operation performed before erasing the first physical cell may be performed based on other program modes, and the invention is not limited thereto. For example, in an exemplary embodiment, the programming operation performed before erasing the first physical cell may be performed as long as the memory cell in the first physical cell that was in the erased state can be removed from the erased state.

FIG. 10 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention. Referring to fig. 10, in step S1001, a data merging operation is performed on the flash memory module to copy first data in a first physical unit of the flash memory module to at least one second physical unit of the flash memory module. After copying the first data in the first physical cell to the at least one second physical cell and before performing an erase operation on the first physical cell, in step S1002, a program operation is performed on the first physical cell to change the data storage state of at least a portion of the memory cells in the first physical cell from a first state to a second state. After programming the first physical unit, in step S1003, the erase operation is performed on the first physical unit.

However, the steps in fig. 10 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 10 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, after the valid data in the first physical unit is completely copied to the target block in the data merging operation, the first physical unit needs to be programmed and then (allowed) erased. Therefore, the data writing quality when the first entity unit is subsequently extracted from the idle area to store new data can be improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (18)

1. A flash memory control method, comprising:

instructing a flash memory module in a flash memory storage device to perform a data union operation to copy first data in a first physical unit of a plurality of physical units of the flash memory module to at least one second physical unit of the plurality of physical units;

after copying the first data in the first physical unit to the at least one second physical unit and before performing the erasing operation on the first physical unit, performing a programming operation on the first physical unit again to change the data storage state of at least part of the memory cells in the first physical unit from a first state to a second state; and

after programming the first physical cell, performing the erase operation on the first physical cell.

2. The flash memory control method of claim 1, wherein the programming operation comprises:

programming the first entity unit according to preset data.

3. The flash memory control method of claim 1, wherein the programming operation comprises:

the first physical unit is programmed according to a preset programming mode.

4. The method of claim 3, wherein the predetermined programming pattern comprises a single level cell pattern.

5. The flash memory control method of claim 1, wherein the programming operation comprises:

at least one memory cell in the first physical cells is converted from an erased state to a programmed state.

6. The method of claim 1, wherein the programming operation is performed to ensure that each of the first physical cells is in a programmed state before erasing the first physical cells.

7. A flash memory storage device, comprising:

a connection interface unit for connecting to a host system;

a flash memory module, wherein the flash memory module comprises a plurality of physical units; and

a flash memory controller connected to the connection interface unit and the flash memory module,

wherein the flash memory controller is configured to perform a data union operation to copy first data in a first physical unit of the plurality of physical units to at least a second physical unit of the plurality of physical units,

the flash memory controller is further configured to perform a program operation on the first physical unit after copying the first data in the first physical unit to the at least one second physical unit and before performing an erase operation on the first physical unit to change the data storage state of at least some of the first physical unit from a first state to a second state, and

the flash memory controller is further configured to perform the erase operation on the first physical cell after programming the first physical cell.

8. The flash memory storage device of claim 7, wherein the programming operation comprises:

programming the first entity unit according to preset data.

9. The flash memory storage device of claim 7, wherein the programming operation comprises:

the first physical unit is programmed according to a preset programming mode.

10. The flash memory storage device of claim 9, wherein the preset programming pattern comprises a single level cell pattern.

11. The flash memory storage device of claim 7, wherein the programming operation comprises:

at least one memory cell in the first physical cells is converted from an erased state to a programmed state.

12. The flash memory storage device of claim 7, wherein the programming operation is configured to ensure that each of the first physical cells is in a programmed state before erasing the first physical cells.

13. A flash memory controller for controlling a flash memory module, wherein the flash memory module comprises a plurality of physical units, and the flash memory controller comprises:

a host interface for connecting to a host system;

a memory interface for connecting to the flash memory module; and

a memory management circuit connected to the connection interface unit and the flash memory module,

wherein the memory management circuit is configured to perform a data union operation to copy first data in a first physical unit of the plurality of physical units to at least a second physical unit of the plurality of physical units,

the memory management circuit is further configured to perform a program operation on the first physical unit after copying the first data in the first physical unit to the at least one second physical unit and before performing an erase operation on the first physical unit to change the data storage state of at least some of the memory cells in the first physical unit from a first state to a second state, and

the memory management circuit is further configured to perform the erase operation on the first physical unit after programming the first physical unit.

14. The flash memory controller of claim 13, wherein the programming operation comprises:

programming the first entity unit according to preset data.

15. The flash memory controller of claim 13, wherein the programming operation comprises:

the first physical unit is programmed according to a preset programming mode.

16. The flash memory controller of claim 15, wherein the preset programming pattern comprises a single level cell pattern.

17. The flash memory controller of claim 13, wherein the programming operation comprises:

at least one memory cell in the first physical cells is converted from an erased state to a programmed state.

18. The flash memory controller of claim 13, wherein the programming operation is configured to ensure that each of the first physical cells is in a programmed state prior to erasing the first physical cells.

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