CN112987840A - Voltage generating circuit - Google Patents
Voltage generating circuit Download PDFInfo
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- CN112987840A CN112987840A CN201911293386.9A CN201911293386A CN112987840A CN 112987840 A CN112987840 A CN 112987840A CN 201911293386 A CN201911293386 A CN 201911293386A CN 112987840 A CN112987840 A CN 112987840A
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- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/04—Regulating voltage or current wherein the variable is AC
- G05F3/06—Regulating voltage or current wherein the variable is AC using combinations of saturated and unsaturated inductive devices, e.g. combined with resonant circuit
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Abstract
The invention provides a voltage generating circuit, which generates an enable control signal through an enable control module and periodically turns on and off the voltage generating module, and the voltage generating module can be turned off only after the voltage is stable and sampling is completed because the start time required by the voltage generating module is short, so that the consumed average current is greatly reduced, the current is saved, and the power consumption of the voltage generating circuit is further reduced.
Description
Technical Field
The invention relates to the field of voltage generation circuits, in particular to a voltage generation circuit.
Background
The reference voltage generating circuit is an important module in analog circuit design, mixed signal circuit design and digital design, and provides a reference voltage which is not changed along with temperature and power supply voltage for a system. In the reference voltage generating circuit, the power consumption parameter plays a decisive role in the performance of the power supply, and the low-power-consumption reference voltage generating circuit is very important for the whole circuit.
Therefore, a voltage generation circuit with low power consumption is an important development direction.
Disclosure of Invention
The invention aims to provide a voltage generating circuit with low power consumption.
In order to solve the above problem, the present invention provides a voltage generation circuit including: the voltage generation module can generate a voltage signal; the holding module is connected with the voltage generating module through a sampling switch and is connected with the output end of the voltage generating circuit, and the holding module is used for sampling and holding the voltage signal; the refresh control module is used for generating at least one refresh control signal, and the refresh control signal is used for controlling the opening and closing of the sampling switch; the enabling control module is used for generating at least one enabling control signal, controlling the voltage generation module to be switched on and off by the enabling control signal and controlling the refreshing control module to generate the refreshing control signal; when the enabling control signal controls the voltage generation module to be started and the voltage signal of the voltage generation module is stable, the refreshing control signal controls the sampling switch to be closed so as to connect the holding module with the voltage generation module, and the holding module samples the voltage signal; when the holding module finishes sampling, the refreshing control signal controls the sampling switch to be disconnected so as to cut off the connection between the holding module and the voltage generating module, and the enabling control signal controls the voltage generating module to be closed.
Further, the enabling control signal controls the voltage generating module and the refreshing control module to be periodically turned on and off.
Furthermore, the time of one period is 20-80 milliseconds.
Further, the enable control module comprises a ring oscillator circuit.
Further, the duty ratio of the enable control signal is controlled by controlling the charge and discharge current of the ring oscillator circuit.
Further, the cycle range of the ring oscillator circuit is 20-80 milliseconds.
Furthermore, the ring oscillation circuit is formed by connecting odd inverters in series and connecting an output end and an input end in an end-to-end manner.
Further, a capacitor is arranged at the output end of at least one inverter.
Furthermore, the enable control module further comprises an in-phase buffer circuit, the output end of the ring oscillation circuit is connected with the input end of the in-phase buffer circuit, and the output end of the in-phase buffer circuit outputs the enable control signal.
Further, the refresh control module includes: the first delay circuit delays the enabling control signal and outputs a first delay signal; the refresh control signal generation circuit comprises a second delay circuit and an AND gate circuit, wherein the second delay circuit is an inverse delay circuit, the first delay signal is used as an input signal of the second delay circuit and the AND gate circuit, the second delay circuit outputs a second delay signal, the second delay signal is used as the other input signal of the AND gate circuit, and the output signal of the AND gate circuit is used as the refresh control signal.
Further, the first delay circuit is formed by connecting an even number of inverters in series, and a capacitor is arranged at the output end of at least one inverter.
Further, the first delay circuit is configured to: when the voltage signal of the voltage generation module is stable, the first delay circuit outputs the first delay signal.
Further, the second delay circuit is formed by connecting an odd number of inverters in series.
Furthermore, a capacitor is arranged at the output end of at least one inverter.
Further, the holding module comprises at least one capacitor.
Furthermore, a buffer module is arranged at the output end of the voltage generating circuit.
The voltage generation circuit further includes: the comparison module is provided with an input end and an output end, the input end is connected with the output end of the voltage generation module and receives the voltage signal, the comparison module can compare the voltage signal with a preset value, and the output end of the comparison module outputs a comparison result signal; and the AND gate module is provided with an input end and an output end, the input end is respectively connected with the enabling control module and the comparison module and receives the enabling control signal and the comparison result signal, the output end is connected with the refreshing control module, and the refreshing control module generates the refreshing control signal according to the output signal of the AND gate module.
The invention has the advantages that the enabling control module generates the enabling control signal to periodically turn on and turn off the voltage generating module, and the voltage generating module can be turned off only after the voltage is stable and sampling is completed because the starting time required by the voltage generating module is short, so that the consumed average current is greatly reduced, the current is saved, and the power consumption of the voltage generating circuit is further reduced.
Drawings
FIG. 1 is a block diagram of one embodiment of a voltage generation circuit according to the present invention;
FIG. 2 is a timing diagram of a first enable control signal, a first voltage signal, and a first refresh control signal for controlling the first sampling switch to turn on and off according to the voltage generating circuit of the present invention;
FIG. 3 is a circuit diagram of an embodiment of a refresh control module of the voltage generation circuit of the present invention;
FIG. 4 is a timing diagram of a first enable control signal, a first voltage signal, a first delay signal and a first refresh control signal of the voltage generating circuit according to the present invention;
FIG. 5 is a circuit diagram of an embodiment of an enable control module of the present invention.
Detailed Description
The following describes in detail a specific embodiment of the low power consumption voltage generation circuit according to the present invention with reference to the drawings.
FIG. 1 is a block diagram of an embodiment of a voltage generation circuit according to the present invention. Referring to fig. 1, the voltage generating circuit of the present invention includes at least one voltage generating module, at least one holding module, a refresh control module 30 and an enable control module 40.
The voltage generation circuit of the present invention may include a plurality of voltage generation modules, which may be arranged in parallel. Fig. 1 schematically shows two voltage generating modules, namely a first voltage generating module 10 and a second voltage generating module 11, which are arranged in parallel. The voltage generation module can generate a voltage signal. Specifically, referring to fig. 1, the first voltage generating module 10 can generate a first voltage signal VGEN1, and the second voltage generating module 11 can generate a second voltage signal VGEN 2. The voltage generating module can be a linear voltage stabilizing circuit, a charge pump voltage stabilizing circuit and the like.
The inventive voltage generation circuit may comprise a plurality of holding modules, which may be arranged in parallel. The holding module is connected with the voltage generating module through a sampling switch and is connected with the output end of the voltage generating circuit. That is, one of the holding modules corresponds to one of the voltage generating modules. Specifically, referring to fig. 1, the first holding module 20 is connected to the first voltage generating module 10 through a first sampling switch 50, and the second holding module 21 is connected to the second voltage generating module 11 through a second sampling switch 51.
The holding module may be an energy storage element, such as a capacitor. The holding module is used for sampling and holding the voltage signal. For example, when the first sampling switch 50 is closed, the first voltage signal VGEN1 of the first voltage generating module 10 is applied to the first holding module 20, and the first voltage generating module 10 charges the first holding module 20. The first holding module 20 samples the first voltage generating module 10 and holds the first voltage signal VGEN1 of the first voltage generating module 10. When the second sampling switch 51 is closed, the second voltage signal VGEN2 of the second voltage generating module 11 is applied to the second holding module 21, and the second voltage generating module 11 charges the second holding module 21. The second holding module 21 samples the second voltage generating module 11 and holds the second voltage signal VGEN2 of the second voltage generating module 11.
The refresh control module 30 is configured to generate at least one refresh control signal, where the refresh control signal is used to control the opening and closing of the sampling switch. In this embodiment, when the holding module is required to sample the voltage generating module, the refresh control signal generated by the refresh control module 30 is at a high level, and the refresh control signal controls the sampling switch to be closed, so that the holding module is connected to the voltage generating module, so that the holding module samples the voltage generating module; when the voltage generating module does not need to be sampled by the holding module, the refresh control signal generated by the refresh control module 30 is at a low level, and the sampling switch is turned off, so that the holding module is disconnected from the voltage generating module, and the holding module stops sampling the voltage generating module. It is understood that the high level and the low level are only used for better illustrating the implementation process of the method, and can be customized during the actual design.
In this embodiment, the refresh control module 30 is capable of generating a plurality of refresh control signals. Specifically, the refresh control module 30 generates a first refresh control signal S1 and a second refresh control signal S2, when the first holding module 20 needs to sample the first voltage generating module 10, the first refresh control signal S1 is high, and the first sampling switch 50 is controlled to be closed, so that the first holding module 20 is connected to the first voltage generating module 10, so that the first holding module 20 samples the first voltage generating module 10; when the second holding module 21 needs to sample the second voltage generating module 11, the second refresh control signal S2 is at a high level, and the second sampling switch 51 is controlled to be closed, so that the second holding module 21 is connected to the second voltage generating module 11, so that the second holding module 21 samples the second voltage generating module 11.
In other embodiments of the present invention, the refresh control module 30 may also generate only one refresh control signal, and the refresh control signal controls the plurality of sampling switches to be turned on and off simultaneously. For example, the refresh control module 30 generates a refresh control signal, and the refresh control signal controls the first sampling switch 50 and the second sampling switch 51 to be turned on and off simultaneously.
The enable control module 40 is configured to generate at least one enable control signal, where the enable control signal controls the voltage generation module to turn on and off, and controls the refresh control module to generate the refresh control signal. Specifically, in the present embodiment, the enable control module 40 generates a first enable control signal EN1 and a second enable control signal EN 2. The first enable control signal EN1 is used to control the first voltage generating module 10 to turn on and off, and control the refresh control module 30 to generate a first refresh control signal S1; the second enable control signal EN2 is used to control the second voltage generating module 11 to turn on and off, and control the refresh control module 30 to generate a second refresh control signal S2.
Each voltage generation module corresponds to an output end, and the output end outputs the output signal of the voltage generation circuit. Referring to fig. 1, an output terminal corresponding to the first voltage generating module 10 outputs a first output signal VGEN11, and an output terminal corresponding to the second voltage generating module 11 outputs a second output signal VGEN 22.
Furthermore, a buffer module is arranged at the output end of the voltage generating circuit. Specifically, a first buffer module 60 is disposed at an output end corresponding to the first voltage generating module 10, and a second buffer module 61 is disposed at an output end corresponding to the second voltage generating module 11. The buffer module can be a low power consumption operational amplifier.
In the voltage generation circuit, the nature of the voltage generation module determines that a voltage signal generated by the voltage generation module is unstable at the initial stage of starting the voltage generation module, after a plurality of times, the voltage signal generated by the voltage generation module tends to be stable, and when the voltage signal generated by the voltage generation module is stable, the refresh control signal controls the sampling switch to be closed so as to connect the holding module with the voltage generation module, and the holding module samples the voltage signal; when the holding module finishes sampling, the refreshing control signal controls the sampling switch to be disconnected so as to cut off the connection between the holding module and the voltage generating module, and the enabling control signal controls the voltage generating module to be closed.
Because the starting time required by the voltage generation module is short, the voltage generation module can be turned off only after the voltage is stable and sampling is completed, so that the consumed average current can be greatly reduced, and the aim of low power consumption is fulfilled. The voltage generation circuit can realize the control of a plurality of voltage generation modules through one set of enabling control module and refreshing control module, thereby further saving the power consumption.
Further, in order to ensure that the refresh control signal generated by the refresh control module outputs a high level after the voltage signal output by the voltage generation module is stable, in another embodiment of the present invention, the voltage generation circuit further includes a comparison module and an and gate module.
The input end of the comparison module is connected with the output end of the voltage generation module, the input end of the AND gate module is connected with the output end of the comparison module and the output end of the enable control module, and the output end of the AND gate module is connected with the input end of the refresh control module.
And the comparison module receives the voltage signal, compares the voltage signal with a preset value prestored in the comparison module and outputs a comparison result signal. If the voltage signal is greater than or equal to the preset value, it is indicated that the voltage signal is stable, the output end of the comparison module outputs a high level, and if the voltage signal is less than the preset value, it is indicated that the voltage signal is not stable, the output end of the comparison module outputs a low level. The preset value may be determined according to a stable voltage that the voltage generation module can generate. For example, the preset value is a stable voltage that can be generated by the voltage generation module, or the preset value is 90%, 85%, and the like, of the stable voltage that can be generated by the voltage generation module. It can be understood that, when the voltage generation circuit includes a plurality of voltage generation modules, the voltage signal output by each voltage generation module needs to be compared with the preset value.
And the AND gate module receives the enable control signal and the comparison result signal, and the refresh control module generates the refresh control signal according to the output signal of the AND gate module. According to the characteristics of the AND gate module, when the enable control signal and the comparison result signal are both at a high level, the AND gate module outputs the high level, and the refresh control signal generated by the refresh control module can control the sampling switch to be closed; when the enable control signal and the comparison result signal have low levels, the and gate module outputs the low level, and the refresh control signal generated by the refresh control module can control the sampling switch to be switched off. It can be understood that, due to the characteristics of the and gate module, when the voltage generation circuit includes a plurality of voltage generation modules, the refresh control signal generated by the refresh control module can control the sampling switch to be turned on only when the voltage signals generated by all the voltage generation modules are stable signals, and when the voltage signal generated by at least one voltage generation module is an unstable signal, the refresh control signal generated by the refresh control module controls the sampling switch to be turned off.
The voltage generation circuit can ensure that the holding module carries out sampling after the voltage signal generated by the voltage generation module is stable through the design of the comparison module and the AND gate module.
Fig. 2 is a timing diagram of the first enable control signal EN1, the first voltage signal VGEN1, and the first refresh control signal S1 that controls the first sampling switch 50 to be turned on and off. Referring to fig. 2, the enable control module applies a first enable control signal EN1 to the first voltage generating module 10, when the first enable control signal EN1 is at a high level, the first voltage generating module 10 is activated, and when the first voltage generating module 10 is initially activated, the first voltage signal VGEN1 generated by the first voltage generating module 10 drops to zero, but is unstable, at this time, the first refresh control signal S1 is at a low level, and the first sampling switch 50 is in an off state; after a certain time, when the first voltage signal VGEN1 generated by the first voltage generation module 10 reaches a preset value and is stabilized or is stabilized for a set time, the first refresh control signal S1 changes from low level to high level, and the first sampling switch 50 is closed, so that the first holding module 20 samples the first voltage generation module 10; after the first holding module 20 finishes sampling, the first refresh control signal S1 goes low, and the first sampling switch 50 is turned off, so that the first holding module 20 is disconnected from the first voltage generating module 10. After the first holding module 20 finishes sampling or at intervals, the first enable control signal EN1 changes from high level to low level, the first voltage generating module 10 is turned off, and the first voltage signal VGEN1 drops to zero, so that the average current consumed in one or more periods is greatly reduced, and the purpose of low power consumption is further achieved. Further, after a certain time interval, the above sequence is repeated.
Further, the enabling control signal controls the voltage generating module and the refreshing control module to be periodically turned on and off. That is, the enable control module 40 applies periodic enable control signals to the voltage generation module and the refresh control module at set intervals, so that the voltage generation module and the refresh control module 30 are periodically turned on and off. The purpose is to maintain the voltage on the holding module and to avoid the voltage on the holding module from being lost due to electric leakage and the like. Further, the set time may be several tens of milliseconds.
Further, the present invention also provides a circuit diagram of an embodiment of the refresh control module 30. Fig. 3 is a circuit diagram of an embodiment of the refresh control module 30 of the present invention. Referring to fig. 3, the refresh control module 30 includes a first delay circuit 31 and a refresh control signal generating circuit 32.
The first Delay circuit 31 delays the enable control signal and outputs a first Delay signal Delay 1. Specifically, for example, the enable control module 40 inputs the first enable control signal EN1 to the refresh control module 30, the signal input at the input end of the first extension circuit 31 is the first enable control signal EN1, and after the Delay of the first extension circuit 31, the output signal is the first Delay signal Delay1, and the first Delay signal Delay1 is delayed by a certain time compared with the first enable control signal EN 1.
The first delay circuit 31 is formed by connecting an even number of inverters in series, and a capacitor C is provided at an output end of at least one inverter. As shown in fig. 3, in the present embodiment, the first delay circuit 31 is formed by two inverters a1 and a2 connected in series, and a capacitor C is disposed at an output end of the first inverter a1 to increase the delay time of the first enable control signal EN 1.
In the present embodiment, the first delay circuit 31 is a one-side delay circuit. Specifically, a bias voltage VNBIAS is applied to the pull-down unit of the first delay circuit 31, and when the first delay circuit 31 inputs a high level, the bias voltage VNBIAS charges and discharges the pull-down unit to delay the rising edge signal output by the first delay circuit 31; when the first delay circuit 31 inputs a low level, the bias voltage VNBIAS of the first delay circuit 31 is not charged or discharged to the pull-up unit, so that the falling edge signal output by the first delay circuit 31 is not delayed.
Further, the first delay circuit 31 is configured to: when the voltage signal of the voltage generation module is stable, the first Delay circuit 31 outputs the first Delay signal Delay 1. That is, in order to completely avoid that the refresh control module 30 outputs a refresh control signal when the voltage signal of the voltage generating module is not stable, the Delay time of the first Delay circuit 31 is increased, so that the first Delay circuit 31 outputs the first Delay signal Delay1 after the voltage signal of the voltage generating module is stable.
The refresh control signal generation circuit 32 includes a second delay circuit 321 and an and circuit 322.
The second delay circuit 321 is an inverting delay circuit. Specifically, the second delay circuit 321 is formed by connecting an odd number of inverters in series. For example, referring to fig. 3, the second delay circuit 321 is formed by connecting inverters a1, a2 and A3 in series. Further, in order to increase the delay time of the second delay circuit 321, a capacitor is disposed at an output end of at least one of the inverters. For example, referring to fig. 3, a capacitor C is disposed at the output of each of the inverters a1 and a 2.
The first Delay signal Delay1 is used as an input signal of the second Delay circuit 321 and the and circuit 322. The second Delay circuit 321 outputs a second Delay signal Delay2, and the second Delay signal Delay2 is used as another input signal of the and circuit 322. The output signal of the and circuit 322 serves as the refresh control signal. In this embodiment, the and circuit 322 can be formed by a nand gate and a not gate connected in series.
The operation of the refresh control module 30 will be described below by taking the first enable control signal EN1 for controlling the first voltage generation module 10 to generate the first voltage signal VGEN1 and the refresh control module 30 for generating the first refresh control signal S1 as examples.
Fig. 4 is a timing diagram of the first enable control signal EN1, the first voltage signal VGEN1, the first Delay signal Delay1, and the first refresh control signal S1, please refer to fig. 4.
The enable control module 40 applies a first enable control signal EN1 to the first voltage generation module 10 and the first delay circuit 31, the first voltage generation module 10 is activated when the first enable control signal EN1 is at a high level, and the first voltage signal VGEN1 slowly rises without directly reaching a preset value when the first voltage generation module 10 is initially activated; the first enable control signal EN1 is delayed by the first Delay circuit 31, and the first Delay circuit 31 outputs a first Delay signal Delay1 after the first voltage signal VGEN1 reaches a preset value, i.e., stabilizes.
When the first Delay signal Delay1 is input to the second Delay circuit 321 and the and gate circuit 322, and when the first Delay signal Delay1 is at a high level, due to the Delay action of the second Delay circuit 321, when the first Delay signal Delay1 is input to the and gate circuit 322, the first Delay signal Delay1 is not inverted, that is, the second Delay signal Delay2 and the first Delay signal Delay1 output by the second Delay circuit 321 are both at a high level, the and gate circuit 322 outputs a high level, that is, the first refresh control signal S1 is at a high level, and the first refresh control signal S1 controls the first sampling switch 50 to be closed, so that the first holding module 20 samples the first voltage generating module 10. After a plurality of times, the first Delay signal Delay1 is changed into a second Delay signal Delay2 after being delayed by the second Delay circuit 321, at this time, signals at two input ends of the and circuit 322 are respectively at a high level (the first Delay signal Delay1) and a low level (the second Delay signal Delay2), the and circuit 322 outputs a low level, that is, the first refresh control signal S1 is at a low level, and the first refresh control signal S1 controls the first sampling switch 50 to be turned off, so that the first holding module 20 is turned off from the first voltage generating module 10.
Further, after the first holding module 20 finishes sampling or at intervals, the first enable control signal EN1 changes from high level to low level, the first voltage generating module 10 is turned off, and the first voltage signal VGEN1 drops to zero, so that the total average current consumed can be greatly reduced, and the purpose of low power consumption is further achieved. Further, after a certain time interval, the above sequence is repeated.
Further, the present invention also provides a circuit diagram of an embodiment of the enable control module 40. FIG. 5 is a circuit diagram of one embodiment of the enable control module 40 of the present invention. Referring to fig. 5, the enable control module 40 includes a ring oscillator circuit 41 with low power consumption. The output of the ring oscillator circuit 41 is an oscillation generating high-low level signal, so that the enable control module 40 generates an enable control signal.
The ring oscillator circuit 41 is formed by connecting odd inverters in series and connecting an output end and an input end to end. Specifically, referring to fig. 5, the ring oscillator circuit 41 is formed by connecting three inverters a1, a2 and A3 in series, and connecting the output end and the input end to end. Further, in consideration of a large device leakage at a high temperature, the period of the ring oscillator circuit 41 is in a range of 20 to 80ms, for example, 40ms, 60ms, or the like.
The enable control module 40 can output the enable control signal through a low power consumption ring oscillator, and has a simple structure. Since the ring oscillator frequency is not high (where f is 12Hz to 50Hz), it can be started with a small bias current (e.g., 50 nA). Further, a capacitor may be added to the output of at least one inverter to increase the period of the enable control signal.
Further, since the enable control signal generated by the enable control module 40 only needs to periodically enable the voltage generation module, and the voltage generation module can be turned off after the voltage signal output by the voltage generation module is stable and the sampling operation is completed, the duty ratio of the enable control signal can be controlled by controlling the charging and discharging current of the ring oscillator circuit.
Further, the enable control module 40 further includes an in-phase buffer circuit 42, an output end of the ring oscillator circuit 41 is connected to an input end of the in-phase buffer circuit 42, and an output end of the in-phase buffer circuit 42 outputs the enable control signal. In this embodiment, the in-phase buffer circuit 42 is formed by two inverters a1 and a2 connected in series, but in other embodiments of the present invention, the in-phase buffer circuit 42 may be formed by another even number of inverters a1 and a2 connected in series.
In the present embodiment, the bias currents PBIAS and NBIAS generate the charging and discharging currents of the ring oscillator circuit 41 through a current mirror structure, so that the ring oscillator circuit 41 generates an enable control signal.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and improvements can be made without departing from the principle of the present invention, and these modifications and improvements should also be considered as the protection scope of the present invention.
Claims (17)
1. A voltage generation circuit, comprising:
the voltage generation module can generate a voltage signal;
the holding module is connected with the voltage generating module through a sampling switch and is connected with the output end of the voltage generating circuit, and the holding module is used for sampling and holding the voltage signal;
the refresh control module is used for generating at least one refresh control signal, and the refresh control signal is used for controlling the opening and closing of the sampling switch;
the enabling control module is used for generating at least one enabling control signal, controlling the voltage generation module to be switched on and off by the enabling control signal and controlling the refreshing control module to generate the refreshing control signal;
when the enabling control signal controls the voltage generation module to be started and the voltage signal of the voltage generation module is stable, the refreshing control signal controls the sampling switch to be closed so as to connect the holding module with the voltage generation module, and the holding module samples the voltage signal; when the holding module finishes sampling, the refreshing control signal controls the sampling switch to be disconnected so as to cut off the connection between the holding module and the voltage generating module, and the enabling control signal controls the voltage generating module to be closed.
2. The voltage generation circuit of claim 1, wherein the enable control signal controls the voltage generation module and the refresh control module to be turned on and off periodically.
3. The voltage generation circuit of claim 2, wherein the time of one cycle is 20 to 80 milliseconds.
4. The voltage generation circuit of claim 1, wherein the enable control module comprises a ring oscillator circuit.
5. The voltage generation circuit of claim 4, wherein the duty cycle of the enable control signal is controlled by controlling a charge and discharge current of the ring oscillator circuit.
6. The voltage generation circuit of claim 4, wherein the period of the ring oscillator circuit is in the range of 20-80 milliseconds.
7. The voltage generation circuit of claim 4, wherein the ring oscillator circuit is formed by an odd number of inverters connected in series with output terminals connected end to end with input terminals.
8. The voltage generation circuit of claim 7, wherein a capacitor is provided at an output of at least one of the inverters.
9. The voltage generation circuit of claim 4, wherein the enable control module further comprises an in-phase buffer circuit, an output terminal of the ring oscillator circuit is connected to an input terminal of the in-phase buffer circuit, and an output terminal of the in-phase buffer circuit outputs the enable control signal.
10. The voltage generation circuit of claim 1, wherein the refresh control module comprises:
the first delay circuit delays the enabling control signal and outputs a first delay signal;
the refresh control signal generation circuit comprises a second delay circuit and an AND gate circuit, wherein the second delay circuit is an inverse delay circuit, the first delay signal is used as an input signal of the second delay circuit and the AND gate circuit, the second delay circuit outputs a second delay signal, the second delay signal is used as the other input signal of the AND gate circuit, and the output signal of the AND gate circuit is used as the refresh control signal.
11. The voltage generation circuit of claim 10, wherein the first delay circuit is formed by connecting an even number of inverters in series, and a capacitor is provided at an output terminal of at least one of the inverters.
12. The voltage generation circuit of claim 10, wherein the first delay circuit is configured to: when the voltage signal of the voltage generation module is stable, the first delay circuit outputs the first delay signal.
13. The voltage generation circuit of claim 10, wherein the second delay circuit is formed by an odd number of inverters connected in series.
14. The voltage generation circuit of claim 13, wherein a capacitor is provided at an output of at least one of the inverters.
15. The voltage generating circuit of claim 1, wherein the holding module comprises at least one capacitor.
16. The voltage generation circuit of claim 1, wherein a buffer module is provided at an output of the voltage generation circuit.
17. The voltage generation circuit of claim 1, further comprising:
the comparison module is provided with an input end and an output end, the input end is connected with the output end of the voltage generation module and receives the voltage signal, the comparison module can compare the voltage signal with a preset value, and the output end of the comparison module outputs a comparison result signal;
and the AND gate module is provided with an input end and an output end, the input end is respectively connected with the enabling control module and the comparison module and receives the enabling control signal and the comparison result signal, the output end is connected with the refreshing control module, and the refreshing control module generates the refreshing control signal according to the output signal of the AND gate module.
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| CN201911293386.9A CN112987840A (en) | 2019-12-16 | 2019-12-16 | Voltage generating circuit |
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| CN103941793A (en) * | 2013-01-23 | 2014-07-23 | 精工电子有限公司 | Constant voltage circuit and analog electronic clock |
| CN107659151A (en) * | 2017-04-24 | 2018-02-02 | 深圳市华芯邦科技有限公司 | Buck load current detection circuits and method without external sampling resistance |
| CN109582073A (en) * | 2019-01-14 | 2019-04-05 | 南开大学 | A kind of programmable band-gap reference circuit of half period capacitance ratio |
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2019
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| CN102915071A (en) * | 2012-10-23 | 2013-02-06 | 南京航空航天大学 | Low-voltage low-power-consumption switching current sampling holding circuit oriented to mixed signal processing |
| CN103941793A (en) * | 2013-01-23 | 2014-07-23 | 精工电子有限公司 | Constant voltage circuit and analog electronic clock |
| CN107659151A (en) * | 2017-04-24 | 2018-02-02 | 深圳市华芯邦科技有限公司 | Buck load current detection circuits and method without external sampling resistance |
| CN109582073A (en) * | 2019-01-14 | 2019-04-05 | 南开大学 | A kind of programmable band-gap reference circuit of half period capacitance ratio |
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Application publication date: 20210618 |