CN112968012B

CN112968012B - Fan-out type chip stacking packaging structure and manufacturing method thereof

Info

Publication number: CN112968012B
Application number: CN202110135105.8A
Authority: CN
Inventors: 曾心如; 陈鹏; 周厚德
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-02-01
Filing date: 2021-02-01
Publication date: 2022-09-09
Anticipated expiration: 2041-02-01
Also published as: CN115274598A; CN112968012A

Abstract

The application provides a fan-out chip stack package structure and a manufacturing method thereof. The fan-out chip stacking packaging structure comprises a stacking structure, a rewiring structure and a plurality of bump structures. The stacking structure comprises a plurality of stacking units which are sequentially stacked, the rewiring structure is arranged on one surface of the stacking structure, and the bump structures are arranged on the surface of one side, far away from the stacking units, of the rewiring structure. In one embodiment, the chips disposed within the stacked unit may have a plurality of rows of I/O ports, which may be electrically connected to a plurality of bump structures through a rewiring structure.

Description

Fan-out type chip stacking packaging structure and manufacturing method thereof

Technical Field

The invention relates to a packaging structure. And more particularly, to a fan-out die stack package structure and a method of manufacturing the same.

Background

Currently, as the technology of the memory industry matures, the miniaturization of the memory package structure becomes a great trend. As the feature size of the chip unit inside the package structure gradually approaches the lower limit, the demand for the chip packaging technology is increasing in order to achieve miniaturization of the package structure.

In the chip stacking and packaging process in the prior art, a routing process and a Through Silicon Via (TSV) process are mainly adopted, but in the face of miniaturization requirements, the two packaging processes have some problems which need to be solved urgently. For example, when a wire bonding process is used for packaging, the area of the whole packaging structure is enlarged by more than 20% due to the existence of gold fingers, and the high-frequency performance of the chipset is limited due to the relatively long conductive path of the gold wire process. In addition, the packaging process requires a long production period, and thus, more wire bonding machines are required to produce a certain number of packaging structures. Due to the limitation of the routing mode, the I/O ends can be led out of the chips in the packaging structure only in a single row, which is not beneficial to subsequent wiring operation. When the TSV process is adopted for packaging, the chip design and the chip packaging need to be matched, which has certain technical difficulty and higher cost. Because the substrate in the packaging structure needs to be provided with the line width/space with the ultra-small space, the manufacturing cost can be exponentially increased along with the reduction of the line width/space, holes need to be punched in the manufacturing process of the substrate, and the holes cannot be filled with metal in the subsequent manufacturing process, so that certain resistance can be increased, and the high-frequency performance of a product is further influenced.

The fan-out package popular in recent years not only can effectively reduce the size of the package structure, but also a redistribution layer (RDL) therein can bring higher performance to the package structure. Therefore, the application of the fan-out package structure to the memory field becomes a hot spot of the fan-out package application.

It should be appreciated that this background section is intended in part to provide a useful background for understanding the present technology and is not intended to imply that such matter has necessarily been prior art, as is known to those skilled in the art, prior to the present application.

Disclosure of Invention

Embodiments of the present disclosure provide a fan-out die stack package structure, including: the packaging structure comprises a stacking structure, a rewiring structure and a plurality of bump structures, wherein the stacking structure comprises a plurality of stacking units which are sequentially stacked; the rewiring structure is arranged on one surface of the stacking structure; the plurality of bump structures are arranged on the surface of one side of the rewiring structure far away from the stacking structure.

According to one embodiment of the present disclosure, an adhesive layer is provided between any adjacent two of the plurality of stacked units.

According to one embodiment of the present disclosure, a plurality of stacking units includes: the image forming apparatus includes a first stacking unit, and one or more second stacking units disposed on one surface of the first stacking unit.

According to one embodiment of the present disclosure, a first stacking unit includes: the chip package comprises a first substrate with a groove, a first chip arranged in the groove, and a first rewiring layer arranged on the surface of one side of the first substrate with the groove.

According to one embodiment of the present disclosure, the first re-wiring layer includes: the first dielectric layer is arranged on at least part of the surface of the first chip which is not surrounded by the groove and the surface of one side of the first substrate with the groove; and the first metal routing is arranged on the surface of one side of the first dielectric layer far away from the first substrate.

According to one embodiment of the present disclosure, a depth of the groove is less than a thickness of the first substrate.

According to one embodiment of the present disclosure, the thickness of the first chip is the same as the depth of the groove.

According to an embodiment of the present disclosure, the second stacking unit includes: a second substrate, a second chip, and a second rewiring layer, wherein the second substrate has a first face and a second face that are opposed, and has an opening and at least one via hole that extend from the first face to the second face; the second chip is arranged in the opening; the second rewiring layer is disposed on at least one of the first surface and the second surface and electrically connected to the second chip.

According to one embodiment of the present disclosure, the second rewiring layer includes: the second dielectric layer is arranged on at least one of the first surface and the second surface; and the second metal routing is arranged on the surface of one side of the second dielectric layer far away from the second substrate.

According to one embodiment of the present disclosure, the thickness of the second chip is the same as the depth of the opening.

According to one embodiment of the present disclosure, the second rewiring layer is electrically connected to at least one of the first rewiring layer, the second rewiring layer, and the rewiring structure through at least one via hole.

According to one embodiment of the present disclosure, the first substrate and the second substrate are made of the same material and are one of silicon-based, ceramic, glass, or plastic package material.

According to one embodiment of the present disclosure, the first dielectric layer and the second dielectric layer are made of the same material and are made of an insulating material.

According to one embodiment of the present disclosure, edges of the first chip and the second chip are aligned in the stacking direction.

According to one embodiment of the present disclosure, at least one of the first chip and the second chip has a plurality of rows of I/O terminals.

According to one embodiment of the present disclosure, the bump structure is a solder ball or a solder column.

According to one embodiment of the present disclosure, the first chip and/or the second chip is a NAND die.

According to one embodiment of the present disclosure, the first stacking unit and/or the second stacking unit further includes a third chip electrically connected to the first metal trace of the first stacking unit and/or the second metal trace of the second stacking unit.

According to one embodiment of the present disclosure, the first stacking unit and/or the second stacking unit further include an electronic component electrically connected to the first metal trace of the first stacking unit and/or the second metal trace of the second stacking unit.

According to one embodiment of the present disclosure, the electronic element includes one of a resistor, a capacitor, or a transistor. Embodiments of the present disclosure also provide a method for manufacturing a fan-out die stack package structure, the method including: forming a stacked structure by stacking a second stacking unit on the first stacking unit; forming a rewiring structure on a surface of a side of the stacking structure away from the first stacking unit; and forming a plurality of bump structures on the surface of the side of the rewiring structure far away from the stacking structure.

According to an embodiment of the present disclosure, the method further comprises: an adhesive layer is disposed between adjacent two stacked units in the stacked structure.

According to an embodiment of the present disclosure, the method further includes the step of forming a first stacking unit including: forming a groove on a first substrate, and arranging a first chip in the groove; and forming a first rewiring layer on at least part of the surface of the first chip not surrounded by the groove and the surface of the first substrate with the groove.

According to one embodiment of the present disclosure, the step of forming the first re-wiring layer includes: forming a first dielectric layer on at least part of the surface of the first chip which is not surrounded by the groove and the surface of the first substrate with the groove; and forming a first metal wire on the surface of one side of the first dielectric layer far away from the first substrate.

According to one embodiment of the present disclosure, a depth of the groove formed on the first substrate is smaller than a thickness of the first substrate.

According to one embodiment of the present disclosure, a thickness of the first chip disposed in the groove is the same as a depth of the groove.

According to an embodiment of the present disclosure, the method further comprises the step of forming a first stacking unit comprising: forming a bonding layer on the bearing sheet; disposing a first chip on the bonding layer; forming a first substrate on one side of the bonding layer far away from the bearing sheet, and enabling the first substrate to wrap the first chip; the carrier sheet and the bonding layer are removed, and a first rewiring layer is formed on one side of the first substrate, where the first chip is exposed.

According to one embodiment of the present disclosure, the step of forming the first re-wiring layer includes: forming a first dielectric layer on one side of the first substrate, which exposes the first chip; and forming a first metal wire on the surface of one side of the first dielectric layer far away from the first substrate.

According to an embodiment of the present disclosure, the method further includes a step of forming at least one second stacked unit, the step of forming each second stacked unit including: forming an opening and at least one communication hole extending from the first surface to a second surface opposite to the first surface, respectively, on the first surface of the second substrate, and disposing the second chip in the opening; and forming a second rewiring layer on surfaces of the second chip and a side of the second substrate away from the first stacking unit.

According to one embodiment of the present disclosure, the step of forming the second rewiring layer includes: a second dielectric layer is arranged on the surfaces of the second chip and the second substrate, which are far away from one side of the first stacking unit; and forming a second metal wire on the surface of one side of the second dielectric layer far away from the second substrate.

According to one embodiment of the present disclosure, a thickness of the second chip disposed in the opening is the same as a thickness of the second substrate.

According to one embodiment of the present disclosure, the first substrate and the second substrate are made of the same material and are made of one of silicon base, ceramic, glass or plastic package material.

According to an embodiment of the present disclosure, the method further comprises: filling metal in at least one of the via holes, and forming a conductive metal pillar or a conductive bridge to electrically connect the second rewiring layer with at least one of the first rewiring layer, the second rewiring layer, and the rewiring structure.

According to an embodiment of the present disclosure, the method further comprises: edges of the first chip and the second chip are aligned in the stacking direction.

According to an embodiment of the present disclosure, the method further comprises: multiple rows of I/O ports are led out from the first chip and/or the second chip, and at least a part of the I/O ports are electrically connected to the bump structures.

According to an embodiment of the present disclosure, the method further comprises: and arranging the third chip in the first stacking unit and/or the second stacking unit, and electrically connecting the third chip with the first metal routing of the first stacking unit and/or the second metal routing of the second stacking unit.

According to an embodiment of the present disclosure, the method further comprises: the electronic element is arranged in the first stacking unit and/or the second stacking unit, and is electrically connected with the first metal wire of the first stacking unit and/or the second metal wire of the second stacking unit.

According to one embodiment of the present disclosure, the electronic element includes one of a resistor, a capacitor, or a transistor.

Embodiments of the present disclosure also provide a memory including any of the fan-out die stack package structures described above.

Compared with the prior art, the fan-out chip stack package structure provided by the embodiment of the application has at least one or more of the following advantages:

1. the traditional gold wire making mode is replaced by the rewiring layer, the overall line distance can be shortened by more than 40%, the signal transmission speed can be effectively improved, and the high-frequency performance of the packaging structure is improved.

2. Because the chip is not limited by a routing process, a single-layer chip can lead out a plurality of parallel I/O ends, and the wiring is convenient to carry out according to the subsequent actual requirement.

3. Can adopt the copper line to replace the gold thread, not only reduce manufacturing cost, can also reduce parasitic resistance and inductance.

4. The processing speed is far higher than that of the wire bonding process, so that the production period of product processing is shortened.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of the non-limiting embodiments made with reference to the following drawings:

fig. 1 shows a schematic block diagram of a fan-out chip stack package structure according to an embodiment of the present application;

fig. 2 shows a schematic block diagram of a first stacking unit according to an embodiment of the present disclosure;

fig. 3 shows a schematic block diagram of a second stacking unit according to an embodiment of the present disclosure;

FIG. 4 illustrates a top view of a chip in a stacked unit, according to one embodiment of the present disclosure;

FIG. 5 shows a flow diagram of a method for fabricating a fan-out die stack package structure according to one embodiment of the present disclosure;

fig. 6A-6D show process step diagrams for fabricating a fan-out die stack package structure, according to one embodiment of the present disclosure.

Fig. 7A-7D show schematic diagrams of process steps for fabricating a fan-out die stack package structure, according to another embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in this specification, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not represent any limitation on the features. Thus, a first electrode discussed below may also be referred to as a second electrode without departing from the teachings of the present application. And vice versa.

In the drawings, the thickness, size, and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. For example, the thickness of the conductive layer and the thickness of the insulating layer are not in proportion in actual production. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that the terms "comprises," "comprising," "has," "having," "includes" and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. In an exemplary embodiment, when the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, when the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 shows a schematic block diagram of a fan-out chip stack package structure according to an embodiment of the present application. The fan-out die stack package 100 includes: a stack structure 110, a redistribution structure 120, and a plurality of bump structures 130.

As shown in fig. 1, the stack structure 110 includes: a first stacking unit 111 and at least one second stacking unit 112 stacked. The stack structure 110 is exemplarily shown in fig. 1 to include one first stack unit 111 and seven second stack units 112.

The rewiring structure 120 is located on a surface of the stacking structure 110 on a side away from the first stacking unit 111, and the I/O terminals of the plurality of chips in the stacking structure 110 may be electrically connected to the plurality of bump structures 130 through the rewiring structure 120.

The plurality of bump structures 130 are arranged in an array on the redistribution structure 120 and electrically connected to the redistribution layer in the redistribution structure 120, and at the same time, the plurality of bump structures 130 serve as circuit I/O terminals of the package structure, which can be used to electrically connect with other printed circuit boards to form a corresponding electronic device (e.g., a memory device). The bump structure 130 may be a solder ball or a solder column, and the material of the bump structure may include, but is not limited to, tin-based alloy or tin. The bump structure 130 can greatly improve the transmission rate and the signal quality of the chip.

In addition, an adhesive layer 140 is disposed between any two adjacent stacked units in the stacked structure 110 for interconnecting the stacked units. The adhesive layer 140 can be formed by, for example, a high polymer material, which can be various types of epoxy resin, novolac epoxy resin, or other adhesive resin, and is doped with an adhesive assistant, a cross-linking agent, etc. according to actual process requirements, and has high adhesive strength, chemical resistance, acid and alkali resistance, and high temperature resistance. Illustratively, the thickness of the adhesive layer 140 is 10 um.

The fan-out chip stacking and packaging structure formed encapsulates any number of stacking units into a whole according to actual requirements, so that the area of the packaging structure can be effectively reduced, and the volume of a packaging body is also reduced.

The specific structure of each component of the stacked structure in the fan-out type chip stacked package structure shown in fig. 1 will be described in detail with reference to fig. 2 and 3.

Fig. 2 illustrates a schematic configuration diagram of a first stacking unit according to an embodiment of the present disclosure. The first stacking unit 111 includes: a first substrate 1111, a first chip 1112, and a first redistribution layer 1115.

The first substrate 1111 has at least one recess 10a having a depth smaller than the thickness of the first substrate 1111 for receiving the first chip 1112, wherein the thickness of the first chip 1112 is substantially the same as the depth of the recess 10a, and the shape of the recess 10a may be designed according to the shape of the first chip 112 it receives. Schematically, the first chip 1112 is mounted in the groove 10 a. Since the thickness of the first chip 1112 is substantially the same as the depth of the groove 10a, the surface of the first chip 1112 not surrounded by the groove 10a is flush with the surface of the side of the first substrate 1111 having the groove 10 a. The first substrate 1111 can protect the first chip 1112 from the external environment; resistance to external moisture, solvents, and shock; electrically insulating the chip from the external environment; good installation performance; thermal shock and mechanical vibration during installation are resisted; thermal diffusion, etc. The first substrate 1111 may be an inorganic substrate or an organic substrate having insulation properties, for example, the first substrate 1111 may be a silicon-based material, a ceramic material, a glass material, or a molding compound material, and specifically, the silicon-based material may be silicon, silicon germanium, porous silicon, microcrystalline silicon, or other compound semiconductor materials heteroepitaxial with silicon as a substrate, but is not limited thereto; the molding compound material includes polymers including resins and polyimides, and may be an Epoxy Molding Compound (EMC), but is not limited thereto, and more specifically, the molding compound material may be one or a combination of an epoxy resin, a novolac epoxy resin, an o-cresol formaldehyde epoxy resin, and the like, but is not limited thereto.

A first heavy wiring layer 1115 is provided over the upper surface of the first chip 1112 and the surface of the first substrate 1111 on the side having the groove 10 a. First redistribution layer 1115 includes first dielectric layer 1113 and first metal trace 1114 for rerouting an I/O port of first chip 1112 and electrically connecting to at least one of other stacked cells or redistribution structures 120.

The first dielectric layer 1113 can effectively retard electron migration and prevent corrosion, and can also effectively shield moisture and increase the moisture resistance of the component, and in addition, the first dielectric layer 1113 can also absorb the internal stress generated by the difference of the thermal expansion coefficients between the substrate and the lead frame, thereby effectively reducing the open circuit caused by the internal stress, and in the subsequent rewiring treatment, the first dielectric layer 1113 can also protect the chip from being damaged in the photoetching operation process. The first dielectric layer 1113 is made of an insulating material, and includes one or a combination of two or more of epoxy resin, silica gel, Polyimide (PI), PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, but is not limited thereto. Illustratively, the first dielectric layer 1113 is a Polyimide (PI) layer.

A first metal trace 1114 is disposed on a surface of the first dielectric layer 1113 on a side away from the first substrate 1111, and is used for extracting an I/O port of the first chip 1112 and performing a redistribution. The material of the first metal trace 1114 includes one or a combination of copper, nickel, titanium tungsten alloy, etc., but is not limited thereto.

Fig. 3 shows a schematic block diagram of a second stacking unit according to an embodiment of the present disclosure. The second stacking unit 112 includes: a second substrate 1121, a second chip 1122, and a second redistribution layer 1125.

The second substrate 1121 has a first face and a second face opposing in the thickness direction, and has an opening 20a extending from the first face to the second face and at least one communication hole 20 b; the second chip 1122 is disposed in the opening 20a, wherein the shape and/or size of the opening 20a can be designed according to the shape of the second chip 1122 received therein, and the thickness of the second chip 1122 is substantially the same as the depth of the opening 20a, so that the upper surface and the lower surface of the second chip 1122 are flush with the upper surface and the lower surface of the second substrate 1121, respectively. The position layout of the communication holes can be determined according to the distribution condition of the chips or the layout condition of the rewiring layer, so that the wiring density of the rewiring layer can be improved, and the layout of metal wires in the rewiring can be more reasonable. A conductive metal pillar or a conductive bridge obtained by filling metal is provided in at least one of the connection holes 20b for realizing connection of electrical signals between the respective stacked units.

The second substrate 1121 can protect the second chip 1122 from the external environment; resistance to external moisture, solvents, and shock; electrically insulating the chip from the external environment; good installation performance; thermal shock and mechanical vibration during installation are resisted; thermal diffusion, etc. The second substrate 1121 may be an inorganic substrate or an organic substrate, for example, the material of the second substrate 1121 may be silicon-based, ceramic, glass, or a plastic package material, and the like, and specifically, the silicon-based material may be silicon, silicon germanium, porous silicon, microcrystalline silicon, and other compound semiconductor materials heteroepitaxial with silicon as a substrate, and the like, but is not limited thereto; the molding compound material may be an Epoxy Molding Compound (EMC), but is not limited thereto, and more specifically, the molding compound material may be one or a combination of an epoxy resin, a novolac epoxy resin, an o-cresol formaldehyde epoxy resin, and the like, but is not limited thereto.

A second redistribution layer 1125 is disposed on at least one of the first side and the second side of the second substrate 1121 (for example, on the first side of the second substrate away from the first stacking unit 111), and the second redistribution layer 1125 includes a second dielectric layer 1123 and a second metal routing 1124.

The second dielectric layer 1123 is disposed on at least one of the first surface and the second surface of the second substrate (for example, on the first surface of the second substrate 1121 that is away from the first stacking unit 111), the second dielectric layer 1123 can effectively block electron migration and prevent corrosion, and can also effectively block moisture and increase the moisture resistance of the device, and in addition, the second dielectric layer 1123 can also absorb internal stress generated by the difference of thermal expansion coefficients between the substrate and the lead frame, so that the open circuit caused by the internal stress can be effectively reduced, and in the subsequent rewiring process, the second dielectric layer 1123 can also protect the chip from being damaged during the photolithography operation. The second dielectric layer 1123 is made of an insulating material, and includes one or a combination of two or more of epoxy resin, silica gel, Polyimide (PI), PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, but is not limited thereto. Illustratively, the second dielectric layer 1123 is a Polyimide (PI) layer.

The second metal trace 1124 is disposed on a surface of the second dielectric layer 1123 on a side away from the second substrate 1121, and the second metal trace 1124 is electrically connected to at least one of the first stacked unit 111, the at least one second stacked unit 112, and the redistribution structure 120 through at least one via hole 20b, and leads out an I/O port of the second chip 1122 for redistribution. The material of the second metal trace 1124 includes one or a combination of copper, nickel, titanium tungsten alloy, etc., but is not limited thereto.

It should be noted that the first chip 1112 and the second chip 1122 in the above example may be NAND chips, and the first chip 1112 and one or more second chips 1122 may be a plurality of NAND chips of the same type/specification, and the plurality of NAND chips may be packaged in a fan-out type chip-on-chip package structure, so as to form a NAND memory. It will be appreciated that the stack structure 110 may determine the number of stack units it contains based on, for example, the storage capacity requirements of the NAND memory and/or the storage capacity of a single NAND die.

It should be noted that the first stack unit 111/the second stack unit 112 of the above example may further include a third chip (e.g., a controller, not shown in the figure) different from the first chip 1112/the second chip 1122, and the third chip may be a chip having a completely different function from the first chip 1112/the second chip 1122, for example, the first chip 1112/the second chip 1122 may be a memory wafer, and the third chip may be a memory controller for controlling one or more memory wafers. The third chip may be fixed in the first substrate 1111 of the first chip 1112/the second substrate 1121 of the second chip 1122, and the third chip may be electrically connected with the first metal trace 1114 of the first stacking unit 111/the second metal trace 1124 of the second stacking unit 112 through its I/O terminal, thereby forming a product implementing a corresponding system function.

It should be noted that the first stacked unit 111/the second stacked unit 112 of the above example may further include an electronic component, for example, one of a resistor, a capacitor, or a transistor. The electronic component may be fixed in the first substrate 1111 of the first chip 1112/the second substrate 1121 of the second chip 1122, and the electronic component may be electrically connected with the first metal wiring 1114 of the first stack unit 111/the second metal wiring 1124 of the second stack unit 112 through its I/O terminal, thereby forming a product implementing a corresponding system function.

Fig. 4 illustrates a top view of a chip disposed in a stacked unit, according to one embodiment of the present disclosure.

As shown in fig. 4, the redistribution layer according to this embodiment may enable multiple rows of I/O pins 401 to be disposed on the substrate of the chip in the stacked unit for the subsequent routing operation, unlike the chip using the wire bonding process, which is limited by the width and the pitch of the metal lines and only can lead out a single row of I/O pins. Specifically, at least a portion of the I/O terminal pins of at least one chip in the package structure may be interconnected through the first and second metal traces 1114 and 1124 and the at least one via hole 20b as shown in fig. 2 and 3, and at least a portion of the I/O terminals may be led out to the re-routing structure 120 disposed on the stacked structure 110, and then connected to the plurality of bump structures 130 through the re-routing structure 120 to be electrically connected to other printed circuit boards, thereby implementing operations, such as an erase operation, a write operation, or a read operation, on the chip in the package structure according to different requirements.

Fig. 5 illustrates a flow diagram of a method 500 for fabricating a fan-out die stack package structure according to one embodiment of the present disclosure. As shown in fig. 5, the method 500 may include:

step S1: forming a first stacking unit;

step S2: forming at least one second stacking unit on one surface of the first stacking unit to form a stacking structure with the first stacking unit;

step S3 of forming a rewiring structure on a surface of a side of the stack structure away from the first stack unit; and

in step S4, a plurality of solder balls are formed on the surface of the redistribution structure on the side away from the stacked structure.

The specific process steps S1-S4 of the various parts of the fan-out die stack package structure according to one embodiment will be described in detail below with reference to fig. 6A-6D. For ease of understanding, the NAND memory chip package structure is hereinafter described as an example, but the present application is not limited thereto. It will be appreciated by those skilled in the art that the present application is also applicable to other memories having similar structures.

Step S1

Fig. 6A shows a specific process example for implementing step S1 according to an embodiment of the present application. As shown in fig. 6A, first, in step S601, a groove 10a is formed in the first substrate 1111, wherein the depth of the groove 10a is smaller than the thickness of the first substrate 1111. Next, in step S602, the first chip 1112 is disposed in the groove 10a, specifically, the first chip 1112 is disposed in the groove 10a in a mounting manner, and the depth of the groove 10a is the same as the thickness of the first chip 1112, so that the surface of the first chip 1112 not surrounded by the groove 10a is flush with the surface of the first substrate 1111 having the groove 10a, wherein the thickness of the first chip 1112 may be 25um to 50um, for example.

Next, a first redistribution layer 1115 is formed on the upper surface of the first chip and the upper surface of the first substrate. The first redistribution layer 1115 includes a first dielectric layer 1113 and a first metal trace 1114. Specifically, first, in step S603, a first dielectric layer 1113 is formed on at least a part of the surface of the first chip 1112 not surrounded by the groove 10a and the surface of the first substrate 1111 on the side having the groove 10 a. Specifically, the first dielectric layer 1113 is made of an insulating material, and includes one or a combination of two or more selected from the group consisting of epoxy resin, silica gel, Polyimide (PI), PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, but is not limited thereto. Illustratively, the first dielectric layer 1113 is a Polyimide (PI) layer. Then, in step S604, a first metal trace 1114 is formed on a surface of the first dielectric layer 1113 on a side away from the first substrate 1111, so as to form a complete first stacked unit 111. Specifically, in the process of forming the first redistribution layer 1115, a seed layer is deposited on an insulating dielectric layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like, a layer of photoresist is coated on the structure, the structure is patterned through a photoetching device, the electroplated metal is used as RDL, the photoresist is removed, and the seed layer is removed.

It should be noted that a third chip (e.g., a controller, not shown) may also be disposed in the first substrate 1111 and electrically connected to the first metal traces 1114 of the first stacking unit 111. In addition, an electronic component (for example, one of a resistor, a capacitor, or a transistor, not shown in the figure) may be disposed in the first substrate 1111 and electrically connected to the first metal trace 1114 of the first stacked unit 111.

Step S2

Fig. 6B shows a specific process example for implementing step S2 according to an embodiment of the present application.

First, in step S605, an adhesive layer 140 is formed on the upper surface of the first stacked unit for interconnecting the next stacked unit. Subsequently in step S606, a second substrate 1121 is formed on the adhesive layer 140, wherein the second substrate 1121 has a first face and a second face opposite to each other. An opening 20a and at least one connection hole 20b extending from the first face to the second face are formed on the second substrate 1121, respectively. The second chip 1122 is disposed in the opening 20a of the second substrate 1121, and specifically, the thickness of the second chip 1122 is the same as that of the second substrate 1121 so that the upper surface and the lower surface of the second chip 1122 are flush with the upper surface and the lower surface of the second substrate 1121, respectively. The thickness of the second chip 1122 can be 25um-50um, for example.

Next, a second rewiring layer 1125 is formed on at least one of the first and second surfaces of the second substrate 1121. The second redistribution layer 1125 includes a second dielectric layer 1123 and a second metal trace 1124. Specifically, in step S607, a second dielectric layer 1123 is formed on the upper surface of the second chip 1122 and the upper surface of the second substrate 1121, wherein the material of the second dielectric layer 1123 is an insulating material, including one or a combination of two or more selected from the group consisting of epoxy resin, silica gel, Polyimide (PI), PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, but not limited thereto. Illustratively, the second dielectric layer 1123 is a Polyimide (PI) layer. Finally, in step S608, a second metal trace 1124 is disposed on a surface of the second dielectric layer 1123 on a side away from the second substrate 1121.

A conductive metal pillar or a conductive bridge is formed by filling a metal in at least one of the connection holes 20b so that the second re-wiring layer 1125 electrically connects the second chip 1122 with a chip in an adjacent stack unit through at least one of the connection holes 20b, that is, the second re-wiring layer 1125 electrically connects at least one of the first stack unit 111, the second stack unit 112, and the re-wiring structure 120 through at least one of the connection holes 20 b. Then, in step S609, a thickness adhesive layer 140 is formed on the second rewiring layer 1125 for interconnection with the next stacked unit. In step S610, the above steps S606 to S610 are repeated to form a required number of second stacking units 112.

With the arrangement, the bonding pads (not shown) of the chips in the stacking unit can be moved outwards, so that no circuit can be arranged below the positions of the chips, and the electric connection of the chips in the stacking unit can be realized by adopting the TSV technology.

It should be noted that a third chip (e.g., a controller, not shown) may also be disposed in the second substrate 1121, and the third chip is electrically connected to the second metal trace 1124 of the second stacking unit 112. In addition, an electronic component (e.g., one of a resistor, a capacitor, or a transistor, not shown) may be disposed in the second substrate 1121, and electrically connected to the second metal trace 1124 of the second stacked unit 112.

Step S3

Fig. 6C shows a specific process example for implementing step S3 according to an embodiment of the present application. As shown in fig. 6C, in step S611, the rewiring structure 120 is formed on the surface of the formed stack structure 110 on the side away from the first stack unit 111. Specifically, the re-wiring structure 120 is electrically connected to the I/O terminal of at least one chip in the stack unit 110 through at least one communication hole 20b as necessary.

Step S4

Fig. 6D shows a specific process example for implementing step S4 according to an embodiment of the present application. As shown in fig. 6D, in step S619, a plurality of bump structures 130 are disposed on a surface of the redistribution structure 120 on a side away from the formed stacked structure to form a complete fan-out chip stacked package structure. Specifically, a plurality of bump structures 130 are arranged in an array on the rewiring structure 120 and electrically connected to the rewiring layer in the rewiring structure 120. The bump structure 130 may be a solder ball or a solder column, and the material thereof may include, but is not limited to, tin-based alloy or tin.

The specific process steps S1-S4 of the respective parts of the fan-out die stack package structure according to another embodiment will be described in detail below with reference to fig. 7A-7D. For ease of understanding, the NAND memory chip package structure is hereinafter described as an example, but the present application is not limited thereto. It will be appreciated by those skilled in the art that the present application is also applicable to other memories having similar structures.

Step S1

Fig. 7A shows a specific process example for implementing step S1 according to an embodiment of the present application. As shown in fig. 7A, first, in step S701, a bonding layer 712 is formed on one surface of a carrier sheet 711. The supporting sheet 711 is an insulating sheet, such as a quartz sheet, a glass sheet, a metal sheet, a silicon wafer, a ceramic sheet, or the like, but is not limited thereto; the bonding layer 712 may be a DAF film (die attach film), a laminate tape or a dry film, and the material thereof may be a release adhesive, a UV adhesive or a laser debonding adhesive, specifically, may be various types of epoxy resin, novolac epoxy resin, or other adhesive resin, and may be doped with an adhesion promoter, a cross-linking agent, etc. according to the actual process requirements, and may also be PSA (pressure sensitive adhesive), Polybenzoxazole (PBO), benzocyclobutene (BCB), etc., but is not limited thereto. Bonding layer 712 combines adhesive strength, chemical resistance, acid and alkali resistance, and high temperature resistance. The thickness of the bonding layer 712 is not likely to be too small, since too small a thickness may affect the bonding effect, while too large a thickness may cause a waste of material.

Then in step S702, the first chip 1112 is disposed on the formed bonding layer 712, specifically, the device side of the first chip 1112 is mounted and disposed on the bonding layer 712 facing the bonding layer 712; in step S703, a first substrate 1111 surrounding the first chip 1112 except five surfaces of the device side is formed on the bonding layer 712 on which the first chip 1112 is provided, and a support layer 713 is provided on the first substrate 1111 formed after the film lamination process. Wherein, the film pressing treatment can be encapsulation by using an electric heating mold film pressing process; the supporting layer 713 plays a role of supporting in the subsequent steps, and prevents the first substrate 1111 and the first chip 1112, which are too thin, from being broken, thereby providing assurance for the subsequent processing steps. In step S704, the carrier 711 is removed, and a first dielectric layer 1113 is formed on the surface of the side where the carrier 711 is located. Specifically, the carrier sheet 711 is separated from the first substrate 1111 thereon by using a laser or thermal peeling method, and the bonding layer 712 is removed; the first dielectric layer 1113 is made of an insulating material, and includes one or a combination of two or more selected from the group consisting of epoxy resin, silica gel, Polyimide (PI), PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, but is not limited thereto. Illustratively, the first dielectric layer 1113 is a Polyimide (PI) layer.

Finally, in step S705, a first metal trace 1114 is formed on a surface of the first dielectric layer 1113 on a side away from the first substrate 1111, so as to form a complete first stacked unit. And the first dielectric layer 1113 and the first metal trace 1114 constitute a first redistribution layer 1115.

Step S2

Fig. 7B shows a specific process example for implementing step S2 according to an embodiment of the present application. As shown in fig. 7B, first, in step S706, an adhesive layer 140 is formed on the first redistribution layer 1115 for interconnection with the next stacked unit. In step S707, a second substrate 1121 having opposite first and second surfaces is formed on the adhesive layer 140, and an opening 20a and at least one connection hole 20b extending from the first surface to the second surface are formed on the second substrate 1121 by a photolithography process, respectively. And the second chip 1122 is disposed in the opening 20a of the second substrate 1121, and specifically, the thickness of the second chip 1122 is the same as that of the second substrate 1121 so that the upper surface of the second chip 1122 is flush with the upper surface of the second substrate 1121.

The photolithography process is a technique for transferring a pattern on a mask to a substrate under the action of light. The specific process comprises the following steps: ultraviolet light irradiates the surface of the substrate attached with a layer of pattern mask through the mask plate to cause the pattern mask in the exposure area to generate chemical reaction; then, the pattern mask of the exposure area or the unexposed area is dissolved and removed through a developing technology, so that the pattern on the mask plate is copied to the pattern mask, namely the area needing to be etched; finally, the pattern is transferred to the substrate by using an etching technology. In this embodiment, the pattern mask used in the photolithography process may include an electrolyte anti-reflective coating (DARC), a carbon hard mask, a bottom anti-reflective coating (BARC), and a photoresist. The etching process may be dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser etching, and the like. The etching process is stopped near the surface of the substrate by controlling the etching time. After the etching process is completed, the photoresist is removed by a solvent, or the photoresist is removed by an ashing process.

Then, in step S708, a second dielectric layer 1123 is formed on one of the first surface and the second surface of the second substrate 1121, and specifically, the material of the second dielectric layer 1123 is an insulating material, including one or a combination of two or more of the group consisting of epoxy resin, silica gel, Polyimide (PI), PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, but not limited thereto. Illustratively, the second dielectric layer 1123 is a Polyimide (PI) layer.

In step S709, a second metal wire 1124 is formed on a surface of the second dielectric layer 1123 on a side away from the second substrate 1121 to form a second stacked unit 112, and a conductive metal pillar or a conductive bridge is formed in at least one connection hole 20b by filling metal so that the second metal wire 1124 is electrically connected to a chip in an adjacent stacked unit through the at least one connection hole 20b, that is, the second routing layer 1125 is electrically connected to at least one of the first stacked unit 111, the second stacked unit 112 and the re-routing structure 120 through the at least one connection hole 20 b. Through the arrangement mode, the bonding pads (not shown) of the chips in the stacking unit can be moved outwards, so that no circuit is arranged below the positions of the chips, and the electric connection of the chips in the stacking unit can be realized by adopting the TSV technology.

In step S710, an adhesive layer 140 is formed on the second redistribution layer 1125 for interconnection with the next stacked unit. Then, in step S711, the above-described steps S707 to S711 are repeated to form a required number of second stack units 112.

It should be noted that a third chip (e.g., a controller, not shown) may also be disposed in the second substrate 1121, and electrically connected to the second metal trace 1124 of the second stacked unit 112. In addition, an electronic component (e.g., one of a resistor, a capacitor, or a transistor, not shown) may be disposed in the second substrate 1121 and electrically connected to the second metal trace 1124 of the second stacked unit 112.

Step S3

Fig. 7C shows a specific process example for implementing step S3 according to an embodiment of the present application. As shown in fig. 7C, in step S712, a rewiring structure is formed on a surface of the formed stack structure on a side away from the first stack unit. Specifically, the I/O terminal of at least one chip in the stacked structure 110 is electrically connected through at least one communication hole 20b as needed.

Step S4

Fig. 7D shows a specific process example for implementing step S4 according to an embodiment of the present application. As shown in fig. 7D, finally, in step S713, a plurality of bump structures 130 are disposed on a surface of the redistribution structure 120 on a side away from the formed stacked structure 110 to form a complete fan-out chip stacked package structure. Specifically, a plurality of bump structures 130 are arranged in an array on the rewiring structure 120 and electrically connected to the rewiring layer of the heavy wiring structure 120. The bump structure 130 may be a solder ball or a solder column, and the material of the bump structure may include, but is not limited to, tin-based alloy or tin.

It should be noted that additional steps may be provided before, during, and after the manufacturing method, and that some of the steps described herein may be replaced, deleted, performed in a different order, or performed in parallel for additional embodiments of the manufacturing method.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by this application is not limited to the embodiments with a specific combination of features described above, but also covers other embodiments with any combination of features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A fan-out die stack-up package structure, comprising:

a stack structure including a plurality of stack units sequentially stacked;

a rewiring structure disposed on one surface of the stack structure; and

a plurality of bump structures disposed on a surface of the redistribution structure on a side away from the stack structure,

wherein the stack unit includes a plurality of second stack units, each of the plurality of second stack units including a second repeating wiring layer and at least one communication hole, the communication holes of at least two adjacent second stack units of the plurality of second stack units being arranged in a spaced-apart manner from each other.

2. The encapsulation structure of claim 1, wherein an adhesive layer is disposed between any adjacent two of the plurality of stacked units.

3. The package structure of claim 1, wherein the plurality of stacking units further comprises a first stacking unit, wherein the plurality of second stacking units are stacked on the first stacking unit.

4. The package structure of claim 3, wherein the first stacking unit comprises:

a first substrate having a groove;

the first chip is arranged in the groove; and

and the first rewiring layer is arranged on the surface of one side of the first substrate with the groove.

5. The package structure of claim 4, wherein the first redistribution layer comprises:

a first dielectric layer disposed on at least a part of a surface of the first chip not surrounded by the groove and a surface of a side of the first substrate having the groove; and

and the first metal routing is arranged on the surface of one side of the first dielectric layer, which is far away from the first substrate.

6. The package structure of claim 4, wherein a depth of the recess is less than a thickness of the first substrate.

7. The package structure of claim 4, wherein a thickness of the first chip is the same as a depth of the recess.

8. The package structure of claim 4, wherein the second stacking unit further comprises:

a second substrate having opposing first and second faces and having an opening extending from the first face to the second face;

a second chip disposed in the opening;

wherein the second rewiring layer is disposed on at least one of the first surface and the second surface and electrically connected to the second chip.

9. The package structure of claim 8, wherein the second redistribution layer comprises:

a second dielectric layer disposed on at least one of the first side and the second side; and

and the second metal routing is arranged on the surface of one side of the second dielectric layer far away from the second substrate.

10. The package structure of claim 8, wherein a thickness of the second chip is the same as a depth of the opening.

11. The package structure of claim 8, wherein the second rewiring layer is electrically connected to at least one of the first rewiring layer, the second rewiring layer, and the rewiring structure through the at least one via.

12. The package structure of claim 8, wherein the first substrate and the second substrate are the same material and are one of silicon-based, ceramic, glass, or a molding compound material.

13. The package structure of claim 8, wherein the first dielectric layer and the second dielectric layer are the same material and are insulating materials.

14. The package structure of claim 8, wherein edges of the first and second chips are aligned in a stacking direction.

15. The package structure of claim 8, wherein at least one of the first chip and the second chip has multiple rows of I/O terminals.

16. The package structure of claim 1, wherein the bump structure is a solder ball or a solder column.

17. The package structure of claim 8, wherein the first chip and/or the second chip is a NAND die.

18. The package structure of claim 5, wherein the first stacking unit further comprises a third chip electrically connected to the first metal trace of the first stacking unit.

19. The package structure of claim 5, wherein the first stacking unit further comprises an electronic component electrically connected to the first metal trace of the first stacking unit.

20. The package structure of claim 9, wherein the second stacking unit further comprises a third chip electrically connected to the second metal trace of the second stacking unit.

21. The package structure of claim 9, wherein the second stacked unit further comprises an electronic component electrically connected to the second metal trace of the second stacked unit.

22. The package structure of claim 19 or 21, wherein the electronic component comprises one of a resistor, a capacitor, or a transistor.

23. A method for fabricating a fan-out die stack up package structure, the method comprising:

forming a stacked structure by stacking a plurality of second stacking units on the first stacking unit;

forming at least one communication hole in each of the plurality of second stack units, and arranging the communication holes of at least two adjacent second stack units in the plurality of second stack units in a spaced-apart manner from each other;

forming a rewiring structure on a surface of a side of the stacking structure away from the first stacking unit; and

forming a plurality of bump structures on a surface of a side of the rewiring structure away from the stack structure,

wherein each of the plurality of second stacked units includes a second rewiring layer.

24. The method of claim 23, further comprising: an adhesive layer is disposed between two adjacent stacking units in the stacking structure.

25. The method of claim 23, wherein the method further comprises the step of forming the first stacking unit comprising:

forming a groove on a first substrate, and arranging a first chip in the groove; and

and forming a first rewiring layer on at least part of the surface of the first chip not surrounded by the groove and the surface of the first substrate on which the groove is formed.

26. The method of claim 25, wherein forming the first redistribution layer comprises:

forming a first dielectric layer on at least part of the surface of the first chip not surrounded by the groove and the surface of the first substrate forming the groove; and

and forming a first metal wire on the surface of one side of the first dielectric layer far away from the first substrate.

27. The method of claim 23, wherein the method further comprises the step of forming the first stacking unit comprising:

forming a bonding layer on the bearing sheet;

disposing a first chip on the bonding layer;

forming a first substrate on one side of the bonding layer far away from the carrier sheet, and enabling the first substrate to wrap the first chip;

and removing the bearing sheet and the bonding layer, and forming a first rewiring layer on one side of the first substrate, which exposes the first chip.

28. The method of claim 27, wherein forming the first redistribution layer comprises:

forming a first dielectric layer on one side of the first substrate, which is exposed out of the first chip; and

29. The method of claim 25 or 27, wherein the method further comprises:

forming openings extending from a first face to a second face opposite to the first face, respectively, on the first face of the second substrate of each of the plurality of second stacking units, and disposing a second chip in the openings; and

forming the second redistribution layer on a surface of the second chip and a side of the second substrate away from the first stacking unit.

30. The method of claim 29, wherein forming the second redistribution layer comprises:

a second dielectric layer is arranged on the surfaces of the second chip and the second substrate, which are far away from one side of the first stacking unit; and

and forming a second metal routing on the surface of one side of the second dielectric layer far away from the second substrate.

31. The method of claim 29, further comprising: filling metal in the at least one via hole, and forming a conductive metal pillar or a conductive bridge to electrically connect the second rewiring layer with at least one of the first rewiring layer, the second rewiring layer, and the rewiring structure.

32. The method of claim 29, further comprising:

a plurality of rows of I/O ports are routed from the first chip and/or the second chip and at least a portion of the I/O ports are electrically connected to the plurality of bump structures.

33. The method of claim 28, wherein the method further comprises: and arranging a third chip in the first stacking unit, and electrically connecting the third chip with the first metal wire of the first stacking unit.

34. The method of claim 28, wherein the method further comprises: arranging an electronic element in the first stacking unit, and electrically connecting the electronic element with the first metal wire of the first stacking unit.

35. The method of claim 30, wherein the method further comprises: and arranging a third chip in the second stacking unit, and electrically connecting the third chip with the second metal routing of the second stacking unit.

36. The method of claim 30, wherein the method further comprises: and arranging an electronic element in the second stacking unit, and electrically connecting the electronic element with the second metal wire of the second stacking unit.

37. The method of claim 34 or 36, wherein the electronic element comprises one of a resistor, a capacitor, or a transistor.

38. The method of claim 29, wherein the first chip and/or the second chip is a NAND die.

39. A memory comprising the fan-out die stack-up package structure of any of claims 1 to 22.