CN112966459A - Quantitative evaluation method and device for single event upset protection design of block memory - Google Patents
Quantitative evaluation method and device for single event upset protection design of block memory Download PDFInfo
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Abstract
本发明提供一种块存储器单粒子翻转防护设计定量评估方法及装置。其中，该方法包括：确定SRAM型FPGA中可配置逻辑单元和块存储器内各模块的存储资源数据、对应的刷新周期以及对应的单位数据翻转率；在同一存储单元的三路中同时出现两路错误的单粒子防护效能情况下，基于不同的算法模型分别得到所述块存储器部位错误导致的错误率、所述自刷新器错误导致的错误率以及所述表决器错误导致的错误率；基于所述块存储器部位错误导致的错误率、所述自刷新器错误导致的错误率以及所述表决器错误导致的错误率，得到块存储器错误率定量评估结果。采用本发明公开的方法，能够实现单粒子防护效能进行定量评估，提高资源使用和防护效果之间的优化配置效率和可靠性。
The present invention provides a quantitative evaluation method and device for block memory single-event overturn protection design. The method includes: determining the storage resource data, the corresponding refresh cycle and the corresponding unit data inversion rate of the configurable logic unit in the SRAM-type FPGA and each module in the block memory; In the case of wrong single-event protection performance, the error rate caused by the block memory location error, the error rate caused by the self-refresher error, and the error rate caused by the voter error are obtained based on different algorithm models. The error rate caused by the block memory location error, the error rate caused by the self-refresher error, and the error rate caused by the voter error are obtained to obtain a block memory error rate quantitative evaluation result. By adopting the method disclosed in the present invention, the quantitative evaluation of the single particle protection effect can be realized, and the optimal configuration efficiency and reliability between resource use and protection effect can be improved.
Description
Technical Field
The invention relates to the technical field of computer application, in particular to a quantitative evaluation method and device for single event upset protection design of a block memory. In addition, an electronic device and a non-transitory computer readable storage medium are also related.
Background
SRAM-type FPGAs are widely used in the digital signal processing and control field due to their powerful computing power and repeatable configuration capability. The biggest advantage of the SRAM type FPGA is that configuration can be repeated infinitely many times theoretically, and the configuration speed is very fast. One of the biggest drawbacks of SRAM-type FPGAs is their volatility, disappearance of configuration data after power failure, and need to be reconfigured every time they are powered up. At present, a common solution is to design a nonvolatile memory to store configuration data, and after power is turned on, the SRAM type FPGA automatically reads the configuration data from the nonvolatile memory to perform configuration. SRAM type FPGAs are very sensitive to single event upsets, which limits their application in the aerospace field. Although the SRAM type FPGA is easily subjected to the single-particle upset effect under the irradiation of space radiation particles in aerospace application, and thus signal processing is wrong, the SRAM type FPGA is still considered to be used in aerospace application due to the strong signal processing capability of the SRAM type FPGA. Mainstream SRAM type FPGA manufacturers such as Xilinx and the like adopt a series of protection measures for protecting the single event upset effect of SRAM type FPGA. The Single Event Upset (SEU) is a phenomenon that a digital memory cell changes storage information from '0' to '1' or from '1' to '0' under the irradiation of a single high-energy particle. The storage resources of SRAM type FPGAs are mainly two major components: configurable Logic Block (CLB) and Block memory (Block RAM, BRAM).
The single event upset protection measures aiming at the configurable logic unit comprise the following steps: triple Modular Redundancy (TMR), partial reconfiguration plus timing refresh. Triple modular redundancy protection of configurable logic cells as shown in fig. 3, the original set of combinational logic processes in the configurable logic cells is divided into three paths. The input signal is divided into three independent paths, the three independent paths are respectively output after passing through a group of combinational logic and are also output independently, and the three outputs are output after passing through a majority vote device (TRV). A majority voter is a voting circuit whose output is the majority of three inputs. For example, if the three inputs are 1,1,0, respectively, the output of the majority voter is 1. Both the combinational logic and the majority voter are constructed using configurable logic cell resources. The triple modular redundancy protection can prevent errors caused by single event upset of the combinational logic or majority voter of a single path. In other words, all single point failures (failures caused by a single failure source) on the signal processing path are eliminated, and the reliability of the FPGA can be effectively improved. The majority voter in the configurable logic unit for realizing triple modular redundancy adopts a lookup table method. If the three paths of input data of the majority voter are regarded as address bits, the corresponding CLB stores 8-bit data 11101000. If the number of times of SEU occurrence in the memory cells in the CLB is increased continuously with the accumulation of time, if SEU errors occur in two or more parts (combinational logic or majority voter) in the TMR protection design, the TMR protection design can not correct the errors. For this reason, the CLB memory cells need to be refreshed periodically to avoid the accumulation of SEU errors.
At present, the SRAM-type FPGA develops a dynamic partial reconfiguration function, that is, during the normal operation of the SRAM-type FPGA, a part of configuration data is reconfigured, so that a correct code stream is continuously covered on the CLB, and the problem of reducing the protection effect of TMR due to the accumulation of SEU errors is effectively avoided. The BRAM part provides data storage of the SRAM type FPGA in the signal processing process. Since the data stored in the BRAM is read and written frequently, usually changed data, the dynamic partial reconfiguration function of the CLB cannot act on the BRAM. For the SEU protection of BRAM by TMR, in order to refresh the BRAM data of TMR at regular time to reduce the SEU error accumulation influence, the CLB resource is needed to be utilized, the data refresher is designed by self, and the data in the BRAM by TMR is refreshed at regular time, and the protection structure is called as BRAM self-refresh triple-modular redundancy single-particle protection design.
As shown in fig. 4, the BRAM resource adopts TMR design, and stores the same data in 3 BRAMs respectively. And BRAM of FPGA is usually dual port design, that is, there are A, B two ports independently accepting read address for data reading. On the data writing operation, the write enable port WEN can be controlled according to the state machine, so that A, B the data writing/writing operation or the reading/writing operation of the same address can be avoided by two ports at the same time. Therefore, after the BRAM data refreshes the data output by the OutB port, the voting result is written back to the DataA through the TRV majority voter. Control of the state machine is implemented by CLB resource configuration as COUNTER, while COUNTER is also a TMR guard and is refreshed by the CLB's dynamic partial reconfiguration function. The main functions of COUNTER are address counting, port enable control. The specific structure of the device is shown in fig. 5, the used minority voter is a voter, when the data of the voter is in minority compared with the other two paths of input data, the voter indicates that the data of the voter is wrong, and outputs an indication signal 1. CEN _ BSCNTR is an address transfer enable vote, the input of which is a three-way CNT _ TR signal, and CEN _ BSCNTR outputs a transfer instruction only when the three-way CNT _ TR signal requires an address bit transfer.
As shown in fig. 5, the COMPARATOR implements state control to avoid A, B conflict caused by simultaneous write operations on ports. ADDRA _ [0|1|2] + WEA [0|1|2] inputs are the A port address and write enable state of BRAM; the Address _ CNTR is a B port Address; error _ indication [0|1|2] is output from a few voting ports Error in the Data Voter Data _ Voter as an Error indication, that is, when one of the three paths of Data is different from the other Data, an Error indication is sent out to indicate that the Data of the path needs to be corrected, and the correct Data is output from a majority voting port VD in the Data _ Voter. The state of COMPARATOR COMPARATOR is controlled as follows: (1) when Error _ indication [0|1|2] does not receive an Error indication, WEB write enable is not started, CNT _ TR sends out an address increment operation, and an address counter jumps to the next address. (2) When Error _ indication [0|1|2] receives an Error indication, firstly comparing whether ADDRA and ADDRB are consistent, if not, indicating that the operation addresses of the port A and the port B are different at the moment, correcting the data of the port B, starting WEB enabling at the moment, and after the write operation cycle is ended, CNT _ TR sends out address increment operation to refresh the data of the next address; if ADDRA and ADDRB are consistent, but WEA write enable is not started, correction can be carried out on B port data, at the moment, WEB is started, and after the write operation cycle is finished, CNT _ TR sends out address increment operation to refresh data of the next address. Only ADDRA and ADDRB are consistent, when WEA write enable is started, WEB is closed, CNT _ TR does not send out address increment operation, and B port data correction is in a standby state. In addition to BRAM _ Block0, BRAM _ Block1, and BRAM _ Block2, other functional blocks are implemented by CLB resources, and these CLB resources will be SEU protected with TMR and partial reconfiguration plus timing refresh.
Due to the adoption of full TMR protection, single-point faults of SRUs are eliminated by any functional block, namely, an SEU occurs in one of the three functional blocks adopting TMR, and the output of wrong data by the BRAM cannot be caused. The timed refresh of CLBs and BRAMs further reduces the likelihood of SEU failures occurring in more than one of the three functional blocks of TMR, and thus, the SEU of BRAM is greatly slowed.
The conventional SEU evaluation technology mainly evaluates the on-track flip rate of a memory cell. The method comprises the steps of firstly carrying out device-level ground simulation tests on CLBs and BRAMs of the SRAM type FPGA, irradiating the device by using high-energy heavy ion sources and high-energy proton sources with different energies, recording the energy, the fluence and the error number of irradiated particles, and processing test data to obtain SEU sections of the CLBs and the BRAMs. And inputting task conditions including running time, running tracks, shielding conditions and the like, and predicting the space radiation environment on the track where the FPGA is to execute the task. And (3) inputting predicted high-energy heavy ion and high-energy proton energy spectrums and SEU cross section data of the orbit by adopting an IRPP model and the like, and obtaining the SEU turnover rate of each storage unit of the CLB and the BRAM respectively.
Although the existing BRAM module SEU protection technology of the SRAM type FPGA can effectively alleviate output data errors caused by the SEU effect in the design principle, the protection needs to consume more extra resources (CLB and BRAM), and therefore the effectiveness of the SEU protection measures needs to be quantitatively evaluated, so that designers can balance consumed resources and obtained protection effects. However, the existing method for evaluating the on-track SEU (SEU) turnover rate of the FPGA mainly adopts SEU protection measures for a single storage unit, and a single bit error cannot be transmitted to the outside. The protection measures of the BRAM are complex, and some existing evaluation methods aiming at the protection measures cannot be completely suitable for evaluating the protection effectiveness of the BRAM. Therefore, how to design an effective and reliable block memory single event upset protection design quantitative evaluation becomes an important topic of research in the field.
Disclosure of Invention
Therefore, the invention provides a quantitative evaluation method and a device for single event upset protection design of a block memory, and aims to solve the problem that in the prior art, a quantitative evaluation scheme for single event upset protection design of the block memory needs to consume more extra resources, so that the configuration efficiency is low.
The invention provides a quantitative evaluation method for single event upset protection design of a block memory, which comprises the following steps:
determining storage resource data, a corresponding refreshing period and a corresponding unit data turnover rate of each module in a configurable logic unit and a block memory in an SRAM type FPGA; the storage resource data comprises a first type of storage resource data, a second type of storage resource data and a third type of storage resource data;
obtaining an error rate caused by errors of the block memory part based on the first type of storage resource data, the refresh cycle, the unit data turnover rate and a preset first block memory error rate algorithm model;
obtaining an error rate caused by the self-refresher error based on the second type of storage resource data, the refreshing period, the unit data turnover rate and a preset second block memory error rate algorithm model;
obtaining an error rate caused by the error of the voter based on the third type of storage resource data, the refresh period, the unit data turnover rate and a preset third block memory error rate algorithm model;
obtaining a block memory error rate quantitative evaluation result based on the error rate caused by the block memory location error, the error rate caused by the self-refresh device error, and the error rate caused by the voter error.
Further, the first type of storage resource data is storage resource data used by a block memory module in the block memory; the second type of storage resource data is storage resource data used by a comparator module, an address generator module and an address enabler module in the configurable logic unit; the self-refresher comprises the comparator module, the address generator module, and the address enabler module; the third type of storage resource data is storage resource data used by a data voter in the configurable logic unit.
Further, the algorithm expression corresponding to the first block memory error rate algorithm model is as follows:
wherein λ iscThe unit data turnover rate corresponding to the configurable logic unit; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mbStorage resource data for use by the block memory module.
Further, the algorithm expression corresponding to the second block memory error rate algorithm model is as follows:
Mcac＝Mcom+MAdd+MCEN
wherein λ iscThe unit data turnover rate corresponding to the configurable logic unit; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mcomStorage resource data for use by the comparator module; mAddStorage resource data for use by the address generator module; mCENStorage resource data for use by the address enabler module; mcacIs the storage resource data used by the self-refresher.
Further, the algorithm expression corresponding to the third block memory error rate algorithm model is as follows:
wherein λ iscThe unit data turnover rate corresponding to the configurable logic unit; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mVDStorage resource data for use by the data voter module.
Further, under the condition of single event protection efficiency that two paths of errors occur in three paths of the same storage unit at the same time, error rates caused by different module errors are obtained respectively.
Correspondingly, the invention also provides a quantitative evaluation device for the single event upset protection design of the block memory, which comprises the following steps:
determining storage resource data, a corresponding refreshing period and a corresponding unit data turnover rate of each module in a configurable logic unit and a block memory in an SRAM type FPGA; the storage resource data comprises a first type of storage resource data, a second type of storage resource data and a third type of storage resource data;
obtaining an error rate caused by errors of the block memory part based on the first type of storage resource data, the refresh cycle, the unit data turnover rate and a preset first block memory error rate algorithm model;
obtaining an error rate caused by the self-refresher error based on the second type of storage resource data, the refreshing period, the unit data turnover rate and a preset second block memory error rate algorithm model;
obtaining an error rate caused by the error of the voter based on the third type of storage resource data, the refresh period, the unit data turnover rate and a preset third block memory error rate algorithm model;
obtaining a block memory error rate quantitative evaluation result based on the error rate caused by the block memory location error, the error rate caused by the self-refresh device error, and the error rate caused by the voter error.
Further, the first type of storage resource data is storage resource data used by a block memory module in the block memory; the second type of storage resource data is storage resource data used by a comparator module, an address generator module and an address enabler module in the configurable logic unit; the self-refresher comprises the comparator module, the address generator module, and the address enabler module; the third type of storage resource data is storage resource data used by a data voter in the configurable logic unit.
Further, the algorithm expression corresponding to the first block memory error rate algorithm model is as follows:
wherein λ iscThe unit data turnover rate corresponding to the configurable logic unit; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mbStorage resource data for use by the block memory module.
Further, the algorithm expression corresponding to the second block memory error rate algorithm model is as follows:
Mcac＝Mcom+MAdd+MCEN
wherein λ iscThe unit data turnover rate corresponding to the configurable logic unit; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mcomStorage resource data for use by the comparator module; mAddStorage resource data for use by the address generator module; mCENFor address enabler modulesThe storage resource data of (1); mcacIs the storage resource data used by the self-refresher.
Further, the algorithm expression corresponding to the third block memory error rate algorithm model is as follows:
wherein λ iscThe unit data turnover rate corresponding to the configurable logic unit; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mVDStorage resource data for use by the data voter module.
Further, under the condition of single event protection efficiency that two paths of errors occur in three paths of the same storage unit at the same time, error rates caused by different module errors are obtained respectively.
Correspondingly, the invention also provides an electronic device, comprising: the method comprises the following steps of storing a program, storing a program in a memory, and executing the program by the processor, wherein the program is executed by the processor to realize the steps of the quantitative evaluation method for the single event upset protection design of the block memory.
Accordingly, the present invention also provides a non-transitory computer readable storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the method for quantitatively evaluating a single event upset protection design of a block memory according to any one of the above items.
By adopting the quantitative evaluation method for the block memory single event upset protection design, the self-refreshing triple-modular redundancy single event protection efficiency of the block memory can be quantitatively evaluated, the probability of the block memory adopting the single event upset protection measure to have a fault is obtained, so that designers can balance the resource use and the protection effect, and the efficiency and the reliability of the optimized configuration are effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic flow chart of a block memory single event upset protection design quantitative evaluation method according to an embodiment of the present invention;
FIG. 2 is a schematic view of a complete flow chart of a block memory single event upset protection design quantitative evaluation method according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a TMR protection structure of a CLB according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a TMR protection structure of a BRAM according to an embodiment of the present invention;
fig. 5 is a TMR protection architecture diagram of a BRAM according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a block memory single event upset protection design quantitative evaluation apparatus according to an embodiment of the present invention;
fig. 7 is a schematic physical structure diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following describes an embodiment of the block memory single event upset protection design quantitative evaluation method based on the invention in detail. As shown in fig. 1 and fig. 2, which are schematic flow diagrams of a block memory single event upset protection design quantitative evaluation method provided by an embodiment of the present invention, a specific implementation process includes the following steps:
step 101: and determining storage resource data, corresponding refresh cycles and corresponding unit data turnover rates of the configurable logic units in the SRAM type FPGA and modules in the block memory. The storage resource data comprises a first type of storage resource data, a second type of storage resource data and a third type of storage resource data. Specifically, the first type of storage resource data is storage resource data used by a block memory module in the block memory; the second type of storage resource data is storage resource data used by a comparator module, an address generator module and an address enabler module in the configurable logic unit; the self-refresher comprises the comparator module, the address generator module, and the address enabler module; the third type of storage resource data is storage resource data used by a data voter in the configurable logic unit.
Step 102: and obtaining the error rate caused by the block memory part error based on the first type of storage resource data, the refreshing period, the unit data turnover rate and a preset first block memory error rate algorithm model.
Specifically, the first block memory error rate algorithm model is a preset block memory location error-caused block memory error rate algorithm formula.
In this embodiment of the present invention, the algorithm expression corresponding to the first block memory error rate algorithm model is:
wherein λ iscThe unit data turnover rate corresponding to the configurable logic unit; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mbStorage resource data for use by the block memory module.
Step 103: and obtaining the error rate caused by the self-refresher error based on the second type of storage resource data, the refreshing period, the unit data turnover rate and a preset second block memory error rate algorithm model.
Specifically, the second block memory error rate algorithm model is a preset block memory error rate algorithm formula caused by self-refresher errors in the configurable logic unit portion.
The algorithm expression corresponding to the second block memory error rate algorithm model is as follows:
Mcac＝Mcom+MAdd+MCEN
wherein λ iscThe unit data turnover rate corresponding to the configurable logic unit; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mcomStorage resource data for use by the comparator module; mAddStorage resource data for use by the address generator module; mCENStorage resource data for use by the address enabler module; mcacIs the storage resource data used by the self-refresher.
Step 104: and obtaining the error rate caused by the error of the voter based on the third type of storage resource data, the refresh period, the unit data turnover rate and a preset third block memory error rate algorithm model.
Specifically, the third block memory error rate algorithm model is a block memory error rate algorithm formula caused by voter errors in the preset configurable logic unit location.
The algorithm expression corresponding to the third block memory error rate algorithm model is as follows:
wherein λ iscThe unit data turnover rate corresponding to the configurable logic unit; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mVDStorage resource data for use by the data voter module.
Step 105: obtaining a block memory error rate quantitative evaluation result based on the error rate caused by the block memory location error, the error rate caused by the self-refresh device error, and the error rate caused by the voter error.
As shown in fig. 4, the output error of BRAM is defined as two or more paths of errors in the three-path a port output data, and the error rate is recorded as λBRAM。
In a complete embodiment, the storage resource conditions used by the modules need to be determined first. As shown in table 1, since each part employs TMR, table 1 shows the resource situation used by a single module, and the total resource situation of the module should be multiplied by 3. And determining the refresh period corresponding to each part, and the dynamic partial reconfiguration refresh period t of the CLBcAnd a refresh period t of BRAMb. The TMR protection structure of the CLB is shown in fig. 3.
TABLE 1 resource situation of each part
Further, determining the single-bit turnover rate, and respectively determining the evaluation results of the single-bit on-track SEU turnover rates of the CLB part and the BRAM part as lambdacAnd λb. The single bit on-track SEU rate of CLB and BRAM of current SRAM type FPGAs is usually 10-7h-1To 4 x 10-11h-1And the refresh period is from several seconds to several minutes, and usually will not exceed 1h, so the condition defined by the application based on practical situation is lambdac×t c1 and lambdab×tb＜＜1。
Note that, since λc×t c1 and lambdab×tbAnd < 1, the single point fault in the refreshing period of the CLB and the BRAM is eliminated, the probability of causing the BRAM error is much smaller, and the influence of the single event effect can not be considered. In addition, in the protection structure, since the Address _ CNTR has a voting function, the logic circuits compare, Address _ CNTR and CEN _ BSCNTR structures can be combined into a 1 module, which is called a self-refresh device, and is denoted as CAC. Due to the protection effect of TMR, the situation that two faults occur simultaneously in different ways and different modules of CAC, Data _ Voter and BRAM in CLB can be eliminated, and the influence of single event effect can be not considered. In addition, the probability of the single event upset of more than two parts occurring at the same time is very small, so that the single event protection efficiency condition of two paths of errors occurring in the same module is only evaluated.
Refresh period t at BRAMbIn addition, more than two of three same address storage bits of the BRAM corresponding to the TMR generate SEU, and the refresher cannot correct errors at the moment. Since the single point fault has been eliminated, the fault caused by the second order effect is considered, and the third order effect is much smaller than the second order effect, then the error of the location causes the error rate of BRAM as formula (1).
Therefore, the total BRAM error rate is proportional to the refresh time, and if the circuit only adopts TMR protection for the BRAM and does not adopt the self-refresh circuit, t is the timebIt can be considered as the life cycle of the data, i.e. the storage time of the data in the BRAM. If the data is loaded in the BRAM at the initial time and is not rewritten until the FPGA is powered off and restarted, the refreshing time at the moment is the interval time of two times of starting and powering on. For a continuous on-track running task, the longest on-off time can reach several years, namely 104h order and second order refresh period 10-3h compared, the two can differ by more than 7 orders of magnitude. The TMR detailed protection structure of BRAM is shown in fig. 5.
Refresh period t at CLBcIn addition, two ways of CAC corresponding to TMR generate SEU, and at the moment, the refresher can not correct and correct errors. Since the single point fault has been eliminated, the fault caused by the second order effect is considered, and the third order effect is much smaller than the second order effect, then the error of the location causes the error rate of BRAM as shown in equation (2).
Mcac＝Mcom+MAdd+MCEN
Refresh period t at CLBcIn the method, two paths of SEUs occur to the Data _ Voter corresponding to the TMR, and at the moment, the refresher cannot correct errors. Since the single point fault has been eliminated, the fault caused by the second order effect is considered, and the third order effect is much smaller than the second order effect, then the error of the location causes the error rate of BRAM as shown in equation (3).
By combining the above analysis, the total BRAM error rate is calculated as formula (4) by formula (4), and the block memory error rate quantitative evaluation result can be obtained.
λBRAM＝λBRAM-B+λBRAM-cac+λBRAM-VD (4)
By adopting the quantitative evaluation method for the single event upset protection design of the block memory, the self-refreshing triple-modular redundancy single event protection efficiency of the block memory can be quantitatively evaluated, the probability of the failure of the block memory adopting the single event upset protection measure is obtained, so that designers can balance the resource use and the protection effect, and the efficiency and the reliability of the optimized configuration are effectively improved.
Corresponding to the method for quantitatively evaluating the single event upset protection design of the block memory, the invention also provides a device for quantitatively evaluating the single event upset protection design of the block memory. Since the embodiment of the device is similar to the method embodiment described above, the description is simple, and please refer to the description of the method embodiment section, and the following description of the embodiment of the block memory single event upset protection design quantitative evaluation device is only schematic. Fig. 6 is a schematic structural diagram of a block memory single event upset protection design quantitative evaluation apparatus according to an embodiment of the present invention.
The invention relates to a block memory single event upset protection design quantitative evaluation device which specifically comprises the following parts:
a target data determining unit 601, configured to determine storage resource data, a corresponding refresh cycle, and a corresponding unit data turnover rate of each module in the configurable logic unit and the block memory in the SRAM-type FPGA; the storage resource data comprises a first type of storage resource data, a second type of storage resource data and a third type of storage resource data;
a first error rate analysis unit 602, configured to obtain an error rate caused by an error in a block memory location based on the first type of storage resource data, the refresh cycle, the unit data turnover rate, and a preset first block memory error rate algorithm model;
a second error rate analysis unit 603, configured to obtain an error rate caused by the self-refresh device error based on the second type of storage resource data, the refresh cycle, the unit data turnover rate, and a preset second block memory error rate algorithm model;
a third error rate analysis unit 604, configured to obtain an error rate caused by the voter error based on the third type of storage resource data, the refresh cycle, the unit data rollover rate, and a preset third block memory error rate algorithm model;
and a quantitative evaluation unit 605 for obtaining a block memory error rate quantitative evaluation result based on the error rate caused by the block memory location error, the error rate caused by the self-refresh error, and the error rate caused by the voter error.
By adopting the block memory single event upset protection design quantitative evaluation device provided by the embodiment of the invention, the self-refreshing triple-modular redundancy single event protection efficiency of the block memory can be quantitatively evaluated, the failure probability of the block memory adopting the single event upset protection measure is obtained, so that designers can balance the resource use and the protection effect, and the efficiency and the reliability of the optimized configuration are effectively improved.
Corresponding to the method for quantitatively evaluating the single event upset protection design of the block memory, the invention also provides electronic equipment. Since the embodiment of the electronic device is similar to the above method embodiment, the description is simple, and please refer to the description of the above method embodiment, and the electronic device described below is only schematic. Fig. 7 is a schematic physical structure diagram of an electronic device according to an embodiment of the present invention. The electronic device may include: a processor (processor)701, a memory (memory)702, and a communication bus 703, wherein the processor 701 and the memory 702 communicate with each other via the communication bus 703. The processor 701 may call logic instructions in the memory 702 to perform a method for quantitative evaluation of block memory single event upset protection design, the method comprising: determining storage resource data, a corresponding refreshing period and a corresponding unit data turnover rate of each module in a configurable logic unit and a block memory in an SRAM type FPGA; the storage resource data comprises a first type of storage resource data, a second type of storage resource data and a third type of storage resource data; obtaining an error rate caused by errors of the block memory part based on the first type of storage resource data, the refresh cycle, the unit data turnover rate and a preset first block memory error rate algorithm model; obtaining an error rate caused by the self-refresher error based on the second type of storage resource data, the refreshing period, the unit data turnover rate and a preset second block memory error rate algorithm model; obtaining an error rate caused by the error of the voter based on the third type of storage resource data, the refresh period, the unit data turnover rate and a preset third block memory error rate algorithm model; obtaining a block memory error rate quantitative evaluation result based on the error rate caused by the block memory location error, the error rate caused by the self-refresh device error, and the error rate caused by the voter error.
Furthermore, the logic instructions in the memory 702 may be implemented in software functional units and stored in a computer readable storage medium when sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In another aspect, an embodiment of the present invention further provides a computer program product, where the computer program product includes a computer program stored on a non-transitory computer-readable storage medium, where the computer program includes program instructions, and when the program instructions are executed by a computer, the computer is capable of executing the method for quantitatively evaluating the single event upset protection design of a block memory provided in the foregoing method embodiments, where the method includes: determining storage resource data, a corresponding refreshing period and a corresponding unit data turnover rate of each module in a configurable logic unit and a block memory in an SRAM type FPGA; the storage resource data comprises a first type of storage resource data, a second type of storage resource data and a third type of storage resource data; obtaining an error rate caused by errors of the block memory part based on the first type of storage resource data, the refresh cycle, the unit data turnover rate and a preset first block memory error rate algorithm model; obtaining an error rate caused by the self-refresher error based on the second type of storage resource data, the refreshing period, the unit data turnover rate and a preset second block memory error rate algorithm model; obtaining an error rate caused by the error of the voter based on the third type of storage resource data, the refresh period, the unit data turnover rate and a preset third block memory error rate algorithm model; obtaining a block memory error rate quantitative evaluation result based on the error rate caused by the block memory location error, the error rate caused by the self-refresh device error, and the error rate caused by the voter error.
In another aspect, an embodiment of the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored, where the computer program is implemented to perform the method for quantitatively evaluating a single-event upset protection design of a block memory provided in the foregoing embodiments when executed by a processor, where the method includes: determining storage resource data, a corresponding refreshing period and a corresponding unit data turnover rate of each module in a configurable logic unit and a block memory in an SRAM type FPGA; the storage resource data comprises a first type of storage resource data, a second type of storage resource data and a third type of storage resource data; obtaining an error rate caused by errors of the block memory part based on the first type of storage resource data, the refresh cycle, the unit data turnover rate and a preset first block memory error rate algorithm model; obtaining an error rate caused by the self-refresher error based on the second type of storage resource data, the refreshing period, the unit data turnover rate and a preset second block memory error rate algorithm model; obtaining an error rate caused by the error of the voter based on the third type of storage resource data, the refresh period, the unit data turnover rate and a preset third block memory error rate algorithm model; obtaining a block memory error rate quantitative evaluation result based on the error rate caused by the block memory location error, the error rate caused by the self-refresh device error, and the error rate caused by the voter error.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A quantitative evaluation method for single event upset protection design of a block memory is characterized by comprising the following steps:
determining storage resource data, a corresponding refreshing period and a corresponding unit data turnover rate of each module in a configurable logic unit and a block memory in an SRAM type FPGA; the storage resource data comprises a first type of storage resource data, a second type of storage resource data and a third type of storage resource data;
obtaining an error rate caused by errors of the block memory part based on the first type of storage resource data, the refresh cycle, the unit data turnover rate and a preset first block memory error rate algorithm model;
obtaining an error rate caused by the self-refresher error based on the second type of storage resource data, the refreshing period, the unit data turnover rate and a preset second block memory error rate algorithm model;
obtaining an error rate caused by the error of the voter based on the third type of storage resource data, the refresh period, the unit data turnover rate and a preset third block memory error rate algorithm model;
obtaining a block memory error rate quantitative evaluation result based on the error rate caused by the block memory location error, the error rate caused by the self-refresh device error, and the error rate caused by the voter error.
2. The quantitative evaluation method for the single event upset protection design of the block memory according to claim 1, wherein the first type of storage resource data is storage resource data used by a block memory module in the block memory; the second type of storage resource data is storage resource data used by a comparator module, an address generator module and an address enabler module in the configurable logic unit; the self-refresher comprises the comparator module, the address generator module, and the address enabler module; the third type of storage resource data is storage resource data used by a data voter in the configurable logic unit.
3. The quantitative evaluation method for the block memory single event upset protection design according to claim 1, wherein the algorithm expression corresponding to the first block memory error rate algorithm model is as follows:
wherein λ iscThe unit data turnover rate corresponding to the configurable logic unit; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mbStorage resource data for use by the block memory module.
4. The quantitative evaluation method for the block memory single event upset protection design according to claim 1, wherein the algorithm expression corresponding to the second block memory error rate algorithm model is as follows:
Mcac＝Mcom+MAdd+MCEN
wherein λ iscThe unit data turnover rate corresponding to the configurable logic unit; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mcomStorage resource data for use by the comparator module; mAddStorage resource data for use by the address generator module; mCENStorage resource data for use by the address enabler module; mcacIs the storage resource data used by the self-refresher.
5. The quantitative evaluation method for the block memory single event upset protection design according to claim 1, wherein the algorithm expression corresponding to the third block memory error rate algorithm model is as follows:
wherein, go intocCorresponding to configurable logic cellsA unit data flip rate; lambda [ alpha ]bThe unit data turnover rate corresponding to the block memory; t is tcConfiguring a refreshing period corresponding to the logic unit; t is tbA refresh period corresponding to the block memory; mVDStorage resource data for use by the data voter module.
6. The quantitative evaluation method for the block memory single event upset protection design according to claim 1, characterized in that under the condition of single event protection effectiveness that two paths of errors occur in three paths of the same memory cell at the same time, error rates caused by different module errors are respectively obtained.
7. A block memory single event upset protection design quantitative evaluation device is characterized by comprising:
the target data determining unit is used for determining storage resource data, corresponding refreshing cycles and corresponding unit data turnover rates of the configurable logic unit in the SRAM type FPGA and each module in the block memory; the storage resource data comprises a first type of storage resource data, a second type of storage resource data and a third type of storage resource data;
the first error rate analysis unit is used for obtaining the error rate caused by the error of the block memory part based on the first type of storage resource data, the refreshing period, the unit data turnover rate and a preset first block memory error rate algorithm model;
a second error rate analysis unit, configured to obtain an error rate caused by the self-refresh device error based on the second type of storage resource data, the refresh cycle, the unit data turnover rate, and a preset second block memory error rate algorithm model;
a third error rate analysis unit, configured to obtain an error rate caused by the voter error based on the third type of storage resource data, the refresh cycle, the unit data rollover rate, and a preset third block memory error rate algorithm model;
and the quantitative evaluation unit is used for obtaining a quantitative evaluation result of the error rate of the block memory based on the error rate caused by the error of the block memory position, the error rate caused by the self-refreshing device error and the error rate caused by the voter error.
8. The quantitative evaluation device for the block memory single event upset protection design according to claim 7, wherein the first type of storage resource data is storage resource data used by a block memory module in the block memory; the second type of storage resource data is storage resource data used by a comparator module, an address generator module and an address enabler module in the configurable logic unit; the self-refresher comprises the comparator module, the address generator module, and the address enabler module; the third type of storage resource data is storage resource data used by a data voter in the configurable logic unit.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the method for quantitative evaluation of single event upset protection design in a block memory according to any of claims 1 to 6 when executing the program.
10. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the steps of the method for quantitative evaluation of a block memory single event upset protection design according to any one of claims 1 to 6.
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