CN112953531A - Phase-locked loop fractional frequency division method based on novel delta-sigma modulator - Google Patents
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Abstract
The invention provides a phase-locked loop fractional frequency division method based on a novel delta-sigma modulator, which adopts a pulse-swallowing type programmable frequency divider to realize frequency division, wherein the frequency divider comprises a high-speed 8/9 prescaler, a programmable M counter, a programmable A counter, a novel delta-sigma modulator and a symbol expansion module; in the frequency divider architecture: the M counter is an n-bit counter and the a counter is an M-bit counter, and the integer part of the division ratio has a number of bits of (n + M) and the fractional part has a number of bits of p. And different frequency division ratios and frequency resolutions are obtained by adjusting the values of n, m and p. The novel delta-sigma modulator is of an MASH type, an error feedback modulator with few bits and an LFSR pseudo-random sequence generator are added, the MASH type delta-sigma modulator is simple in design, time sequence requirements are easily met, and the layout area is small. Despite the introduction of jitter by the LFSR, noise at the low frequencies of the delta-sigma modulator output sequence is not degraded.
Description
Technical Field
The invention relates to the field of digital-analog hybrid integrated circuits and radio frequency integrated circuits, in particular to a frequency divider circuit of a fractional frequency division phase-locked loop, and more particularly to a fractional frequency division method of a phase-locked loop based on a novel delta-sigma modulator.
Background
The modern frequency synthesizer generally adopts a phase-locked loop PLL structure, and the design of the frequency synthesizer is challenged by broadband, low noise, high frequency resolution, fast switching, low power consumption and the like. In order to solve the contradiction between the frequency resolution and the frequency switching, a scheme of a fractional frequency division phase-locked loop is adopted in many applications. A very important module in fractional-n plls is the fractional divider.
One of the great application problems of fractional division techniques is the generation of fractional spurs. Since the 80 s of the last century, after fractional division technology began to spread, how to suppress fractional spurs also became a research hotspot of fractional division phase-locked loops, such as DAC compensation methods, phase interpolation methods, and delta-sigma modulator technologies. In the DAC compensation method, it is assumed that generation of fractional spurs can be estimated, and such effective estimation is generally effective only when a first-order Δ Σ modulator, i.e., an accumulator, is used as a frequency division ratio switching control block (see references 1 and 5), and for a higher-order Δ Σ modulator, the DAC compensation scheme is not easily implemented, and further, the spur suppression effect is greatly affected by mismatch and accuracy of the DAC, and PFD (phase detector)/CP (charge pump) nonlinearity. Phase interpolation essentially reduces the magnitude of fractional spurs, but fractional spurs still exist because phase interpolation processes the VCO output signal (see reference 2), not the divide ratio. The delta-sigma modulator is used as a frequency division ratio switching control module, and the greatest advantage is that the frequency resolution of the phase-locked loop can be greatly improved.
The delta-sigma modulator transfers the frequency spectrum of quantization noise to a high frequency by means of noise shaping, and then suppresses the quantization noise by using the low-pass characteristic of the phase-locked loop itself. The delta-sigma modulator adopted in the fractional-N phase-locked loop is generally realized by a digital finite-state machine, so that the output sequence of the modulator has a certain period length, and the core method for inhibiting fractional spurs is to prolong the period length.
Further, it is specifically noted that, in order to omit the trouble of repeated description, the entire contents of references 1 to 5 are actually incorporated in their entirety into the present application based on the disclosure thereof. See the following references 1-5 for details.
Reference 1: "A fraction-N fraction synthesizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.50, No.11, pp.839-849, Nov.2003.
Reference 2: prudenus research and design of fractional divider based on phase interpolation [ D ] university of electronic science and technology in hangzhou 2020.
Reference 3: ringzhi, design of a fractional divider in a 5G-oriented CMOS phase-locked loop frequency synthesizer [ D ]. southeast university, 2019.
Reference 4: song and I.park, "spread-Free MASH Delta-Sigma Modulation," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol.57, No.9, pp.2426-2437, Sept.2010
Reference 5: royal Tengjia, Li national Confucian, Li Haoming, Shen Yupeng, Chen Xu. CN109936361B, 2020-08-04.
Disclosure of Invention
The invention provides a phase-locked loop fractional frequency division method based on a novel Delta-sigma modulator, which comprises a high-speed 8/9 prescaler, a programmable M counter, a programmable A counter, a novel Delta-sigma (Delta-sigma) modulator and a symbol expansion module;
the high-speed 8/9 prescaler prescalers the VCO (voltage controlled oscillator) output clock to generate f1 output frequency, when the mode control signal MC is high, the frequency dividing ratio is 9, and when the mode control signal MC is low, the frequency dividing ratio is 8;
the M counter divides the frequency of the output signal f1 of the prescaler, the frequency dividing ratio is M, the value of M is determined by the input n-bit binary number, and the range is 1 to (2)n-1) loading a new counter value M after the M counter has completed a round of up-counting, and simultaneously outputting a 1/f1 period Reset signal Reset to the a counter to Reset the a counter, the new counter value a being loaded, the value of a being determined by the input M-bit binary number and ranging from 0 to (2)m-1)；
A counter: taking f1 as a clock, the counter A performs down counting, the output signal MC is high in the counting process, after the counter A completes one round of counting, the output signal MC is low, and the counter M is waited to complete counting, so that a reset signal is provided for the counter A;
the novel delta-sigma modulator takes an output signal after frequency division as a clock, the modulator is a frequency division ratio switching control module, p-bit decimal frequency control words are input, the real-time frequency division ratio of the whole decimal frequency divider is an integer, and the output clock changes for 1 time after every other frequency division, so that decimal frequency division is realized on average effect; the delta-sigma modulator outputs a 4-bit digital signal to the symbol expansion module; the 4-bit digital signal is a signed number, and sign expansion is carried out to (n + m) bits through a sign expansion module.
Further, the novel delta-sigma modulator is a MASH1-1-1 type delta-sigma modulator, comprises 3 error feedback modulators, and comprises a delay unit 1/z and an adder to form an error elimination unit.
The linear model of the novel delta-sigma modulator is MASH1-1-1 type delta-sigma modulator is as follows:
in the linear model, Y (z), X (z), E (z) are z-transformed versions of y [ n ], x [ n ], and e [ n ], respectively; d (z) is a z-transformed version of dither d [ n ]; p is the modulus of the p-bit accumulator.
And the counter value A of the counter A is less than or equal to the counter value M of the counter M.
Wherein, the M counter is an n-bit counter, the A counter is an M-bit counter, the number of bits of the integer part of the frequency dividing ratio is (n + M) bits, and the number of bits of the decimal part is p bits; and different frequency division ratios and frequency resolutions are obtained by adjusting the values of n, m and p.
Drawings
FIG. 1 is a diagram illustrating a fractional frequency division method and an architecture of a phase-locked loop according to the present invention;
FIG. 2(a) is an EFM linear model;
FIG. 2(b) is the MASH1-1-1 linear model;
FIG. 3 is a MASH structure according to the present invention;
FIG. 4 is an exemplary LFSR circuit configuration;
FIG. 5 is a schematic diagram illustrating the verification of a delta-sigma modulator for real-time divide ratio modulation;
fig. 6 is a plot of the power spectral density of the modulator output sequence.
Detailed Description
In order to delay the period length of the output sequence of the delta-sigma modulator, the invention provides a novel MASH (Multi-stageneroise mapping) type delta-sigma modulator, and compared with the traditional MASH, an Error Feedback Modulator (EFM) and an LFSR (Linear Feedback Shift register) pseudo-random sequence generator with a small number of bits are added. The MASH type delta-sigma modulator is simple in design, easy to meet the time sequence requirement and small in layout area. Despite the introduction of jitter by the LFSR, noise at the low frequencies of the delta-sigma modulator output sequence is not degraded. In addition, the invention provides an implementation scheme for applying the novel MASH type modulator to a pulse swallow type programmable frequency divider.
In the present invention, the whole frequency divider scheme is as shown in fig. 1, and includes a high-speed 8/9 prescaler, a programmable M counter, a programmable a counter, a novel Delta-sigma (Delta-sigma) modulator, and a symbol expanding module. The frequency divider provided by the invention is a digital frequency divider, and each module is realized by digital synthesis by adopting verilog codes.
The fractional frequency divider main body framework is a pulse swallowing programmable frequency divider, and the working mode of the fractional frequency divider is introduced as follows:
high speed 8/9 prescaler: the output clock of a VCO (voltage controlled oscillator) is prescaled to generate an output frequency f1, when a mode control signal MC is high, the frequency dividing ratio is 9, and when the mode control signal MC is low, the frequency dividing ratio is 8.
M counter: frequency division is carried out on the output signal f1 of the prescaler, the frequency division ratio is M, the value of M is determined by the input n-bit binary number, and the range is 1 to (2)n-1) loading a new counter value M after the M counter has completed a round of up-counting, and simultaneously outputting a 1/f1 period Reset signal Reset to the a counter to Reset the a counter, the new counter value a being loaded, the value of a being determined by the input M-bit binary number and ranging from 0 to (2)m-1)。
A counter: and f1 is used as a clock, the A counter performs down counting, the output signal MC is high in the counting process, after the A counter completes one round of counting, the output signal MC is low, and the M counter is waited to complete counting, and a reset signal is provided for the M counter, wherein the counter value A of the A counter is less than or equal to the counter value M of the M counter (namely, A is less than or equal to M).
Novel delta-sigma modulator: the output signal after frequency division is used as a clock, the modulator is a frequency division ratio switching control module, p-bit decimal frequency control words are input, the real-time frequency division ratio of the whole decimal frequency divider is an integer, but the frequency division ratio is modulated by the output of the delta-sigma modulator, and the output clock changes for 1 time after every other frequency division, so that decimal frequency division is achieved on the average effect. The delta-sigma modulator outputs a 4-bit digital signal to the symbol spreading module.
A symbol expansion module: the novel delta-sigma modulator outputs 4-bit digital signals as signed numbers, and the signs need to be expanded to (n + m) bits so as to be added with the (n + m) bit integer frequency division ratio.
The above 5 modules are mutually matched, so that a frequency dividing ratio can be realized: 8 × M + a, frequency resolution ═ phase locked loop reference clock × 1/2p。
As shown in fig. 1, in the divider architecture: the M counter is an n-bit counter and the a counter is an M-bit counter, and the integer part of the division ratio has a number of bits of (n + M) and the fractional part has a number of bits of p. Design workers can adjust the values of n, m and p according to requirements to obtain different frequency division ratios and frequency resolutions.
The core of the invention is mainly described below:
novel delta-sigma modulator
The delta-sigma modulator transfers the frequency spectrum of quantization noise to a high frequency by a noise shaping method, and then suppresses the quantization noise by utilizing the low-pass characteristic of the phase-locked loop. The delta-sigma modulator is typically implemented with a digital finite state machine, and the MASH type modulator is a classic type of delta-sigma modulator, but because of finite state machine implementation issues, the period length of the MASH output sequence is closely related to the input fractional divide control word and the initial value of the accumulator in the MASH.
As shown in fig. 2(b), the MASH1-1-1 type Δ Σ modulator includes: and 3 error feedback modulators, wherein the delay unit 1/z and the adder form an error elimination unit.
Where EFM is typically implemented with an accumulator and the input is a fractional part of a P-bit frequency divider, EFM may be a P-bit accumulator, and the modulus of the accumulator is P, where P is 28。
The EFM model is expressed using linear equations:
wherein Y (z), X (z), E (z) are z-transformed versions of y [ n ], x [ n ], and e [ n ], respectively;
then for FIG. 2(b), there are
Y1(z)、Y2(z)、Y3(z) are each y1[ n ]]、y2[n]、y3[n]Form of z transformation of (E)1(z)、E2(z)、E3(z) is e1[ n ]]、e2[n]、e3[n]Z transformed form of (1).
Then, according to the operation of the error elimination unit, it can obtain
The implementation method for adding the MASH output result to the frequency dividing ratio comprises the following steps: the MASH1-1-1 output result is a 4-bit signed number, taking the scheme in fig. 1 as an example, m is the high m-bit of the integer frequency division ratio, n is the low n-bit of the integer frequency division ratio, the MASH output result needs to pass through a sign expansion module, the 4-bit output result is expanded to (n + m) -bit, and then is added with the (n + m) -bit integer frequency division ratio to obtain a new frequency division ratio, and then is loaded into the frequency divider.
The output sequence period length of a MASH1-1-1 type Δ Σ modulator is at most 2P and is affected by the initial value of the accumulator in the input x [ n ] and EFM, which in turn causes fractional spurs in the output spectrum of the PLL.
In order to extend the period length of the digitally implemented delta-sigma modulator output sequence, the present invention proposes a novel MASH architecture: as shown in fig. 3, the new MASH structure adds an EFM with a small number of bits compared to the conventional MASH, and an lfsr (linear Feedback Shift register) pseudo random sequence generator.
The linear model of the output of the MASH type Δ Σ modulator in the present invention is:
wherein D (z) is jitter d [ n ]]Z transformed form of (1). The period of K-stage LFSR output sequence is K-2k-1, the output sequence period of this structure is 16K × P2And is not subject to input x [ n ]]And the effect of the accumulator initial value in EFM, it can be seen from the second term in (equation 6) that adding a 4-bit EFM can reduce jitter d n]Middle low frequency component to effective output
The interference of (2). The output sequence period range of SP-MASH1-1-1 proposed in reference 4 is: 2 XP2～P3Is inputted x [ n ]]The MASH structure proposed in reference 3 has one more EFM compared to SP-MASH1-1-1, and the EFM bit number needs to be larger to obtain better fractional spur suppression. Compared with the two schemes of reference 3 and reference 4, the k-stage LFSR of the present invention has only k registers and a few simple logic gates, for example, an 8-stage LFSR, as shown in fig. 4. The EFM (namely 4-bit accumulator) is simple in design, easy to meet the time sequence requirement and small in layout area. Despite the introduction of jitter d n]But does not degrade the noise at the low frequencies of the delta-sigma modulator output sequence.
Examples of the applications
The whole divider in fig. 1 was simulated, and m-3, n-8, and p-8 were selected. Setting the VCO output clock to be 10GHz, and the frequency dividing ratio to be: the integer part is 112, the corresponding binary number is the fractional part: 11b000_0111_000, the fractional part is P/2, the selected EFM bit number is P-8 bits, P-256, and the input of the novel Δ Σ modulator is 8b1000_ 0000. In the LFSR, the number of stages k is 7.
The simulation results are as follows: verification of the modulation of the real-time division ratio by the delta-sigma modulator of the present invention is shown in fig. 5.
As shown in fig. 5, sd _ out is a 4-bit binary number output by the MASH Δ Σ modulator of the present invention, and is a signed number, DIV is the dividing ratio of the entire divider, and when sd _ out is a hexadecimal number 2, DIV is 112+ 2; when sd _ out is a hexadecimal number F, DIV is 112-1; when sd _ out is a hexadecimal number 0, the DIV is 112+ 0. By analogy, the frequency dividing ratio of the frequency divider can be modulated by the delta-sigma modulator.
The effect of the MASH type Δ Σ modulator of the present invention on suppression of fractional spurs can be obtained by MATLAB simulink simulation, as shown in fig. 6, the fractional part and EFM bit number of the same input division ratio are the same, and the MASH type Δ Σ modulator of the present invention has a good effect of suppressing spurs, and at the same time, the power spectral density characteristic at low frequencies is not deteriorated despite jitter introduced into the modulator.
While the foregoing is directed to the embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (5)
1. A phase-locked loop fractional frequency division method based on a novel Delta-sigma modulator comprises a high-speed 8/9 prescaler, a programmable M counter, a programmable A counter, a novel Delta-sigma (Delta-sigma) modulator and a symbol expansion module;
the high-speed 8/9 prescaler prescalers the VCO (voltage controlled oscillator) output clock to generate f1 output frequency, when the mode control signal MC is high, the frequency dividing ratio is 9, and when the mode control signal MC is low, the frequency dividing ratio is 8;
the M counter divides the frequency of the output signal f1 of the prescaler, the frequency dividing ratio is M, the value of M is determined by the input n-bit binary number, and the range is 1 to (2)n-1) loading a new counter value M after the M counter has completed a round of up-counting, and simultaneously outputting a 1/f1 period Reset signal Reset to the a counter to Reset the a counter, the new counter value a being loaded, the value of a being determined by the input M-bit binary number and ranging from 0 to (2)m-1)；
A counter: taking f1 as a clock, the counter A performs down counting, the output signal MC is high in the counting process, after the counter A completes one round of counting, the output signal MC is low, and the counter M is waited to complete counting, so that a reset signal is provided for the counter A;
the novel delta-sigma modulator takes an output signal after frequency division as a clock, the modulator is a frequency division ratio switching control module, p-bit decimal frequency control words are input, the real-time frequency division ratio of the whole decimal frequency divider is an integer, and the output clock changes for 1 time after every other frequency division, so that decimal frequency division is realized on average effect; the delta-sigma modulator outputs a 4-bit digital signal to the symbol expansion module; the 4-bit digital signal is a signed number, and sign expansion is carried out to (n + m) bits through a sign expansion module.
2. The method of claim 1, wherein the method comprises the following steps:
the novel delta-sigma modulator is a MASH1-1-1 type delta-sigma modulator, comprises 3 error feedback modulators, and comprises an error elimination unit consisting of a delay unit 1/z and an adder.
3. The novel delta-sigma modulator based phase locked loop fractional division method of claim 1 or 2, characterized in that:
the linear model of the novel delta-sigma modulator is a MASH1-1-1 type delta-sigma modulator is as follows:
wherein Y (z), X (z), E (z) are z-transformed versions of y [ n ], x [ n ], and e [ n ], respectively; d (z) is a z-transformed version of dither d [ n ]; p is the modulus of the p-bit accumulator.
4. The method for fractional division of a phase locked loop based on a novel delta-sigma modulator as claimed in any of claims 1 to 3, characterized in that: and the counter value A of the counter A is less than or equal to the counter value M of the counter M.
5. The method of claim 1, wherein the method comprises the following steps: wherein, the M counter is an n-bit counter, the A counter is an M-bit counter, the number of bits of the integer part of the frequency dividing ratio is (n + M) bits, and the number of bits of the decimal part is p bits; and different frequency division ratios and frequency resolutions are obtained by adjusting the values of n, m and p.
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