CN112951901A

CN112951901A - Semiconductor structure

Info

Publication number: CN112951901A
Application number: CN201911171930.2A
Authority: CN
Inventors: 林鑫成; 周政伟
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2019-11-26
Filing date: 2019-11-26
Publication date: 2021-06-11

Abstract

A semiconductor structure, comprising: the grid structure comprises a grid electrode arranged on the substrate and a grid metal layer arranged on the grid electrode, wherein the grid metal layer at least has a gap, the gap exposes the grid electrode below, and the potential of the source electrode structure is different from that of the grid electrode structure.

Description

Semiconductor structure

Technical Field

The present invention relates to semiconductor structures, and more particularly to semiconductor structures having gate field plates.

Background

Gallium nitride-based (GaN-based) semiconductor materials have many excellent material characteristics, such as high heat resistance, wide band-gap (band-gap), and high electron saturation rate. Therefore, the gallium nitride based semiconductor material is suitable for high speed and high temperature operation environment. In recent years, gallium nitride-based semiconductor materials have been widely used in Light Emitting Diode (LED) devices, high frequency devices such as High Electron Mobility Transistors (HEMTs) having a hetero-interface structure, and the like.

With the development of gallium nitride-based semiconductor materials, these semiconductor devices using gallium nitride-based semiconductor materials are applied in more severe operating environments, such as higher frequencies, higher temperatures, or higher voltages. Therefore, there is still a need for further improvement of semiconductor devices having gallium nitride based semiconductor materials to overcome the challenges.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor structure, comprising: the transistor comprises a substrate, a grid structure on the substrate, and a source electrode structure and a drain electrode structure which are arranged on the substrate and are arranged on two sides of the grid structure. The gate structure includes a gate electrode on the substrate and a gate metal layer on the gate electrode. The gate metal layer has at least one notch (notch) exposing the gate electrode therebelow. The source structure is at a different potential than the gate structure.

Some embodiments of the present invention further provide a semiconductor structure, comprising: the transistor comprises a substrate, a grid structure on the substrate, and a source electrode structure and a drain electrode structure which are arranged on the substrate and are arranged on two sides of the grid structure. The gate structure includes a gate electrode on the substrate and a gate metal layer on the gate electrode. In the top view of the gate electrode and the gate metal layer projected to the substrate, the gate metal layer is U-shaped (U shape) and partially overlaps the gate electrode.

Drawings

The embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the present invention.

FIG. 1 is a partial perspective view illustrating an exemplary semiconductor structure, according to some embodiments of the present invention;

FIG. 2 is a perspective view illustrating an exemplary partial semiconductor structure, in accordance with some embodiments of the present invention;

FIG. 3 illustrates a partial top projection view of the semiconductor structure corresponding to that shown in FIG. 1, in accordance with some embodiments of the present invention;

FIGS. 4-11 are partial top plan views of semiconductor structures according to other embodiments of the present invention;

FIG. 12 illustrates a cross-sectional view taken along line A-A' of the semiconductor structure of FIG. 1, in accordance with certain embodiments of the present invention;

FIG. 13 is a partial perspective view illustrating an exemplary semiconductor structure according to other embodiments of the present invention;

FIG. 14 is a cross-sectional view taken along line B-B' of the semiconductor structure shown in FIG. 13, in accordance with another embodiment of the present invention;

FIG. 15 is a schematic cross-sectional view illustrating a semiconductor structure according to another embodiment of the present invention;

FIG. 16 is a partial perspective view illustrating an exemplary semiconductor structure according to further embodiments of the present invention;

FIG. 17 is a partial perspective view illustrating an exemplary semiconductor structure according to further embodiments of the present invention;

FIG. 18 is a cross-sectional view of a line C-C' corresponding to the semiconductor structure of FIG. 1, in accordance with further embodiments of the present invention.

[ description of symbols ]

100. 200, 300, 400-semiconductor structure

102-substrate

110-compound semiconductor layer

112 buffer layer

114 channel layer

116 barrier layer

120. 130 dielectric layer

140-source electrode structure

142 source electrode

144 source contact

146 source metal layer

147 to opening (of source metal layer)

148 source metal layer

149 to (of the additional source metal layer) opening

150-grid structure

152-gate electrode

154-gate metal layer

154 a-profile of gate metal layer on both sides of the gap

155-gap (of gate metal layer)

156-doped compound semiconductor layer

160-drain structure

162-drain electrode

164-drain contact

166-Drain Metal layer

170 dielectric layer

L-length

T1-thickness

WN-width (of gap)

Width of WG (of gate electrode)

WGM1 (minimum of gate metal layer) width

WGM2 (maximum gate metal layer) width

WO1 (of the opening of the source metal layer)

WO2 width (of the opening of the additional source metal layer)

A-A ', B-B ', C-C ' -section plane (section line)

Detailed Description

Various embodiments or examples are provided below for implementing different elements of the provided semiconductor structures. References in the specification to a first element being formed on a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that the first and second elements are not in direct contact. In addition, embodiments of the present invention may use repeated reference numerals in many instances. These repetitions are merely for simplicity and clarity and do not represent a particular relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, such as "above," "below," "above … …," "below … …," and the like, encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to other orientations (rotated 90 degrees or other orientations), then the spatially relative descriptors used herein should be interpreted as such with respect to the rotated orientation.

As used herein, the term "about", "about" or "substantially" generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are approximate amounts, i.e., the meanings of "about", "about" and "about" may be implied without specific recitation of "about", "about" and "about".

The semiconductor structure provided by the embodiment of the invention reduces the risk of the gate structure suffering from high electric field by extending the gate metal layer along the direction of the drain structure and using the gate metal layer as a gate field plate (gate field plate), and the gate field plate is provided with at least one notch to effectively reduce the gate-to-drain capacitance (C)_gd) And gate to source capacitance (C)_gs) Further, the switching loss (switch loss) is reduced, and the malfunction at the time of fast switching is also reduced. Therefore, the semiconductor structure provided by the embodiment of the invention can reduce the input capacitance (C)_gs+C_gd) The switching loss can be effectively reduced, and the efficiency of the semiconductor structure is further improved.

Fig. 1 is a partial perspective view illustrating an exemplary semiconductor structure, according to some embodiments of the present invention. As shown in fig. 1, the semiconductor structure 100 includes a compound semiconductor layer 110 on a substrate 102, a dielectric layer 120 on the compound semiconductor layer 110, and a dielectric layer 130. The semiconductor structure 100 further includes a gate structure 150 on the semiconductor compound layer 110, and a source structure 140 and a drain structure 160 on both sides of the gate structure.

In some embodiments, the substrate 102 may be a doped (e.g., doped with a p-type or n-type dopant) or undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or similar semiconductor substrate. In some embodiments, the substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (silicon on insulator) substraten-on insulator, SOI) substrate. In other embodiments, the substrate 102 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an alumina substrate (Al)₂O₃) (otherwise known as Sapphire (Sapphire) substrates) or other similar substrates.

In some embodiments, the compound semiconductor layer 110 includes a buffer layer 112, a channel layer 114 on the buffer layer 112, and a barrier layer 116 on the channel layer 114. The buffer layer 112 may relieve strain (strain) of a channel layer 114 subsequently formed on the buffer layer 112 to prevent defects from forming in the overlying channel layer 114. The strain is caused by the mismatch of the channel layer 114 and the substrate 102. In some embodiments, the material of the buffer layer 112 may be AlN, GaN, Al_xGa_1-xN (wherein 0)<x<1) Combinations of the foregoing, or other similar materials. The buffer layer 112 may be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), combinations thereof, or the like. It is noted that although the buffer layer 112 has a single-layer structure in the embodiment shown in fig. 1, the buffer layer 112 may have a multi-layer structure (not shown) in other embodiments.

In some embodiments, a two-dimensional electron gas (2DEG) (not shown) is formed at the heterointerface between the channel layer 114 and the barrier layer 116. The semiconductor structure 100 shown in fig. 1 is a High Electron Mobility Transistor (HEMT) using a two-dimensional electron gas (2DEG) as a conductive carrier. In some embodiments, the channel layer 114 may be a gallium nitride (GaN) layer, and the barrier layer 116 formed on the channel layer 114 may be an aluminum gallium nitride (AlGaN) layer, wherein the GaN layer and the aluminum gallium nitride layer may or may not have dopants (e.g., n-type dopants or p-type dopants). Both the channel layer 114 and the barrier layer 116 may be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), combinations thereof, or the like.

With continued reference to fig. 1, next,

dielectric layers

120 and 130, a gate structure 150, and a source structure 140 and a drain structure 160 on both sides of the gate structure 150 are formed on the compound semiconductor layer 110 by a deposition process and a patterning process.

In some embodiments, the gate structure 150 includes a gate electrode 152 and a gate metal layer 154 electrically connected to the gate electrode 152. In some embodiments, gate electrode 152 is disposed on barrier layer 116 and embedded in dielectric layer 120, and gate metal layer 154 is disposed on dielectric layer 120 and covered by dielectric layer 130. In other embodiments, an optional doped compound semiconductor layer 156 may be included between the gate electrode 152 and the barrier layer 116, the details of which will be described further below.

In some embodiments, source structure 140 includes a source electrode 142, a source contact 144, and a source metal layer 146. In some embodiments, the source electrode 142 is embedded in the dielectric layer 120, and the source metal layer 146 is disposed on the dielectric layer 130, wherein the source electrode 142 and the source metal layer 146 are electrically connected by the source contact 144 embedded in the dielectric layer 130. The source metal layer 146 electrically connected to the source electrode 142 has a different potential from the gate metal layer 154 electrically connected to the gate electrode 152. In this embodiment, the source metal layer 146 reduces the electric field strength by extending along the direction of the drain structure and acting as a source field plate (source field plate).

In some embodiments, the drain structure 160 includes a drain electrode 162, a drain contact 164, and a drain metal layer 166. In some embodiments, the drain electrode 162 is embedded in the dielectric layer 120, and the drain metal layer 166 is disposed on the dielectric layer 130, wherein the drain electrode 162 and the drain metal layer 166 are electrically connected by the drain contact 164 embedded in the dielectric layer 130. In some embodiments, the source electrode 142 and the drain electrode 162 on both sides of the gate electrode 152 contact the channel layer 114 through the barrier layer 116.

In some embodiments, the material of the gate electrode 152 may be a conductive material, such as a metal, a metal nitride, or a semiconductor material. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, combinations thereof, or multi-layer structures thereof. The semiconductor material may be polysilicon or poly-germanium. The conductive material may be formed on the barrier layer 116 by, for example, Chemical Vapor Deposition (CVD), sputtering, resistive heating evaporation, e-beam evaporation, or other suitable deposition methods, and then patterned to form the gate electrode 152.

In some embodiments, the doped compound semiconductor layer 156 may be formed on the barrier layer 116 before the gate electrode 152 is formed, and then the gate electrode 152 is formed on the doped compound semiconductor layer 156. By disposing the doped compound semiconductor layer 156 between the gate electrode 152 and the barrier layer 116, the generation of a two-dimensional electron gas (2DEG) under the gate electrode 152 can be suppressed to achieve a normally-off state of the semiconductor structure 100. In some embodiments, the material of the doped compound semiconductor layer 156 may be p-type doped or n-type doped gallium nitride (GaN). The step of forming the doped compound semiconductor layer 156 may include forming it at a position corresponding to a position where the gate electrode 152 is to be formed, by epitaxial growth and etch-back processes.

In some embodiments, the material of the source electrode 142 and the drain electrode 162 formed on both sides of the gate electrode 152 may be selected from the materials used to form the gate electrode 152. Moreover, the gate electrode 152 and the source electrode 142 and the drain electrode 162 on both sides thereof may be formed in the same process, and thus are not described herein again. In other embodiments, the gate electrode 152 and the source electrode 142 and the drain electrode 162 on both sides thereof may be formed in different processes.

In some embodiments, the gate metal layer 154, the source contact 144, the source metal layer 146, the drain contact 164, and the drain metal layer 166 may be formed by a deposition process and a patterning process, and the material of the material may include a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), silicon nitride (TaC), tantalum nitride (TaSiN), tantalum nitride (TaCN), titanium aluminide (TiAl), titanium nitride (TiAlN), a metal oxide, a metal alloy, other suitable conductive materials, or a combination thereof.

In some embodiments, the

dielectric layers

120, 130 may each comprise one or more single or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, Tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and/or other suitable dielectric materials. Low-k dielectric materials may include, but are not limited to, Fluorinated Silicon Glass (FSG), Hydrogen Silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous carbon fluoride (fluorinated carbon), parylene, benzocyclobutene (BCB), or polyimide (polyimide). For example, the

dielectric layers

120, 130 may be formed by spin coating (spin coating), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma CVD (HDPCVD), other suitable methods, or combinations thereof.

With continued reference to fig. 1, in accordance with some embodiments of the present invention, the semiconductor structure 100 has a length direction X, a width direction Y, and a height direction Z. In the present embodiment, the direction toward the source structure is defined as the-Y direction, and the direction toward the drain structure is defined as the + Y direction.

With continued reference to fig. 1, according to some embodiments of the present invention, the gate metal layer 154 has a notch (notch)155 and exposes the underlying gate electrode 152 to improve switching speed. In other words, the dielectric layer 130 passes through the gap of the gate metal layer 154 and directly contacts the gate electrode 152. Compared with the comparative example in which the gate metal layer has no gap, the dielectric layer covering the gate metal layer in the embodiment of the present invention does not pass through the gate metal layer to contact the gate electrode.

In some embodiments, the notch 155 may be oriented in the direction of the source structure (-Y direction) from the top view to simultaneously reduce the gate-to-source capacitance (C)_gs) And gate to drain capacitance (C)_gd)。

Compared with the High Electron Mobility Transistor (HEMT) device of the comparative example, the field plate structure is disposed in the high electric field region of the semiconductor device to reduce the peak electric field (peak electric field) of the high electric field region. One of the field plates is a field plate connected to the source electrode (i.e., a source field plate), and the other is a field plate connected to the gate electrode (i.e., a gate field plate), both of which can reduce the electric field strength on the drain side of the gate electrode. However, the field plate structure is configured such that the gate-to-drain capacitance (C)_gd) And gate to source capacitance (C)_gs) A large rise, causing severe switching losses.

Therefore, some embodiments of the present invention may reduce the gate-to-source capacitance (C) by digging at least one gap 155 in the gate metal layer 154 to reduce the coverage of the gate field plate (gate metal layer 154) by the source field plate (source metal layer 146)_gs) While also reducing the gate field plate coverage of a two-dimensional electron gas (2DEG) (not shown) formed between the channel layer 114 and the barrier layer 116, and also reducing the gate-to-drain capacitance (C)_gd). In reducing input capacitance (C)_gs+C_gd) Meanwhile, the switching speed is increased, and the switching loss (switch loss) is also reduced. It is noted that the coverage of the gate metal layer 154 by the source metal layer 146 provided in the embodiments of the present invention is merely exemplary, which can be adjusted according to the actual product design and the required switching speed.

Reference is now made to fig. 2. FIG. 2 is a perspective view illustrating an exemplary partial semiconductor structure, according to some embodiments of the present invention. Fig. 2 is a perspective view of only the gate electrode 152 and the gate metal layer 154, and the X, Y, Z direction of fig. 1 is also applicable for convenience of describing the relative positions thereof. The gate metal layer 154 has a thickness T1 (in the Z direction), a maximum width WGM1, a minimum width WGM2 (in the Y direction), and a length L (in the X direction) on both sides of the gap 155. The gap 155 has a width WN (in the Y direction), and the gate electrode 152 has a width WG (in the Y direction).

In one embodiment, the minimum width WGM2 of the gate metal layer 154 is greater than or equal to the difference between the maximum width WGM1 of the gate metal layer 154 and the width WG of the gate electrode 152. That is, the width WN of the notch 155 is less than or equal to the width WG of the gate electrode 152. For example, the gate electrode 152 is 1 μm, and the width WG of the gap may be 1 μm, 0.5 μm, or 0.2 μm. When the width WN of the notch is larger than the width WG of the gate electrode, the breakdown voltage is likely to be lowered.

In one embodiment, the length L of the gate metal layer 154 on both sides of the gap 155 is greater than or equal to five times the thickness T1 of the gate metal layer 154. For example, the thickness T1 of the gate electrode 152 is 0.2 μm, and the length L of the gate metal layer 154 may be 1 μm, 1.5 μm, or 2 μm. In the case where the length L of the gate metal layer 154 on both sides of the notch 155 is less than five times the thickness T1 of the gate metal layer 154, the device is easily broken.

It should be understood that not all of the elements of the semiconductor structure 100 shown in fig. 1 are shown in fig. 2 for the sake of simplicity in describing embodiments of the present invention and highlighting features thereof.

Fig. 3 is a partial top projection view of a semiconductor structure corresponding to that shown in fig. 1, in accordance with some embodiments of the present invention. FIG. 3 also applies to the coordinates of FIG. 1, however, FIG. 3 is a plan view, and therefore has only X and Y directions. In a top view of the gate electrode 152 and the gate metal layer 154 projected onto the substrate 102, the gate metal layer 154 is U-shaped, and the gate metal layer 154 partially overlaps the gate electrode 152, as shown in fig. 3. The overlapping area of the gate metal layer 154 and the gate electrode 152 may occupy about 10%, about 30%, about 50%, about 70% of the area of the gate electrode 152 to reduce the input capacitance (C) while reducing the electric field strength_gs+C_gd)。

With continued reference to fig. 3. In some embodiments, the gap 155 exposes one side of the gate electrode 152, and the gap 155 is aligned with the other side of the gate electrode 152 (align), i.e., the width WN of the gap is the same as the width WG of the gate electrode, and the gap faces the-Y direction. In some embodiments, the gate metal layers 154 on both sides of the gap 155 may have the same shape, that is, the gate metal layers 154 are symmetrical with respect to a middle line of the gate metal layers 154 in the length direction (in the X direction). In some embodiments, the gate metal layers 154a on both sides of the gap 155 may have a rectangular profile, that is, the gap 155 may be rectangular. In the embodiment shown in fig. 3, the width WN of the gap can be adjusted according to the actual product design and the required switching speed, so that the areas of the gate electrodes exposed by the gap are different.

Fig. 4-11 are partial top plan views illustrating semiconductor structures according to other embodiments of the present invention. Fig. 4-11 also apply to the coordinates in fig. 3, having an X direction and a Y direction (not shown). In the top view of the gate electrode 152 and the gate metal layer 154 projected onto the substrate 102, the gate metal layer 154 may have two notches 155 as shown in fig. 4, or four notches 155 as shown in fig. 5. The gate metal layer 154 may also be comb-shaped (comb shape), as shown in fig. 5. It should be noted that although only a limited number of notches are shown in fig. 4 and 5, the number of notches can be modified according to actual requirements, and is not limited thereto.

In some embodiments, the plurality of gaps 155 of the gate metal layer 154 may have the same shape and size as each other, as shown in fig. 4, or may have different shapes and sizes, as shown in fig. 6. That is, the size of the gap can be adjusted according to the actual situation to adjust the switching speed. In detail, the larger the size of the notch in the width direction is, the larger the input capacitance (C)_gs+C_gd) The faster the switching speed.

In some embodiments, the gate metal layers 154 on both sides of the gap 155 on the gate electrode 152 may have an arc profile or a trapezoidal profile, as shown in fig. 7. In some embodiments, the notch 155 can be triangular, as shown in FIG. 8, or the notch 155 can be trapezoidal, as shown in FIG. 9. The area and shape of the gate electrode exposed from the notch further affect the shape and area of the gate metal layers on two sides of the notch, so that the adjustment can be performed according to the actual product design and the required switching speed.

In some embodiments, the gap 155 may vary linearly along the gate electrode, that is, the width of the gate metal layer may vary linearly along the extension direction of the gate electrode, as shown in fig. 9, so that the width of the gate metal layer may be different in different electron flow directions in the semiconductor structure, and the C may be reduced_gdMeanwhile, the excessive rise of the gate resistance (Rg) is inhibited, and the switching speed of the element is further improved.

In some embodiments, portions of the gate metal layer 154 on both sides of the gap 155 extend beyond the gate electrode 152, as shown in fig. 10. The area of the gate metal layer on both sides of the gap beyond the gate electrode may be 1 times the area of the gate metal layer overlapping the gate electrode (confirmed). The area of the gate metal layer beyond the gate electrode can be adjusted to achieve the desired switching speed.

In some embodiments, the gap 155 exposes one side of the gate electrode 152 and the gap 155 covers the other side of the gate electrode 152, i.e. the width of the gap 155 is smaller than the width of the gate electrode 152, as shown in fig. 11, when C is decreased_gdMeanwhile, the excessive rise of the gate resistance (Rg) is inhibited, and the switching speed of the element is further improved.

It should be understood that all elements of the semiconductor structure 100 shown in fig. 1 are not shown in fig. 3-11 for the sake of simplicity and clarity in describing the embodiments and highlighting the technical features thereof.

FIG. 12 is a cross-sectional view taken along line A-A' of the semiconductor structure of FIG. 1, in accordance with some embodiments of the present invention. FIG. 12 also applies to the coordinates of FIG. 1, however, FIG. 12 is a plan view and therefore has only Y and Z directions. In the embodiment shown in fig. 12, the source metal layer 146 extends to the drain structure 160(+ Y direction), and the source metal layer 146 extends beyond the gate metal layer 154, so as to optimize the electric field distribution and effectively reduce the electric field strength of the gate electrode on the drain side.

Please refer to fig. 13 to fig. 15. Fig. 13 is a partial perspective view illustrating an exemplary semiconductor structure according to other embodiments of the present invention, and fig. 14 is a cross-sectional view illustrating a line B-B' corresponding to the semiconductor structure shown in fig. 13 according to other embodiments of the present invention. FIG. 15 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention.

FIG. 13 also applies to the X, Y, Z orientation of FIG. 1, and FIGS. 14 and 15 also apply to the Y, Z orientation of FIG. 12, for ease of describing their relative positions.

The semiconductor structure 200 depicted in fig. 13 is substantially similar to the semiconductor structure 100 of fig. 1, with the difference that the source metal layer 146 in the semiconductor structure 200 has an opening 147 to further reduce the gate-to-source capacitance (C)_gs). In the cross-sectional views shown in fig. 14 and 15, the opening 147 in the source metal layer 146 has a width WO1, the gate electrode 152 has a width WG, and the gate metal layer 154 has a width WGM 2.

In some embodiments, since the side of the gate electrode 152 facing the drain structure 160(+ Y direction) is adjacent to the side of the gate metal layer 154 facing the source structure 140(-Y direction), the width of the opening 147 may be less than the sum of the width WG of the gate electrode 152 and the width WGM2 of the gate metal layer 154, as shown in fig. 14. In this embodiment, the projections of the source metal layer 146, the gate metal layer 154 and the gate electrode 152 on the substrate 102 are such that the source metal layer 146 partially overlaps the gate metal layer 154 and the gate electrode 152, respectively. In other embodiments, the width of the opening 147 may be greater than the sum (not shown) of the width WG of the gate electrode 152 and the width WGM2 of the gate metal layer 154.

Since the gap 155 of the gate metal layer 154 exposes the gate electrode 152, the source-to-gate capacitance (C) is reduced_gs) The opening 147 of the source metal layer 146 further reduces the area covered by the source metal layer 146 and the gate structure 150, thereby further reducing the source-to-gate capacitance (C)_gs) To adjust the switching speed.

In other embodiments, the width WO1 of the opening 147 may be equal to the sum of the width WG of the gate electrode 152 and the width WGM2 of the gate metal layer 154, as shown in FIG. 15. In this embodiment, both sides of the opening 147 are substantially aligned with the gate metal layer 154 toward the drainOne side of the pole structure 160(+ Y direction) and one side of the gate electrode 152 facing the source structure 140(-Y direction). That is, the projections of source metal layer 146 and gate metal layer 154 and gate electrode 152 on substrate 102 are aligned (align) with openings WO1 and gate metal layer 154 and gate electrode 152 to further reduce gate-to-source capacitance (C)_gs)。

By forming an opening in the source metal layer and adjusting the size of the opening according to actual requirements, the capacitance (C) from the source to the gate can be further reduced_gs) To adjust the switching speed.

Fig. 16 is a partial perspective view illustrating an exemplary semiconductor structure according to further embodiments of the present invention. FIG. 16 also applies to the X, Y, Z orientation of FIG. 1 to facilitate description of its relative position.

The semiconductor structure 300 depicted in fig. 16 is substantially similar to the semiconductor structure 100 of fig. 1, with the difference that an additional source metal layer 148 is also included in the semiconductor structure 300. Specifically, the semiconductor structure 300 further includes a dielectric layer 170 on the source metal layer 146 and the dielectric layer 130, and a source metal layer 148 on the dielectric layer 170.

In some embodiments, the source metal layer 148 may serve as an additional source field plate and is electrically connected to the source electrode 142 and the source metal layer 146 by the source contact 144. The source metal layers 146, 148 electrically connected to the source electrode 142 have a different potential than the gate metal layer 154 electrically connected to the gate electrode 152. In this embodiment, the side of the gate electrode 152 facing the drain structure 160(+ Y direction) is adjacent to the side of the gate metal layer 154 facing the source structure 140(-Y direction), and the width of the additional source metal layer 148 is greater than the width of the source metal layer 146, i.e., the additional source metal layer 148 may completely cover the source metal layer 146.

Since the gap 155 of the gate metal layer 154 exposes the gate electrode, the source-to-gate capacitance (C) is reduced_gs) The extra source metal layer 148 further reduces the electric field strength, thereby reducing the input capacitance (C)_gs+C_gd) The risk of the gate structure being subjected to high electric fields is reduced.

In other embodiments, the width of the additional source metal layer 148 may be smaller than the width of the source metal layer 146 (not shown), or equal to the width of the source metal layer 146 (not shown). By providing an additional source metal layer, the electric field strength and the input capacitance can be reduced. It should be noted that although only one additional source metal layer 148 is illustrated in the embodiments of the present invention, the number and size of the additional source metal layer may be adjusted according to the actual product design and the required switching speed, and is not limited thereto.

Please refer to fig. 17 and fig. 18. Fig. 17 is a partial perspective view illustrating an exemplary semiconductor structure according to further embodiments of the present invention, and fig. 18 is a cross-sectional view illustrating a line C-C' corresponding to the semiconductor structure shown in fig. 1 according to further embodiments of the present invention. FIG. 17 also applies to the X, Y, Z orientation of FIG. 1, and FIG. 18 also applies to the Y, Z orientation of FIG. 12, for ease of describing the relative positions.

The semiconductor structure 400 depicted in fig. 17 is substantially similar to the semiconductor 100 of fig. 1, with the difference that the source metal layer 146 has an opening 147 and the additional source metal layer 148 also has an opening 149 in the semiconductor structure 400 to further reduce the gate-to-source capacitance (C)_gs). Specifically, the semiconductor structure 400 includes a source metal layer 146 having an opening 147, a dielectric layer 170 disposed on the source metal layer 146 and the dielectric layer 130, and a source metal layer 148 disposed on the dielectric layer 170 and having an opening 149. In the cross-sectional view of fig. 18, the opening 147 in the source metal layer 146 has a width WO1, the opening 149 in the additional metal layer 148 has a width WO2, and the gate electrode 152 has a width WG and the gate metal layer 154 has a width WGM 2.

In some embodiments, the width of opening 149 may be less than the width of opening 147, as shown in FIG. 18. In this embodiment, the side of the gate electrode 152 facing the drain structure 160 is adjacent to the side of the gate metal layer 154 facing the source structure 140, and the projection of the source metal layer 146 and the additional source metal layer 148 on the substrate 102 is completely overlapped. The description of the gate electrode 152 and the gate metal layer 154 is similar to that of fig. 13-15, and will not be repeated herein.

Since the gap 155 of the gate metal layer 154 exposes the gate electrode, the source-to-gate capacitance (C) is reduced_gs) The source metal layer with opening further reduces the source-to-gate capacitance (C)_gs) The extra source metal layer 148 with the opening further reduces the electric field strength and reduces the source-to-gate capacitance (C)_gs) Thus, the input capacitance (C) can be reduced_gs+C_gd) While reducing the risk of the gate structure being subjected to high electric fields.

The opening can be arranged on the source metal layer, the additional source metal layer is arranged, and the opening is arranged on the additional source metal layer at the same time, so that the electric field intensity is further reduced. It should be noted that although only the source metal layer 146 having the opening 147 and the source metal layer 148 having the opening 149 are illustrated in the embodiments of the present invention, the number and size of the source metal layers and the number and size of the openings in the source metal layers can be adjusted according to the actual product design and the required switching speed, which is not limited thereto.

It is to be noted that, in the semiconductor structure provided by the embodiment of the present invention, the number and size of the notches of the gate metal layer, the number and size of the source metal layer, and the number, size, and shape of the openings included in the source metal layer and located above the gate metal layer and the gate electrode are not limited to the above-mentioned embodiments. For example, various polygonal (e.g., pentagonal, hexagonal, or octagonal), circular, or irregular arc-shaped gaps or/openings may also be applied to the semiconductor structure provided by the embodiments of the present invention. The number, size, and shape of the notches and/or openings described in the various embodiments above may be integrated into a single semiconductor structure to adjust the degree of coverage of the gate metal layer as a gate field plate by the source metal layer as a gate field plate and the degree of coverage of the two-dimensional electron gas (2DEG) by the gate metal layer as a gate field plate, depending on the actual product design and the desired switching speed.

In summary, the embodiments of the present invention provide a half-shellThe conductor structure can reduce the risk of high electric field of the grid structure by the grid field plate, optimize electric field distribution by the source field plate, and reduce the grid-to-drain capacitance (C)_gd) Furthermore, the gate-to-source capacitance (C) can be reduced by forming a gap in the gate metal layer to adjust the coverage of the gate field plate with the source field plate and the coverage of the gate field plate with the two-dimensional electron gas (2DEG) simultaneously_gs) And gate to drain capacitance (C)_gd) Further, the purpose of reducing the switch loss is achieved. Therefore, the semiconductor structure provided by the embodiment of the invention has a breakdown voltage (breakdown voltage) and an input capacitance (C)_gs+C_gd) The switching loss can be effectively reduced by good balance between the two, and the efficiency of the semiconductor structure is further improved.

The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, comprising:

a substrate;

a gate structure on the substrate, wherein the gate structure comprises:

a gate electrode on the substrate; and

a gate metal layer on the gate electrode, wherein the gate metal layer has at least one gap exposing the gate electrode below; and

and the drain electrode structure and the source electrode structure are arranged on two sides of the grid electrode structure, wherein the potential of the grid electrode structure is different from that of the source electrode structure.

2. The semiconductor structure of claim 1, wherein the notch is oriented in a direction of the source structure.

3. The semiconductor structure of claim 1, wherein the gate metal layer on both sides of the gap has an arc profile, a rectangular profile, or a trapezoidal profile.

4. The semiconductor structure of claim 1, wherein the notch is rectangular, trapezoidal, or triangular.

5. The semiconductor structure of claim 1, wherein a width of the gate metal layer varies linearly with an extending direction of the gate electrode.

6. The semiconductor structure of claim 1, wherein portions of the gate metal layer on either side of the gap extend beyond the gate electrode.

7. The semiconductor structure of claim 1, wherein the gap exposes a first side of the gate electrode and covers a second side of the gate electrode opposite the first side.

8. The semiconductor structure of claim 1, wherein the indentation exposes a first side of the gate electrode and is aligned with a second side of the gate electrode opposite the first side.

9. The semiconductor structure of claim 1, wherein the length of the gate metal layer on both sides of the gap is greater than or equal to five times the thickness of the gate metal layer.

10. The semiconductor structure of claim 1, wherein the source structure comprises:

a source electrode on the substrate; and

and the source metal layer is arranged on the source electrode and is electrically connected with the source electrode.

11. The semiconductor structure of claim 10, wherein the source metal layer extends toward the drain structure and beyond the gate metal layer.

12. The semiconductor structure of claim 10, wherein the source metal layer has at least one opening.

13. The semiconductor structure of claim 10, wherein the source structure further comprises another source metal layer on the source metal layer, and the another source metal layer is electrically connected to the source electrode.

14. The semiconductor structure of claim 13, wherein the another source metal layer extends toward the drain structure and beyond the source metal layer.

15. The semiconductor structure of claim 13, wherein the another source metal layer has at least one opening.

16. The semiconductor structure of claim 15, wherein the width of the opening of the another source metal layer is less than the width of an opening of the source metal layer.

17. A semiconductor structure, comprising:

a substrate;

a gate structure on the substrate, wherein the gate structure comprises:

a gate electrode on the substrate; and

a gate metal layer on the gate electrode; and

a drain structure and a source structure on both sides of the gate structure, wherein the gate metal layer is U-shaped and partially overlaps the gate electrode in a top view of the gate electrode and the gate metal layer projected onto the substrate.

18. The semiconductor structure of claim 17, further comprising an interlayer dielectric layer over the gate electrode, wherein the interlayer dielectric layer passes through the gate metal layer and contacts the gate electrode.

19. The semiconductor structure of claim 17, wherein the gate metal layer is comb-shaped.

20. The semiconductor structure of claim 17, wherein the gate metal layer is symmetrical about a lengthwise centerline of the gate metal layer.