CN112951714A

CN112951714A - Semiconductor structure and forming method thereof

Info

Publication number: CN112951714A
Application number: CN201911260433.XA
Authority: CN
Inventors: 刘长宇; 韩亮
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-12-10
Filing date: 2019-12-10
Publication date: 2021-06-11

Abstract

A semiconductor structure and a method for forming the same, the forming method comprises: providing a substrate, the substrate comprising a first region and a second region adjacent to each other; forming a floating gate layer on the substrate of the first region and the substrate of the second region; A hard mask layer is formed on the floating gate layer, and the top of the hard mask layer in the first region is lower than the top of the hard mask layer in the second region; on the hard mask layer in the first region and the hard mask layer in the second region forming a first oxide layer on it; etching the first oxide layer, the hard mask layer, the floating gate layer and the substrate, forming a plurality of first grooves in the first area, and forming a plurality of second grooves in the second area ; Form a second oxide layer filling the first groove and the second groove; Etch the second oxide layer and the first oxide layer until the top surface of the hard mask layer in the second region is exposed, and the first oxide layer remains layer covers the top of the hard mask layer in the first region. The present invention helps to improve the uniformity of the top surface height of the second oxide layer in each of the first grooves.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.

Background

At present, Flash Memory (Flash), also called Flash Memory, has become the mainstream of Non-volatile Memory (NVM). Flash memories are classified into Nor Flash (Nor Flash) and NAND Flash (NAND Flash) according to their structures. The flash memory has the main characteristics of capability of keeping stored information for a long time under the condition of no power-on, and has the advantages of high integration level, high storage speed, easy erasing and rewriting and the like, so the flash memory is widely applied to the fields of microcomputer, automatic control and the like.

NAND flash memory devices have higher cell density, higher storage density, faster writing and erasing speed, and become a structure of flash memory, and are mainly used in flash memory cards of digital cameras and MP3 players.

However, the performance of NAND flash memory devices is still in need of improvement.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which are beneficial to improving the consistency of the top surface height of a second oxide layer in each first groove and increasing the read-write times of a NAND flash memory device.

To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first area and a second area which are adjacent; forming floating gate layers on the substrate of the first region and the substrate of the second region; forming a hard mask layer on the floating gate layer, wherein the top of the hard mask layer in the first area is lower than that of the hard mask layer in the second area; forming a first oxide layer on the hard mask layer of the first area and the hard mask layer of the second area; etching the first oxide layer, the hard mask layer, the floating gate layer and the substrate, forming a plurality of first grooves in the first area, and forming a plurality of second grooves in the second area; forming a second oxide layer filling the first groove and the second groove; and etching the second oxide layer and the first oxide layer until the top surface of the hard mask layer of the second area is exposed, and remaining the first oxide layer to cover the top of the hard mask layer of the first area.

Optionally, the second oxide layer is made of the same material as the first oxide layer.

Optionally, the second oxide layer and the first oxide layer are etched by a chemical mechanical polishing process.

Optionally, a difference between the top of the hard mask layer in the first region and the top of the hard mask layer in the second region is

Optionally, before forming the floating gate layer, the method further includes: and forming gate oxide layers on the surfaces of the substrate of the first area and the substrate of the second area.

Optionally, before the floating gate layer is formed, the top of the gate oxide layer of the first region is flush with the top of the gate oxide layer of the second region.

Optionally, the process for forming the hard mask layer includes: forming an initial hard mask layer on the floating gate layer by adopting a chemical vapor deposition process; forming a photoresist layer on the top of the initial hard mask layer in the second area; etching and removing part of the initial hard mask layer with the thickness of the first area to form a hard mask layer; and removing the photoresist layer.

Optionally, the second region includes a middle region and an edge region, and the middle region is located between the first region and the edge region; in the process of forming the gate oxide layer, the top of the gate oxide layer of the first area is flush with the top of the gate oxide layer of the middle area, and the top of the gate oxide layer of the middle area is lower than the top of the gate oxide layer of the edge area.

Optionally, the thickness of the gate oxide layer in the first region and the thickness of the gate oxide layer in the middle region are both first thicknesses, the thickness of the gate oxide layer in the edge region is a second thickness, and the first thickness is smaller than the second thickness.

Optionally, the gate oxide layer includes a first sub-gate oxide layer and a second sub-gate oxide layer, the gate oxide layer of the first region and the gate oxide layer of the middle region serve as the first sub-gate oxide layer, and the gate oxide layer of the edge region serves as the second sub-gate oxide layer; the forming process of the gate oxide layer comprises the following steps: forming a first insulating layer on top of the substrate in the first and intermediate regions; etching the substrate of the edge area with partial thickness; performing first oxidation treatment on the top surface of the substrate in the edge region to form the second sub-gate oxide layer; removing the first insulating layer; forming a second insulating layer on the top of the substrate in the edge region, wherein the second insulating layer exposes the first region and the top of the substrate in the middle region; and carrying out second oxidation treatment on the surface of the top of the substrate exposed by the second insulating layer to form the first sub-gate oxide layer.

Optionally, the difference between the top of the gate oxide layer in the first region and the top of the gate oxide layer in the edge region is

Optionally, the floating gate layer is formed by a furnace tube process.

Optionally, the hard mask layer is formed by a furnace tube process or a chemical vapor deposition process.

Accordingly, the present invention also provides a semiconductor structure comprising: the substrate comprises a first area and a second area which are adjacent; the floating gate layer is positioned on the substrate of the first area and the substrate of the second area; the hard mask layer is positioned on the floating gate layer, and the top of the hard mask layer in the first area is lower than that of the hard mask layer in the second area; the first oxidation layer covers the top of the hard mask layer of the first area; a first groove located within the first region; a second groove located within the second region; a second oxide layer filling the first and second recesses.

Compared with the prior art, the technical scheme of the invention has the following advantages:

because the top of the hard mask layer in the first area is lower than the top of the hard mask layer in the second area, in the process of etching the second oxide layer and the first oxide layer, the top surface of the hard mask layer in the second area can be used as an etching stop surface of the etching process, so that the consistency of the heights of the top surfaces of the second oxide layers in the first grooves is improved, and the phenomenon that the height difference of the top surfaces of the second oxide layers in the first grooves is overlarge after the etching process is finished is avoided. The consistency of the top surface height of the second oxide layer in each first groove is good, which is beneficial to improving the uniformity of the starting voltage in each byte in the first area and increasing the read-write times of the NAND flash memory device.

Drawings

Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;

FIGS. 4 to 12 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 13 to fig. 20 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As is known in the art, the performance of the conventional semiconductor structure is still to be improved.

Now, an analysis is performed in combination with a method for forming a semiconductor structure, and fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in the method for forming a semiconductor structure, where the steps of the process for forming a semiconductor structure mainly include:

referring to fig. 1, a substrate 10 is provided, the substrate 10 comprising a first region i and a second region ii adjacent to each other; forming a floating gate layer 30 on the substrate 10 of the first region i and the substrate 10 of the second region ii; a hard mask layer 50 is formed on the floating gate layer 30, and the top of the hard mask layer 50 in the first region i is flush with the top of the hard mask layer 50 in the second region ii.

Wherein the first area i is a cell (cell) and the second area ii is a peripheral area (periphery).

Referring to fig. 2, the hard mask layer 50, the floating gate layer 30 and the substrate 10 are etched to form a plurality of first grooves 71 in the first region i and a plurality of second grooves 72 in the second region ii, wherein the width of the second grooves 72 is greater than that of the first grooves 71; and forming an oxide layer 60 which fills the first groove 71 and the second groove 72, wherein the oxide layer 60 covers the top of the hard mask layer 50.

Referring to fig. 3, the oxide layer 60 covering the top of the hard mask layer 50 is removed using a chemical mechanical polishing process.

Since the hard mask layer 50 and the oxide layer 60 are made of different materials, the hard mask layer 50 and the oxide layer 60 have different polishing rates during the chemical mechanical polishing process. The hard mask layer 50 and the oxide layer 60 with different grinding rates are ground simultaneously, so that after the chemical mechanical grinding process is finished, the oxide layer 60 in the first groove 71 and the second groove 72 is in a disc-shaped opening shape, the depths of disc-shaped openings formed by the oxide layer 60 in different first grooves 71 are different, and the height difference of the top surface of the oxide layer 60 in each first groove 71 is large. The difference in the height of the top surface of the oxide layer 60 in each first groove 71 is large, so that the uniformity of the turn-on Voltage (VT) in each byte (bit) in the first region i is poor, and the read-write frequency of the NAND flash memory device is affected.

The inventors have studied the forming method of the semiconductor structure, and as a result of creative work, the inventors have noticed that, in the process of forming the hard mask layer, the top of the hard mask layer in the first region is lower than the top of the hard mask layer in the second region, and in the chemical mechanical polishing process, by stopping polishing on the top of the hard mask layer in the second region, the hard mask layer in the first region can be prevented from being polished, which is helpful for improving the uniformity of the top surface of the second oxide layer in each of the first grooves.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 4 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to fig. 4, a substrate 100 is provided, wherein the substrate 100 includes a first region i and a second region ii adjacent to each other.

The substrate 100 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 100 may also be a silicon substrate on an insulator or a germanium substrate on an insulator; in this embodiment, the substrate 100 is a silicon substrate.

In this embodiment, the top of the substrate 100 of the first zone i is flush with the top of the substrate 100 of the second zone ii.

In this embodiment, the first area i is a cell (cell), and the second area ii is a peripheral area (periphery).

Referring to fig. 5, a floating gate layer 300 is formed on the substrate 100 of the first region i and the substrate 100 of the second region ii.

In this embodiment, the top of the floating gate layer 300 of the first zone i is flush with the top of the floating gate layer 300 of the second zone ii.

In this embodiment, before forming the floating gate layer 300, the method further includes: and forming a gate oxide layer 200 on the surface of the substrate 100 in the first area I and the substrate 100 in the second area II.

The gate oxide layer 200 is made of silicon oxide or germanium oxide. In this embodiment, the gate oxide layer 200 is made of silicon oxide.

In this embodiment, before the floating gate layer 300 is formed, the top of the gate oxide layer 200 of the first region i is flush with the top of the gate oxide layer 200 of the second region ii.

In this embodiment, the material of the floating gate layer 300 is polysilicon.

Referring to fig. 6 to 8, a hard mask layer 500 is formed on the floating gate layer 300, and the top of the hard mask layer 500 of the first region i is lower than the top of the hard mask layer 500 of the second region ii.

The process of forming the hard mask layer 500 includes: as shown in fig. 6, an initial hard mask layer 510 is formed on the floating gate layer 300 by using a chemical vapor deposition process; forming a photoresist layer 520 on the top of the initial hard mask layer 510 in the second region II; as shown in fig. 7, etching to remove a portion of the initial hard mask layer 510 in the first region i to form a hard mask layer 500; as shown in fig. 8, the photoresist layer 520 is removed.

In this embodiment, the initial hard mask layer 510 is made of silicon nitride. In other embodiments, the material of the initial hard mask layer 510 is silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.

In this embodiment, after the initial hard mask layer 510 is formed by a chemical vapor deposition process and before the photoresist layer 520 is formed, the method further includes: and carrying out planarization treatment on the initial hard mask layer 510, so that the top of the initial hard mask layer 510 of the first area I is flush with the top of the initial hard mask layer 510 of the second area II.

Wherein, the initial hard mask layer 510 is planarized by a chemical mechanical polishing process.

The photoresist layer 520 is used to protect the top surface of the initial hard mask layer 510 in the second region ii, so that the etching process only etches and removes a portion of the thickness of the initial hard mask layer 510 in the first region i, and the top of the initial hard mask layer 510 in the first region i is lower than the top of the initial hard mask layer 510 in the second region ii, thereby forming the hard mask layer 500.

The top of the hard mask layer 500 in the first area i is lower than the top of the hard mask layer 500 in the second area ii, and the top surface of the hard mask layer 500 in the second area ii can be used as an etching stop layer to prevent the etching process from etching the top surface of the hard mask layer 500 in the first area i.

In this embodiment, a dry etching process is used to form the initial hard mask layer 510 with a portion of the thickness of the first region i removed by etching. In other embodiments, the initial hard mask layer 510 is formed by a wet etching process to etch away a portion of the thickness of the first region i.

In this embodiment, the difference between the top of the hard mask layer 500 in the first region i and the top of the hard mask layer 500 in the second region ii is

If the difference between the top of the hard mask layer 500 in the first region I and the top of the hard mask layer 500 in the second region II is too largeAnd small, the effect of the difference on protecting the top surface of the hard mask layer 500 in the first region i is affected. If the difference between the top of the hard mask layer 500 in the first area i and the top of the hard mask layer 500 in the second area ii is too large, the height of the hard mask layer 500 in the second area ii is too high, and the risk of toppling over of the hard mask layer 500 in the second area ii is increased.

In this embodiment, before forming the hard mask layer 500, the method further includes: and forming an adhesion layer 400 on the surfaces of the floating gate layer 300 in the first region I and the floating gate layer 300 in the second region II.

The adhesion layer 400 is used to improve the bonding force between the hard mask layer 500 and the floating gate layer 300, and prevent a gap from occurring between the surface of the hard mask layer 500 and the surface of the floating gate layer 300.

In this embodiment, the material of the adhesion layer 400 is silicon oxide.

In this embodiment, the top of the adhesive layer 400 of the first zone i is flush with the top of the adhesive layer 400 of the second zone ii.

Referring to fig. 9, a first oxide layer 610 is formed on the first region i of the hard mask layer 500 and on the second region ii of the hard mask layer 500.

In this embodiment, the material of the first oxide layer 610 is silicon oxide. In other embodiments, the material of the first oxide layer 610 is germanium oxide.

In this embodiment, the forming process of the first oxide layer 610 includes: forming a first oxide film by adopting a chemical vapor deposition process; and carrying out planarization treatment on the first oxide film to form the first oxide layer 610, wherein the top of the first oxide layer 610 of the first area I is flush with the top of the first oxide layer 610 of the second area II.

And carrying out planarization treatment on the first oxide film by adopting a chemical mechanical polishing process.

Referring to fig. 10, the first oxide layer 610, the hard mask layer 500, the floating gate layer 300 and the substrate 100 are etched to form a plurality of first grooves 710 in the first region i and a plurality of second grooves 720 in the second region ii.

The first recess 710 serves as an isolation trench for the first region i.

In this embodiment, the width L1 of the first groove 710 is smaller than the width L2 of the second groove 720. The distance between adjacent first grooves 710 is smaller than the distance between adjacent second grooves 720. The density of the first grooves 710 in the first zone i is greater than the density of the second grooves 720 in the second zone ii.

In this embodiment, the first recess 710 and the second recess 720 are formed in the same process step.

In this embodiment, the first groove 710 and the second groove 720 are formed by a wet etching process. In other embodiments, the first groove 710 and the second groove 720 are formed by a dry etching process.

In this embodiment, the etching process for forming the first recess 710 and the second recess 720 consumes a portion of the thickness of the first oxide layer 610, so that the thickness of the first oxide layer 610 is reduced before and after the formation of the first recess 710 and the second recess 720 (refer to fig. 9).

Referring to fig. 11, a second oxide layer 620 is formed to fill the first recess 710 and the second recess 720.

In this embodiment, the material of the second oxide layer 620 is silicon oxide.

In this embodiment, the second oxide layer 620 covers the top of the first oxide layer 610 in the first region i and the top of the first oxide layer 610 in the second region ii.

In this embodiment, the second oxide layer 620 is formed by a chemical vapor deposition process.

Referring to fig. 12, the second oxide layer 620 and the first oxide layer 610 are etched until the top surface of the hard mask layer 500 of the second region ii is exposed, and the first oxide layer 610 is left to cover the top of the hard mask layer 500 of the first region i.

Because the top of the hard mask layer 500 in the first region i is lower than the top of the hard mask layer 500 in the second region ii, in the process of etching the second oxide layer 620 and the first oxide layer 610, the top surface of the hard mask layer 500 in the second region ii can be used as an etching stop surface, so that the top surface of the hard mask layer 500 in the first region i is prevented from being etched.

Since the etching process is stopped immediately after the top surface of the hard mask layer 500 of the second region ii is exposed, the top of the hard mask layer 500 of the first region i is still covered with the first oxide layer 610 with a certain thickness, and the first oxide layer 610 on the top surface of the hard mask layer 500 of the second region ii is completely etched away. Since the first oxide layer 610 and the second oxide layer 620 are made of the same material, the first oxide layer 610 and the second oxide layer 620 have the same etching rate in the etching process. After the etching process is finished, the top surface of the first oxide layer 610 is substantially flush with the top surface of the second oxide layer 620 in the first grooves 710, so that the uniformity of the height of the top surface of the second oxide layer 620 in each first groove 710 is improved. The consistency of the top surface height of the second oxide layer 620 in each first groove 710 is good, which is helpful to improve the uniformity of the turn-on voltage in each byte in the first region and increase the read-write times of the NAND flash memory device.

In this embodiment, a chemical mechanical polishing process is used to etch the second oxide layer 620 and the first oxide layer 610.

Referring to fig. 13, a substrate 100 is provided, wherein the substrate 100 includes a first region i and a second region ii adjacent to each other.

In this embodiment, the second region ii includes a middle region iii and an edge region iv, and the middle region iii is located between the first region i and the edge region iv.

And subsequently forming a semiconductor structure, wherein the applied voltage values of the first region I and the middle region III are first voltages, the applied voltage value of the edge region IV is a second voltage, and the first voltage is less than the second voltage.

Referring to fig. 14, a gate oxide layer 200 is formed on the surface of the substrate 100 of the first region i, the substrate 100 of the middle region iii and the substrate 100 of the edge region iv, the top of the gate oxide layer 200 of the first region i is flush with the top of the gate oxide layer 200 of the middle region iii, and the top of the gate oxide layer 200 of the middle region iii is lower than the top of the gate oxide layer 200 of the edge region iv.

In this embodiment, the thickness of the gate oxide layer 200 in the first region i is a first thickness d 1. The thickness of the gate oxide layer 200 of the middle area III is also the first thickness d 1. The thickness of the gate oxide layer 200 of the edge region iv is a second thickness d2, and the first thickness d1 is smaller than the second thickness d 2.

In this embodiment, the difference between the second thickness d2 and the first thickness d1 is

In this embodiment, the gate oxide layer 200 includes a first sub-gate oxide layer 210 with the first thickness d1 and a second sub-gate oxide layer 220 with the second thickness d 2.

In this embodiment, the gate oxide layer 200 of the first region i and the gate oxide layer 200 of the middle region iii are used as the first sub-gate oxide layer 210, and the gate oxide layer 200 of the edge region iv is used as the second sub-gate oxide layer 220.

The forming process of the gate oxide layer 200 comprises the following steps: forming a first insulating layer (not shown) on top of the substrate 100 in the first region i and the intermediate region iii; etching the substrate 100 with partial thickness of the edge region IV; performing first oxidation treatment on the top surface of the substrate 100 in the edge region iv to form the second sub-gate oxide layer 220; removing the first insulating layer; and performing a second oxidation process on the top surface of the substrate 100 exposed by the second insulating layer to form the first sub-gate oxide layer 210.

In this embodiment, the first insulating layer is made of silicon nitride. In other embodiments, the material of the first insulating layer is silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.

The second insulating layer is made of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride. In this embodiment, the second insulating layer is made of silicon nitride.

In this embodiment, the first oxidation treatment and the second oxidation treatment are performed in steps, and the process time of the first oxidation treatment and the process time of the second oxidation treatment are controlled to make the process time of the second oxidation treatment longer than the process time of the first oxidation treatment, so as to ensure that the thickness of the second sub-gate oxide layer 220 is greater than that of the first sub-gate oxide layer 210, and further to make the top of the gate oxide layer 200 in the edge area iv higher than the top of the gate oxide layers 200 in the first area i and the middle area iii.

Referring to fig. 15, a floating gate layer 300 is formed on the surfaces of the gate oxide layer 200 in the first region i, the gate oxide layer 200 in the middle region iii, and the gate oxide layer 200 in the edge region iv.

In this embodiment, the top of the floating gate layer 300 in the edge region iv is higher than the top of the floating gate layer 300 in the first region i and the middle region iii.

In this embodiment, the material of the floating gate layer 300 is polysilicon.

In this embodiment, the floating gate layer 300 is formed by a furnace process.

The furnace tube process is adopted to form the floating gate layer 300, which is beneficial to ensuring that the thicknesses of the floating gate layer 300 in the first zone I, the middle zone III and the edge zone IV are consistent, so that the top of the floating gate layer 300 in the edge zone IV is higher than the tops of the floating gate layer 300 in the first zone I and the middle zone III.

Referring to fig. 16, a hard mask layer 500 is formed on the floating gate layer 300, and the top of the hard mask layer 500 in the edge region iv is higher than the top of the hard mask layer 500 in the first region i and the middle region iii.

In this embodiment, the hard mask layer 500 is made of silicon nitride. In other embodiments, the material of the hard mask layer 500 is silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.

In this embodiment, the hard mask layer 500 is formed by a furnace process. In other embodiments, the hard mask layer 500 may also be formed by a chemical vapor deposition process.

The hard mask layer 500 is formed by the furnace tube process, which is helpful for ensuring that the thicknesses of the hard mask layer 500 in the first region i, the middle region iii and the edge region iv are consistent, so that the top of the hard mask layer 500 in the edge region iv is higher than the tops of the hard mask layer 500 in the first region i and the middle region iii.

In this embodiment, before forming the hard mask layer 500, the method further includes: and forming adhesion layers (not shown) on the surfaces of the floating gate layer 300 of the first region I and the floating gate layer 300 of the second region II, wherein the top of the adhesion layer 400 of the edge region IV is higher than that of the adhesion layers of the first region I and the middle region III.

The subsequent top surface of the hard mask layer 500 in the second region ii may be used as an etching stop layer to prevent the etching process from etching the top surface of the hard mask layer 500 in the first region i.

Referring to fig. 17, a first oxide layer 610 is formed on the first region i of the hard mask layer 500 and on the second region ii of the hard mask layer 500.

Referring to fig. 18, the first oxide layer 610, the hard mask layer 500, the floating gate layer 300 and the substrate 100 are etched to form a plurality of first grooves 710 in the first region i and a plurality of second grooves 720 in the second region ii.

In this embodiment, the width L1 of the first groove 710 is smaller than the width L2 of the second groove 720.

Referring to fig. 19, a second oxide layer 620 is formed to fill the first recess 710 and the second recess 720.

Referring to fig. 20, the second oxide layer 620 and the first oxide layer 610 are etched until the top surface of the hard mask layer 500 of the second region ii is exposed, and the first oxide layer 610 is left to cover the top of the hard mask layer 500 of the first region i.

In the process of etching the second oxide layer 620 and the first oxide layer 610, the top surface of the hard mask layer 500 in the second region ii can be used as an etching stop surface. After the etching process is finished, in the first region i, the top surface of the hard mask layer 500 covers the first oxide layer 610 with a certain thickness, and the top surface of the first oxide layer 610 is flush with the top surface of the second oxide layer 620 in the first groove 710. The top surface of the second oxide layer 620 in each of the first grooves 710 is substantially flush with good uniformity.

Referring to fig. 12, the present invention also provides a semiconductor structure obtained by the above forming method, the semiconductor structure including: the substrate 100 comprises a first area I and a second area II which are adjacent to each other; the floating gate layer 300 is positioned on the substrate 100 of the first area I and the substrate 100 of the second area II; the hard mask layer 500 is positioned on the floating gate layer 300, and the top of the hard mask layer 500 in the first area I is lower than that of the hard mask layer 500 in the second area II; a first oxide layer 610, wherein the first oxide layer 610 covers the top of the hard mask layer 500 of the first region I; a first groove 710, wherein the first groove 710 is located in the first region I; a second groove 720, wherein the second groove 720 is located in the second zone II; a second oxide layer 620, the second oxide layer 620 filling the first recess 710 and the second recess 720.

In this embodiment, the top of the second oxide layer 620 in the first region i is flush with the top of the first oxide layer 610.

The semiconductor structure further includes: a gate oxide layer 200 between the substrate 100 and the floating gate layer 300.

In this embodiment, the top of the gate oxide layer 200 of the first region i is flush with the top of the gate oxide layer 200 of the second region ii.

The semiconductor structure further includes: an adhesion layer 400 between the floating gate layer 300 and the hard mask layer 500.

Referring to fig. 20, in other embodiments, the second zone ii includes a middle zone iii and an edge zone iv, and the middle zone iii is located between the first zone i and the edge zone iv.

In this embodiment, the semiconductor structure further includes: a gate oxide layer 200 between the substrate 100 and the floating gate layer 300. The top of the gate oxide layer 200 of the first area I is flush with the top of the gate oxide layer 200 of the middle area III, and the top of the gate oxide layer 200 of the middle area III is lower than the top of the gate oxide layer 200 of the edge area IV.

In this embodiment, the thickness of the gate oxide layer 200 in the first region i is a first thickness, and the thickness of the gate oxide layer 200 in the middle region iii is also the first thickness. The thickness of the gate oxide layer 200 of the edge region iv is a second thickness, and the first thickness is smaller than the second thickness.

In this embodiment, the top of the floating gate layer 300 in the edge region iv is higher than the top of the floating gate layer 300 in the first region i and the middle region iii. The thicknesses of the floating gate layer 300 in the first region I, the middle region III and the edge region IV are equal.

In this embodiment, the top of the hard mask layer 500 in the edge region iv is higher than the top of the hard mask layer 500 in the first region i and the middle region iii. The thicknesses of the hard mask layer 500 in the first region i, the middle region iii and the edge region iv are equal.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a first area and a second area which are adjacent;

forming floating gate layers on the substrate of the first region and the substrate of the second region;

forming a hard mask layer on the floating gate layer, wherein the top of the hard mask layer in the first area is lower than that of the hard mask layer in the second area;

forming a first oxide layer on the hard mask layer of the first area and the hard mask layer of the second area;

etching the first oxide layer, the hard mask layer, the floating gate layer and the substrate, forming a plurality of first grooves in the first area, and forming a plurality of second grooves in the second area;

forming a second oxide layer filling the first groove and the second groove;

and etching the second oxide layer and the first oxide layer until the top surface of the hard mask layer of the second area is exposed, and remaining the first oxide layer to cover the top of the hard mask layer of the first area.

2. The method of claim 1, wherein the second oxide layer is the same material as the first oxide layer.

3. The method of claim 1, wherein the second oxide layer and the first oxide layer are etched using a chemical mechanical polishing process.

4. The method of claim 1, wherein a difference between a top of the hard mask layer in the first region and a top of the hard mask layer in the second region is

5. The method of forming of claim 1, further comprising, prior to forming the floating gate layer: and forming gate oxide layers on the surfaces of the substrate of the first area and the substrate of the second area.

6. The method of forming of claim 5 wherein prior to forming said floating gate layer, a top of a gate oxide layer of said first region is flush with a top of a gate oxide layer of said second region.

7. The method of claim 6, wherein forming the hard mask layer comprises: forming an initial hard mask layer on the floating gate layer by adopting a chemical vapor deposition process;

forming a photoresist layer on the top of the initial hard mask layer in the second area;

etching and removing part of the initial hard mask layer with the thickness of the first area to form a hard mask layer;

and removing the photoresist layer.

8. The method of forming as claimed in claim 5, wherein said second region includes a middle region and an edge region, said middle region being located between said first region and said edge region;

in the process of forming the gate oxide layer, the top of the gate oxide layer of the first area is flush with the top of the gate oxide layer of the middle area, and the top of the gate oxide layer of the middle area is lower than the top of the gate oxide layer of the edge area.

9. The method of forming of claim 8 wherein said gate oxide thickness of said first region and said gate oxide thickness of said intermediate region are each a first thickness and said gate oxide thickness of said edge regions is a second thickness, said first thickness being less than said second thickness.

10. The method of forming as claimed in claim 9, wherein said gate oxide layer comprises a first sub-gate oxide layer and a second sub-gate oxide layer, said first region gate oxide layer and said intermediate region gate oxide layer are said first sub-gate oxide layer, and said edge region gate oxide layer is said second sub-gate oxide layer; the forming process of the gate oxide layer comprises the following steps:

forming a first insulating layer on top of the substrate in the first and intermediate regions;

etching the substrate of the edge area with partial thickness;

performing first oxidation treatment on the top surface of the substrate in the edge region to form the second sub-gate oxide layer;

removing the first insulating layer;

forming a second insulating layer on the top of the substrate in the edge region, wherein the second insulating layer exposes the first region and the top of the substrate in the middle region;

and carrying out second oxidation treatment on the surface of the top of the substrate exposed by the second insulating layer to form the first sub-gate oxide layer.

11. The method of forming of claim 8 wherein a difference between a top of the gate oxide layer in said first region and a top of the gate oxide layer in said edge region is

12. The method of claim 8, wherein the floating gate layer is formed using a furnace process.

13. The method of claim 8, wherein the hard mask layer is formed using a furnace process or a chemical vapor deposition process.

14. A semiconductor structure, comprising:

the substrate comprises a first area and a second area which are adjacent;

the floating gate layer is positioned on the substrate of the first area and the substrate of the second area;

the hard mask layer is positioned on the floating gate layer, and the top of the hard mask layer in the first area is lower than that of the hard mask layer in the second area;

the first oxidation layer covers the top of the hard mask layer of the first area;

a first groove located within the first region;

a second groove located within the second region;

a second oxide layer filling the first and second recesses.