CN112947662A - Low-power consumption LDO circuit based on comparator - Google Patents
Low-power consumption LDO circuit based on comparator Download PDFInfo
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- CN112947662A CN112947662A CN202110320682.4A CN202110320682A CN112947662A CN 112947662 A CN112947662 A CN 112947662A CN 202110320682 A CN202110320682 A CN 202110320682A CN 112947662 A CN112947662 A CN 112947662A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
A low-power LDO circuit based on a comparator is provided with an NMOS tube used for input and output of the LDO, the drain electrode of the NMOS tube is connected with an input power voltage VDD, and the source electrode of the NMOS tube is used as an output voltage VLDO of the LDO, wherein: a charge pump is arranged, the output voltage of the charge pump is used as the LDO input voltage and is connected to the grid electrode of the NMOS tube; a voltage division circuit is configured, and the voltage division circuit divides the LDO output voltage VLDO and outputs the VLDO as a divided voltage VFB; the low-power consumption comparator unit is also provided with at least one low-power consumption comparator unit, and one reference voltage and a divided voltage VFB are used as the input of the low-power consumption comparator unit; the low power consumption comparator unit compares the divided voltage VFB with the reference voltage to generate a control signal, and the control signal is used for controlling the working state of a charge pump circuit. The whole power consumption of the LDO can be reduced to a very low level, the requirements of a low-power consumption circuit or a system needing a low-power consumption sleep working mode can be met, and the stability problem of the LDO is solved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-power LDO circuit based on a comparator.
Background
Low dropout linear regulators (LDOs) are widely used in electronic circuits to generate a dc voltage source relatively independent of the power supply, and the Power Supply Rejection Ratio (PSRR), the input-output voltage (dropvoltage) is an important design parameter.
With increasingly strict requirements of an electronic system, particularly a battery power supply system, on low power consumption, the conventional LDO circuit is more and more difficult to meet the requirements of the system, for example, an MCU circuit requires that the whole circuit is smaller than 1uA in a sleep mode, and thus the working current of the LDO circuit needs to be in the order of hundreds nA, which poses challenges on the area and stability of the conventional LDO design.
Patent CN109416553B proposes an LDO circuit using NMOS transistor, in which a gate boost circuit is added between the error amplifier of the conventional LDO and the NMOS transistor used as the input/output device, so that the differential voltage between the input and output can be reduced to the level of the PMOS transistor when the NMOS transistor is used as the input/output device, and the advantages of high PSRR and low output impedance when the NMOS transistor is used as the output device are also exerted; however, since the conventional error amplifier is also used, in low power consumption applications, if the power consumption is to be reduced, the bias current of the NMOS transistor and the bias current of the amplifier are necessarily required to be reduced, the poles of the output terminal and the gate terminal of the NMOS transistor of the LDO become smaller and closer, and the stability of the LDO is difficult to be ensured. How to reduce power consumption and simultaneously maintain the area of the NMOS LDO and ensure the stability of the LDO loop is still a problem that is difficult to solve.
Disclosure of Invention
In order to make up for the above defects in the prior art, the invention provides a low-power consumption LDO circuit based on a comparator, and the technical scheme is as follows.
A low-power LDO circuit based on a comparator is provided with an NMOS tube used for input and output of the LDO, the drain electrode of the NMOS tube is connected with an input power voltage VDD, and the source electrode of the NMOS tube is used as an output voltage VLDO of the LDO, wherein:
a charge pump is arranged, the output voltage of the charge pump is used as the LDO input voltage and is connected to the grid electrode of the NMOS tube;
a voltage division circuit is configured, and the voltage division circuit divides the LDO output voltage VLDO and outputs the VLDO as a divided voltage VFB;
the low-power consumption comparator unit is also provided with at least one low-power consumption comparator unit, and one reference voltage and a divided voltage VFB are used as the input of the low-power consumption comparator unit;
the low power consumption comparator unit compares the divided voltage VFB with the reference voltage to generate a control signal, and the control signal is used for controlling the working state of a charge pump circuit.
In the technical scheme, when the source electrode of the NMOS tube, namely the output of the LDO output voltage VLDO, is lower than a lower target value, the divided voltage VFB is lower than the reference voltage, the output of the comparator unit is high, and at the moment, the charge pump enables to work, the grid voltage of the NMOS tube is increased, so that the output voltage VLDO is increased; when the output voltage VLDO of the LDO is higher than a higher target value, the divided voltage VFB is higher than the reference voltage, the output of the comparator is low, the charge pump can work in a de-energized mode, the grid voltage of the NMOS tube is kept by the grid capacitor CG, and the output end of the LDO is kept unchanged along with the grid capacitor CG; thus the circuit forms a one-sided hysteretic control loop.
During normal operation, when the output voltage VLDO of the LDO decreases due to a load or the voltage drops due to NMOS gate leakage and is lower than a lower target value, the charge pump is turned on, the output voltage VLDO of the LDO increases accordingly, and when the output voltage VLDO of the LDO is higher than a higher target value, the charge pump is turned off. The LDO output voltage VLDO fluctuates within an allowable range of high and low target values throughout the process.
Compared with the prior art, the invention has the beneficial effects that:
the whole power consumption of the LDO can be reduced to a very low level, and the requirements of a low-power consumption circuit or a system needing a low-power consumption sleep working mode can be met; the advantages of the NMOS transistor LDO are reserved; meanwhile, due to the boosting of the charge pump to the grid electrode of the NMOS tube, the input-output voltage difference can be reduced to the level of the LDO (low dropout regulator) of the PMOS tube; in addition, due to the characteristic of the unilateral hysteresis control loop, the unilateral hysteresis control loop is a steady-state oscillation circuit, and the stability problem of the LDO is solved.
The present invention will be further described with reference to the drawings and the detailed description.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention.
FIG. 2 is a schematic diagram of an output waveform of the LDO of the present invention.
Fig. 3 is a schematic circuit diagram of a first embodiment of the present invention.
Fig. 4 is a schematic circuit diagram of a second embodiment of the present invention.
Fig. 5 is a schematic circuit diagram of a charge pump circuit according to the present invention.
Fig. 6 is a schematic diagram of another circuit of the charge pump circuit of the present invention.
Detailed Description
As shown in fig. 1 to fig. 2, a low power consumption LDO circuit based on a comparator is configured with an NMOS transistor 40 for LDO input/output, a drain of the NMOS transistor 40 is connected to an input power voltage VDD, and a source of the NMOS transistor 40 is used as an LDO output voltage VLDO, wherein:
a charge pump 30 is arranged, the output voltage of the charge pump 30 is used as the LDO input voltage and is connected to the grid electrode of the NMOS tube 40;
a voltage division circuit 50 is configured, wherein the voltage division circuit 50 divides the LDO output voltage VLDO and outputs the VLDO as a divided voltage VFB;
at least one low power consumption comparator unit 20 is further configured, and a reference voltage 10 and a divided voltage VFB are used as the input of the low power consumption comparator unit 20;
the low power consumption comparator unit 20 compares the divided voltage VFB with the reference voltage 10 to generate a control signal, and the control signal is used to control the operation state of a charge pump 30 circuit.
In the above technical solution, when the source of the NMOS transistor 40, i.e., the output of the LDO output voltage VLDO, is lower than a lower target value VL, the divided voltage VFB is lower than the reference voltage 10, and the output of the comparator unit is high, at this time, the charge pump 30 is enabled to operate, and the gate voltage of the NMOS transistor 40 is increased, thereby increasing the output voltage VLDO of the LDO; when the output voltage VLDO of the LDO is higher than a higher target value VH, the divided voltage VFB is higher than the reference voltage 10, the output of the comparator is low, the charge pump 30 can work in a de-energized mode, the grid voltage of the NMOS tube 40 is kept by the grid capacitor CG, and the output end of the LDO is kept unchanged along with the grid capacitor CG; thus the circuit forms a one-sided hysteretic control loop.
During normal operation, when the LDO output voltage VLDO decreases due to load or the voltage drops due to NMOS gate leakage and is lower than a lower target value, the charge pump 30 is turned on, the LDO output voltage VLDO increases accordingly, and the charge pump 30 is turned off after the higher target value is exceeded. The LDO output voltage VLDO fluctuates within an allowable range of high and low target values throughout the process.
When the system works with low power consumption, the repetition frequency of the output voltage of the LDO can be very low, and the whole circuit power consumption is only consumed by the low-power consumption comparator 20 and the voltage division circuit 50 in most of time, so the average power consumption of the LDO circuit can be reduced to be lower than 100nA or lower.
Therefore, the overall power consumption of the LDO can be reduced to a very low level, and the requirements of a low-power circuit or a system requiring a low-power sleep working mode can be met. The advantages of the NMOS transistor LDO are reserved; meanwhile, due to the boosting of the charge pump 30 to the grid electrode of the NMOS tube 40, the input-output voltage difference can be reduced to the level of the LDO (low dropout regulator) of the PMOS tube; in addition, due to the characteristic of the unilateral hysteresis control loop, the unilateral hysteresis control loop is a steady-state oscillation circuit, and the stability problem of the LDO is solved.
[ EXAMPLES one ]
As shown in fig. 3, in the present embodiment, the low power comparator unit 20 includes a first low power comparator, a second low power comparator, and a hysteresis latch, and the reference voltage 10 includes a first voltage reference VREFH with a higher voltage and a second voltage reference VREFL with a lower voltage; the positive end of the first low-power-consumption comparator is connected with a first voltage reference VREFH, the positive end of the second low-power-consumption comparator is connected with a second voltage reference VREFL, and the negative ends of the first low-power-consumption comparator and the second low-power-consumption comparator are both connected with a divided voltage VFB; the output of the first low-power comparator and the output of the second low-power comparator are respectively sent to the first input end and the second input end of the hysteresis latch, and the hysteresis latch generates an output signal as the output of the low-power comparator unit 20; the output and input relations of the hysteresis latch are as follows: the output is high when the first input terminal is high, low when the second input terminal is low, and the output is the same as the level of the previous state when the first input terminal is low and the second input terminal is high.
In the present embodiment, the first voltage reference VREFH and the second voltage reference VREFL are selectively generated from a series of reference voltages by a selection circuit.
[ example two ]
As shown in fig. 4, in the present embodiment, the reference voltage 10 includes a first voltage reference VREFH with a higher voltage and a second voltage reference VREFL with a lower voltage, and the low power consumption comparator unit 20 employs a low power consumption comparator; the first voltage reference VREFH and the second voltage reference VREFL are connected to the positive input terminal of the low power consumption comparator through an one-of-two multiplexer 60, the divided voltage VFB is connected to the negative input terminal of the low power consumption comparator, and the low power consumption comparator outputs or inverts to the selection terminal of the one-of-two multiplexer 60.
In the present embodiment, the first voltage reference VREFH and the second voltage reference VREFL are selectively generated from a series of reference voltages by a selection circuit.
In other embodiments, optionally, the low power consumption comparator unit 20 is a hysteresis comparator, positive and negative input terminals of the hysteresis comparator are respectively connected to the reference voltage 10 and the divided voltage VFB, and an output terminal of the hysteresis comparator is used as an output of the low power consumption comparator unit 20; the reference voltage 10, the voltage division ratio of the voltage division circuit 50 and the hysteresis range of the comparator are all adjustable.
Optionally, the charge pump 30 circuit is a double-voltage charge pump or a triple-voltage charge pump or a multi-stage charge pump or any other type of charge pump, and performs the function of raising or multiplying one or more input voltages and then outputting the one or more input voltages. As shown in fig. 5, the charge pump 30 is a double-voltage charge pump, and is controlled by a clock circuit; as shown in fig. 6, the charge pump 30 is a triple voltage charge pump, also controlled by a clock circuit.
Optionally, the voltage dividing circuit 50 is formed by connecting a resistor or a MOS transistor or a switched capacitor in series.
In a typical application, the NMOS transistor 40 is also used as an input/output transistor of another LDO with larger power consumption; during and only during the operation of the large-power-consumption LDO, the comparator unit and the charge pump 30 are stopped by turning off the clock signal or setting the power-off signal. Therefore, the low-power-consumption LDO circuit can be used as a power supply in a low-power-consumption working mode of the system, an input/output NMOS tube is shared with the LDO in a large-power-consumption working mode of the system, the low-power-consumption LDO circuit is turned on when the system is switched to the low-power-consumption mode, and the low-power-consumption LDO circuit is turned off when the system is switched to the large-power-consumption mode.
It will be clear to a person skilled in the art that the scope of protection of the present invention is not limited to details of the foregoing illustrative embodiments, and that all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein by the appended claims without departing from the spirit or essential characteristics thereof.
Claims (9)
1. A low-power LDO circuit based on a comparator is provided with an NMOS tube used for input and output of the LDO, the drain electrode of the NMOS tube is connected with an input power voltage VDD, and the source electrode of the NMOS tube is used as an output voltage VLDO of the LDO, and the LDO circuit is characterized in that:
a grid capacitor CG is configured, and the grid of the NMOS tube is grounded through the grid capacitor CG;
a charge pump is arranged, the output voltage of the charge pump is used as the LDO input voltage and is connected to the grid electrode of the NMOS tube;
a voltage division circuit is configured, and the voltage division circuit divides the LDO output voltage VLDO and outputs the VLDO as a divided voltage VFB;
the low-power consumption comparator unit is also provided with at least one low-power consumption comparator unit, and one reference voltage and a divided voltage VFB are used as the input of the low-power consumption comparator unit;
the low power consumption comparator unit compares the divided voltage VFB with the reference voltage to generate a control signal, and the control signal is used for controlling the working state of a charge pump circuit.
2. The comparator-based low power LDO circuit of claim 1, wherein the low power comparator unit comprises a first low power comparator, a second low power comparator, and a hysteresis latch, and the reference voltage comprises a first voltage reference VREFH with a higher voltage and a second voltage reference VREFL with a lower voltage; the positive end of the first low-power-consumption comparator is connected with a first voltage reference VREFH, the positive end of the second low-power-consumption comparator is connected with a second voltage reference VREFL, and the negative ends of the first low-power-consumption comparator and the second low-power-consumption comparator are both connected with a divided voltage VFB; the output of the first low-power-consumption comparator and the output of the second low-power-consumption comparator are respectively sent to a first input end and a second input end of the hysteresis latch, and the hysteresis latch generates an output signal which is used as the output of the low-power-consumption comparator unit; the output and input relations of the hysteresis latch are as follows: the output is high when the first input terminal is high, low when the second input terminal is low, and the output is the same as the level of the previous state when the first input terminal is low and the second input terminal is high.
3. The comparator-based LDO circuit with low power consumption according to claim 2, wherein the first voltage reference VREFH and the second voltage reference VREFL are selectively generated from a series of reference voltages by a selection circuit.
4. The comparator-based LDO circuit, according to claim 1, wherein the reference voltage comprises a first voltage reference VREFH with a higher voltage, a second voltage reference VREFL with a lower voltage, and the low power comparator unit employs a low power comparator; the first voltage reference VREFH and the second voltage reference VREFL are connected to the input positive end of the low-power consumption comparator through an one-of-two multi-way switch, the divided voltage VFB is connected to the input negative end of the low-power consumption comparator, and the low-power consumption comparator outputs or outputs in an inverted mode to the selection end of the one-of-two multi-way switch.
5. The comparator-based low power LDO circuit of claim 4, wherein the first voltage reference VREFH and the second voltage reference VREFL are selectively generated from a plurality of reference voltages by a selection circuit.
6. The LDO circuit with low power consumption based on the comparator as claimed in claim 1, wherein the low power consumption comparator unit is a hysteresis comparator, positive and negative input terminals of the hysteresis comparator are respectively connected to the reference voltage and the divided voltage VFB, and an output terminal of the hysteresis comparator is used as an output of the low power consumption comparator unit; the reference voltage, the voltage division proportion of the voltage division circuit and the hysteresis range of the comparator are all adjustable.
7. The comparator-based LDO circuit with low power consumption of claim 1, wherein the charge pump circuit is a double voltage charge pump or a triple voltage charge pump or a multi-stage charge pump or any other type of charge pump that performs the function of boosting or multiplying one or more input voltages and then outputting the boosted or multiplied voltages.
8. The LDO circuit with low power consumption based on comparator as claimed in claim 1, wherein the voltage divider circuit is formed by a resistor or a MOS transistor or a switched capacitor connected in series.
9. The comparator-based LDO circuit with low power consumption of claim 1, wherein the NMOS transistor is simultaneously used as an input/output transistor of another LDO with higher power consumption; during and only during the operation of the high-power LDO, the comparator unit and the charge pump are stopped to work by closing the clock signal or setting a power-off signal.
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| CN202110320682.4A CN112947662A (en) | 2021-03-25 | 2021-03-25 | Low-power consumption LDO circuit based on comparator |
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| CN202110320682.4A CN112947662A (en) | 2021-03-25 | 2021-03-25 | Low-power consumption LDO circuit based on comparator |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113852281A (en) * | 2021-09-18 | 2021-12-28 | 上海咨芯微电子有限公司 | Low-power-consumption booster circuit system and battery protection chip |
| CN114253333A (en) * | 2021-12-16 | 2022-03-29 | 乐鑫信息科技（上海）股份有限公司 | Voltage stabilizer |
| CN116382409A (en) * | 2023-06-06 | 2023-07-04 | 上海灵动微电子股份有限公司 | Linear voltage stabilizing circuit system and control method thereof |
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