CN112929021A - Detector module and signal counting correction method thereof - Google Patents
Detector module and signal counting correction method thereof Download PDFInfo
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Abstract
The application provides a detector module and a counting rate correction method thereof, wherein the detector module comprises: a detector; and the readout circuit is used for reading out the electric signal of the detector and counting the electric signal, and comprises a charge sensitive pre-amplification CSA circuit, a shaping circuit, a discriminator and a counter, wherein the readout circuit further comprises a signal accumulation correction circuit which is connected between the discriminator and the counter and is used for dividing the pulse width of the signal of the discriminator based on the preset window time of the signal accumulation correction circuit to perform accumulated signal correction under the condition that the signal output by the shaping circuit is accumulated so as to enable the counter to count the corrected signal.
Description
Technical Field
The present disclosure relates to the field of X-ray radiation, and more particularly to a detector module and a signal count correction method thereof.
Background
The X-ray imaging system generally comprises a detector, a readout circuit, data transmission and storage, and upper computer software, wherein the detector is generally a linear array or an area array photodetector, a dedicated readout integrated circuit is used for reading out an electrical signal of the detector, and the detector are core devices of the imaging system.
The readout circuit is classified into two types according to the difference of signal processing modes: one type of chip is called a current integration type data converter (ADC), which integrates a current signal of a detector and converts the integrated current signal into a digital signal through the ADC to realize the amplitude detection of rays in a given integration period; the other type of the single photon counting type chip is called as a single photon counting type chip, and the single photon counting type chip amplifies, discriminates and counts signals of a detector to realize the detection of energy quantum counting, amplitude information and time information of single photons.
When the signals of the detector are counted by the conventional readout circuit, accumulation of the output signals of the shaping circuit in the readout circuit occurs when the counting rate is high and the interval between the signals is too small. Signal pile-up can reduce the linearity of the readout circuit/chip count rate and also affect the maximum count rate. In addition, signal pile-up can cause more high energy region counts than low energy region counts, which can cause erroneous results and affect the application of energy calibration, material identification, etc. of the X-ray imaging system.
Disclosure of Invention
In view of the drawbacks described in the background above, the present invention is directed to: the problem of non-linearity of the counting rate of a single photon counting chip caused by signal accumulation under the condition of high counting rate is solved. By the nonlinear correction of the counting rate of the chip, the chip can work under the condition of higher counting rate without saturation of the chip.
The solution to this problem is to add a Pile-up Correction (PUC) circuit between the discriminator and the counter. When there is no signal accumulation, the input pulse width of the PUC circuit is less than the forming time twThe PUC circuit inputs a pulse, and the output also obtains a pulse; when there is signal accumulation, the input pulse width of the PUC circuit is larger than twAt this time, the PUC inputs one pulse, and n pulses are obtained according to the width of the input pulse and the window time of the PUC. By adding the PUC circuit, the counting rate of the single photon counting chip can be corrected and the maximum counting rate can be improved.
To achieve this object, in a first aspect of the present application, there is provided a detector module, which may include: a detector; and the reading circuit is used for reading the electric signal of the detector and counting the electric signal, and comprises a charge sensitive pre-amplification CSA circuit, a shaping circuit, a discriminator and a counter, wherein the reading circuit further comprises a signal accumulation correction circuit which is connected between the discriminator and the counter and is used for dividing the pulse width of the signal of the discriminator based on the preset window time of the signal accumulation correction circuit to perform accumulated signal correction under the condition that the signal output by the shaping circuit is accumulated so as to enable the counter to count the corrected signal.
According to a first aspect of the present application, the signal pile-up correction circuit may include: at least one first one-of-two circuit having a first input terminal INO, a second input terminal IN1, a gate input terminal S, and an output terminal Q; and a delay circuit having an input terminal and an output terminal, wherein the first input terminal IN0 of the at least one first one-out-of-two circuit is connected with the output terminal of the discriminator, the gate input terminal S of the at least one first one-out-of-two circuit is connected with the output terminal of the delay circuit, and the output terminal Q of the at least one first one-out-of-two circuit is connected with the input terminal of the delay circuit.
According to the first aspect of the present application, the signal pile-up correction circuit may further include: and a second alternative circuit for selecting whether the signal pile-up correction circuit performs a correction function IN the readout circuit or does not perform a correction function IN the readout circuit, wherein a first input terminal INO of the second alternative circuit is connected to an output terminal Q of the at least one first alternative circuit, and a second input terminal IN1 of the second alternative circuit is connected to an output terminal of the discriminator.
According to the first aspect of the present application, the predetermined window time of the signal pile-up correction circuit is equal to the sum of the delay time from the input rising edge to the output rising edge of the delay circuit and the delay time from the input falling edge to the output falling edge of the delay circuit.
According to the first aspect of the present application, IN the case where the signal output by the discriminator is a high-level trigger pulse, the delay time from the input rising edge to the output rising edge of the delay circuit is longer than the delay time from the input falling edge to the output falling edge of the delay circuit, and the second input terminal IN1 IN the at least one first one-out-of-two circuit is kept at a low level; or IN the case where the signal output by the discriminator is a low-level trigger pulse, the delay time from the input rising edge to the output rising edge of the delay circuit is smaller than the delay time from the input falling edge to the output falling edge of the delay circuit, and the second input terminal IN1 IN the at least one first one-out-of-two circuit is kept at a high level.
According to the first aspect of the present application, the signal pile-up correction circuit may be further configured to perform the following operations: when the signal output by the discriminator in the reading circuit is a high-level trigger pulse, dividing the pulse width of the signal of the discriminator at the delay time from the input falling edge to the output falling edge by taking the delay time from the input rising edge to the output rising edge of the signal accumulation correction circuit as a scale, thereby obtaining the pulse width/preset window time pulses of the divided signal; and taking the smallest integer larger than the pulse width of the signal/the predetermined window time as the quantity value of the piled-up signal, so that the counter counts the number value.
According to the first aspect of the present application, the signal pile-up correction circuit may be further configured to perform the following operations: when the signal output by the discriminator in the reading circuit is a low-level trigger pulse, dividing the pulse width of the signal of the discriminator at the delay time from the input rising edge to the output rising edge by taking the delay time from the input falling edge to the output falling edge of the signal accumulation correction circuit as a scale, thereby obtaining the pulse width/preset window time pulses of the divided signal; and taking the smallest integer larger than the pulse width of the signal/the predetermined window time as the quantity value of the piled-up signal, so that the counter counts the number value.
According to the first aspect of the present application, the predetermined window time may be adjusted by configuring the signal pile-up correction circuit.
According to the first aspect of the present application, in the case where the readout circuit has a plurality of energy regions, the predetermined window time of the signal pile-up correction circuit corresponding to the discriminator of the high energy region is less than or equal to the predetermined window time of the signal pile-up correction circuit corresponding to the discriminator of the low energy region.
In a second aspect of the present application, there is provided a signal count correction method performed in a detector module, the method may include: in the case of accumulation of signals output by a shaping circuit in a readout circuit in a detector module, a pulse width of a signal at a discriminator is divided for accumulation signal correction based on a predetermined window time of a signal accumulation correction circuit by a signal accumulation correction circuit provided between the discriminator and a counter in the readout circuit to cause the counter to count the corrected signals.
According to the second aspect of the present application, the window time of the signal pile-up correction circuit is equal to the sum of the delay time from the input rising edge to the output rising edge of the delay circuit in the signal pile-up correction circuit and the delay time from the input falling edge to the output falling edge of the delay circuit.
According to the second aspect of the present application, in the case where the signal output by the discriminator in the readout circuit is a high-level trigger pulse, the delay time from the input rising edge to the output rising edge of the delay circuit is longer than the delay time from the input falling edge to the output falling edge of the delay circuit; and when the signal output by the discriminator is a low-level trigger pulse, the delay time from the input rising edge to the output rising edge of the delay circuit is less than the delay time from the input falling edge to the output falling edge of the delay circuit.
According to a second aspect of the present application, dividing the pulse width of the signal at the discriminator based on the predetermined window time of the signal pile-up correction circuit to cause the counter to count the corrected signal comprises the operations of: when the signal output by the discriminator in the readout circuit is a high-level trigger pulse, dividing the piled-up signal at the delay time from the input falling edge to the output falling edge by taking the delay time from the input rising edge to the output rising edge of the signal pile-up correction circuit as a scale, thereby obtaining pulse width/predetermined window time pulses of the divided piled-up signal; and counting the number value of the piled-up signals by the smallest integer larger than the pulse width/predetermined window time of the piled-up signals.
According to a second aspect of the present application, dividing the pulse width of the signal at the discriminator based on the predetermined window time of the signal pile-up correction circuit to cause the counter to count the corrected signal comprises the operations of: when the signal output by the discriminator in the reading circuit is a low-level trigger pulse, dividing the pulse width of the signal of the discriminator at the delay time from the input rising edge to the output rising edge by taking the delay time from the input falling edge to the output falling edge of the signal accumulation correction circuit as a scale, thereby obtaining the pulse width/preset window time pulses of the divided signal; and counting the number value of the piled-up signals by the smallest integer larger than the pulse width of the signals/the predetermined window time.
According to a second aspect of the application, the predetermined window time may be adjusted by configuring the signal pile-up correction circuit.
According to the second aspect of the present application, in the case where the readout circuit has a plurality of energy regions, the predetermined window time of the signal pile-up correction circuit corresponding to the discriminator of the high energy region is less than or equal to the predetermined window time of the signal pile-up correction circuit corresponding to the discriminator of the low energy region.
In a third aspect of the application, an X-ray imaging system is provided, which may comprise a detector module according to the first aspect.
Drawings
The above and other embodiments and features of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the attached drawings in which:
fig. 1 schematically shows a diagram of an example arrangement of detectors and readout circuitry in an X-ray imaging system according to an embodiment of the present disclosure;
FIG. 2 schematically illustrates a circuit diagram of an exemplary readout circuit according to an embodiment of the present disclosure;
figure 3 schematically illustrates the output waveforms of a shaping circuit and a discriminator in the case of signal pile-up according to an embodiment of the disclosure;
FIG. 4 schematically illustrates a graph of output count rate versus input count rate in a readout circuit according to an embodiment of the disclosure;
FIG. 5 schematically illustrates a circuit diagram of a first embodiment of a readout circuit including a signal pile-up correction circuit, according to an embodiment of the present disclosure;
FIG. 6 schematically shows a circuit diagram of a second embodiment of a readout circuit including a signal pile-up correction circuit according to an embodiment of the present disclosure;
FIG. 7 schematically illustrates a circuit diagram of a first embodiment of a signal pile-up correction circuit according to an embodiment of the present disclosure;
FIG. 8 schematically illustrates a circuit diagram of a second embodiment of a signal pile-up correction circuit according to an embodiment of the present disclosure;
FIG. 9 schematically illustrates a circuit diagram of a third embodiment of a signal pile-up correction circuit according to an embodiment of the present disclosure;
FIG. 10 schematically illustrates several implementations of low-level output units in a signal pile-up circuit according to an embodiment of the disclosure;
FIG. 11 schematically shows circuit diagrams of two delay circuits in a second embodiment of a signal pile-up correction circuit according to an embodiment of the present disclosure;
FIG. 12 schematically illustrates an output and an output waveform diagram of a signal pile-up correction circuit according to an embodiment of the disclosure;
FIG. 13 is a diagram schematically illustrating the relationship between input count rate and output count rate before and after utilizing a signal pile-up correction circuit, according to an embodiment of the present disclosure;
FIG. 14 schematically illustrates a comparison of low and high energy zone count rates before and after using a signal pile-up correction circuit according to an embodiment of the disclosure.
Detailed Description
Specific embodiments of the present invention will be described in detail below, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the present invention. In other instances, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present invention.
Throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples.
It will be understood that when an element is referred to as being "coupled" or "connected" to another element, it can be directly coupled or connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, there are no intervening elements present.
Further, as used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that a noun in the singular corresponding to a term may include one or more things unless the relevant context clearly dictates otherwise. As used herein, each of the phrases such as "a or B," "at least one of a and B," "at least one of a or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B or C" may include all possible combinations of the items listed together with the respective one of the plurality of phrases. As used herein, terms such as "1 st" and "2 nd" or "first" and "second" may be used to distinguish one element from another element simply and not to limit the elements in other respects (e.g., importance or order).
As used herein, the term "circuitry" may include units implemented in hardware, software, or firmware, and may be used interchangeably with other terms (e.g., "logic," "logic block," "portion," or "module"). A module may be a single integrated component adapted to perform one or more functions or a minimal unit or portion of the single integrated component. For example, according to an embodiment, the modules may be implemented in the form of Application Specific Integrated Circuits (ASICs).
It should be understood that the various embodiments of the present disclosure and the terms used therein are not intended to limit the technical features set forth herein to specific embodiments, but include various changes, equivalents, or alternatives to the respective embodiments. Unless otherwise explicitly defined herein, all terms are to be given their broadest possible interpretation, including meanings implied in the specification and meanings understood by those skilled in the art and/or defined in dictionaries, papers, etc.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. For the description of the figures, like reference numerals may be used to refer to like or related elements. The present disclosure will be described below by way of example with reference to the accompanying drawings.
It should be noted that, in the fields of security inspection, nondestructive testing and medical imaging, in order to obtain better image quality and more accurate substance identification under lower X-ray irradiation dose, interconnection between the electrode of the pixel type detector and the readout chip is realized through a flip-chip process by developing a large-scale pixel type detector and a pixel type single photon counting readout chip matched with the large-scale pixel type detector. The interconnected detector and chip are referred to as a detector module, and a typical pixel detector module is shown in fig. 1 and mainly comprises a PCB, a readout chip (or readout circuit), bumps and a detector. One pixel detector module can be used for independent imaging or energy spectrum detection, and radiation imaging or energy spectrum detection with larger area can be realized through a scheme of splicing a plurality of detector modules.
A system block diagram of a typical n-pixel, m-energy-zone single photon counting chip is shown in fig. 2. The circuit mainly comprises a Charge Sensitive preamplifier (CSA) circuit, a shaping circuit (shape), a Discriminator and a Counter. The charge sensitive pre-discharge circuit may be one or more stages for effecting charge-to-voltage conversion. The shaping circuit is used for carrying out shaping filtering processing on the signal output by the charge sensitive front discharge circuit so as to reduce the noise of the signal. The discriminator is used for realizing amplitude discrimination of the signal, namely when the amplitude of the signal output by the shaping amplifier is larger than a preset threshold value, the discriminator outputs a pulse. The counter is used for counting the output pulses of the discriminator. The number of discriminators and counters in the same path indicates the number of chip energy regions. Usually, the chip also integrates modules such as an I/O module, a bias circuit, a configuration register, and a trimming DAC.
Figure 3 schematically illustrates the output waveforms of the shaping circuit and the discriminator in the case of signal pile-up according to an embodiment of the disclosure. As shown, the forming time of the forming circuit is twThe discriminator < 1 > and the discriminator < 2 > are two discriminators, and the predetermined threshold voltages are VTH< 1 > and VTH< 2 >, (wherein V)TH< 2 > is greater than VTH< 1 >. The outputs of the shaping circuit, discriminator and counter in both the no signal pile-up and the signal pile-up cases will be described below with reference to fig. 3.
(ii) No Signal Stacking
As shown in FIG. 3, the first output signal of the shaping circuit is shaped over a shaping time twAnd then may return to baseline. When the amplitude of the output signal of the shaping circuit is larger than VTHWhen the number is less than 1, the discriminator outputs a pulse signal when the number is less than 1, and the corresponding counter increases by 1. At this point, the counter correctly records the number of pulses.
② there is signal accumulation
As shown in FIG. 3, the second, third and fourth signals outputted from the forming circuit cannot be formed at the forming time t due to accumulationwInternal recovery to a predetermined threshold V of discriminator < 1 >THBelow < 1 > this causes the discriminator to output only one pulse, losing information for both signals, although the shaping circuit outputs three signals.
In general, in the absence of signal pile-up, the number of pulses output by a discriminator with a low threshold is greater than the number of pulses output by a discriminator with a high threshold over a period of time due to the statistical distribution of the amplitude of the signal output by the shaping circuit. For high count rates and with a large amount of signal pile-up, a discriminator with a high threshold may output more pulses over a period of time than a discriminator with a low threshold. As shown in fig. 3, a discriminator with a high threshold < 2 > outputs 4 pulses, while a discriminator with a low threshold < 1 > outputs only 3 pulses due to signal pile-up.
Fig. 4 schematically shows a graph of the relationship between the output count rate and the input count rate in a readout circuit according to an embodiment of the disclosure.
As can be seen from fig. 4, when the input count rate is less than C1, the output count rate is a linear function of the input count rate due to no or little signal pile-up; when the input count rate is between C1 and C2, the output count rate curve deviates from an ideal linear line as signal pile-up conditions degrade; when the input count rate is higher than C2, the signal pile-up is severe and the output count rate decreases as the input count rate increases. Typically, the performance of a single photon counter system will deteriorate when the input count rate is greater than C2. Therefore, a signal pile-up correction circuit is needed to correct the counts of the single photon counter, by which the loss of counts under high count rate conditions can be reduced while ensuring that the counts of the high energy region counter are less than the counts of the low energy region counter over a period of time. By adding the signal accumulation correction circuit, the single photon counting system can work under the condition of higher counting rate.
To address the problems as described in the background section, embodiments of the present disclosure provide an X-ray imaging system and method that can more accurately count detector signals without being affected by signal pile-up. The X-ray imaging system may include a detector; and the reading circuit is used for reading the electric signal of the detector and comprises a charge sensitive pre-amplification CSA circuit, a shaping circuit, a discriminator and a counter, wherein the reading circuit further comprises a signal accumulation correction circuit, and the signal accumulation correction circuit is connected between the discriminator and the counter and is used for splitting the accumulated signal based on the window time of the signal accumulation correction circuit and the pulse width of the signal input to the reading circuit under the condition that the signal output by the shaping circuit is accumulated so as to enable the counter to count and correct the accumulated signal.
Fig. 5 schematically shows a circuit diagram of a first embodiment of a readout circuit including a signal pile-up correction circuit according to an embodiment of the present disclosure.
As shown in fig. 5, the readout circuit can include a CSA, a shaping circuit, a discriminator, a signal pile-up correction circuit, and a counter.
In an exemplary embodiment, there may be multiple discriminators in the readout circuit. Correspondingly, the readout circuit may also include a signal pile-up correction circuit and a counter corresponding to each of the plurality of discriminators.
In an exemplary embodiment, a signal pile-up correction circuit PUC is connected between the discriminator and the counter for correctly dividing the pulse output via the discriminator, thereby enabling the counter to perform count correction on the signal.
Fig. 6 schematically shows a circuit diagram of a second embodiment of a readout circuit including a signal pile-up correction circuit according to an embodiment of the present disclosure.
The readout circuits in fig. 5 and 6 are substantially the same except for the inclusion of a power window circuit.
In an exemplary embodiment, the signal pile-up correction circuit is connected between the discriminator and the energy window circuit in the presence of the energy window circuit, whereby the energy window circuit can count the counter corresponding to each pulse excitation divided via the signal pile-up circuit in the case where the signal pile-up circuit correctly divides the pulse output by the discriminator.
Fig. 7 schematically illustrates a circuit diagram of a first embodiment of a signal pile-up correction circuit according to an embodiment of the present disclosure.
In an exemplary embodiment, the signal pile-up correction circuit 700 may include an alternative circuit 701 and a delay circuit 702.
As shown, the one-out-of-two circuit 702 includes a gate input S, a first input IN0, a second input IN1, and an output Q.
IN an exemplary embodiment, the first input IN0 is connected to the output of the discriminator, i.e., the signal output by the discriminator is the input signal I of the first input IN 0.
Whether the second input terminal IN1 is kept high or low depends on the input signal I. Specifically, IN the case where the input signal I is a high-level trigger pulse, the second input terminal IN1 is kept at a low level; IN the case where the input signal I is a low trigger pulse, the second input terminal IN1 remains high.
IN case the input signal I is a high level trigger pulse, the second input terminal IN1 may be connected with a low level output unit. One implementation of a low level output cell is shown in fig. 10.
IN an exemplary embodiment, the second input terminal IN1 may be connected to a nand gate whose input is high.
IN another exemplary embodiment, the second input terminal IN1 may be directly grounded.
When the S terminal of the second one of the two-out circuits 701 is at a high level, the second input terminal IN1 is gated, and the value of the output terminal Q is the same as that of the second input terminal IN 1; when the S terminal is low, the IN0 terminal is gated on, and the output terminal Q has the same value as the input terminal IN 0.
The delay time t from the input rising edge to the output rising edge of the delay circuit 702rd1The delay time from input falling edge to output falling edge is tfd1。
In the case of input signal I being a high level trigger pulse, the delay time t from the input rising edge to the output rising edgerd1Is far greater than the delay time from the input falling edge to the output falling edge and is tfdl。
In the case of the input signal I being a low level trigger pulse, the delay time t from the input rising edge to the output rising edgerd1Much less than the delay time from the input falling edge to the output falling edge of tfd1。
Fig. 8 schematically illustrates a circuit diagram of a second embodiment of a signal pile-up correction circuit according to an embodiment of the present disclosure.
The signal pile-up correction circuit 800 may include two alternative circuits 801, 802 and one delay circuit 803.
The configuration of the alternative circuits 801 and 802 is the same as that of the alternative circuit 701 described in fig. 7, and the configuration of the delay circuit 803 is the same as that of the delay circuit 803 described in fig. 7. To avoid redundant description, the description of the one- out circuits 801 and 802 and the delay circuit 803 is omitted here.
Although only two alternative circuits are shown in fig. 8, it will be understood by those skilled in the art that more alternative circuits may be provided.
Fig. 9 schematically illustrates a circuit diagram of a third embodiment of a signal pile-up correction circuit according to an embodiment of the present disclosure.
The signal pile-up correction circuit 900 may include two alternative circuits 901, 902 and two delay circuits 903 and 904.
The configurations of the alternative circuits 901 and 902 are the same as those of the alternative circuit 701 in fig. 7 and the alternative circuits 801 and 802 in fig. 8, and are not described again.
It should be noted that the signal pile-up correction circuit in fig. 9 includes two delay circuits 903 and 904, where the delay time from the input rising edge to the output rising edge of the delay circuit 903 is trd3The delay time from input falling edge to output falling edge is tfd3The delay time from the input rising edge to the output rising edge of the delay circuit 904 is trd4The delay time from input falling edge to output falling edge is tfd4。
In case of a high level trigger pulse of the input signal I, trd3＜tfd3And t isfd4＜＜trd4。
Exemplarily, tfd4Is t rd41/20, 1/30, 1/40, 1/50, preferably 1/100. However, not limited thereto, tfd4And trd4The correspondence between them can be adjusted as needed.
Alternatively, t is the case where the input signal I is a high level trigger pulserd3＞tfd3And t isrd4＞tfd4。
In case of a low level trigger pulse of the input signal I, tfd3＜trd3And t isrd4＜＜tfd4。
As mentioned above, exemplarily, trd4Is t fd41/20, 1/30, 1/40, 1/50, preferably 1/100. However, not limited thereto, tfd4And trd4The correspondence between them can be adjusted as needed.
Alternatively, t is the case where the input signal I is a low level trigger pulsefd3＞trd3And t isfd4＞trd4。
IN an exemplary embodiment, the signal pile-up correction circuit may further include an additional one of two circuits MUX3 (e.g., 905 of FIG. 9) so that when EN is high, MUX3 gates the input of IN1 and output Y is the same as input I, at which time the PUC circuit function is masked. When EN is low, MUX3 gates the input of IN0, and the output Y is the same as the signal at node b, so that the PUC circuit operates normally.
For convenience of description, reference will be made to the signal pile-up correction circuit shown in fig. 9.
Fig. 11 schematically shows circuit diagrams of two kinds of delay circuits in the second embodiment of the signal pile-up correction circuit according to the embodiment of the present disclosure. In fig. 11, (a) shows a circuit diagram of the delay circuit 903 in fig. 9, and (b) in fig. 11 shows a circuit diagram of the delay circuit 904 in fig. 9.
In fig. 11 (a), the R1 resistance is much larger than the on-resistance of the PMOS transistor MP4 and the NMOS transistor MN4, and when the potential of the node a changes from low to high, the current flowing through the PMOS transistor MP4 directly charges C1 with the charging time constant being the product of the on-resistance of C1 and MP 4; when the potential of the node a changes from high to low, the charge on the capacitor C1 is discharged through the R1 with a discharge time constant of about the product of R1 and C1. The resistor R1 in the circuit can be replaced by a MOS tube working in a linear region; c1 may also be replaced by a MOS capacitor.
In fig. 11 (b), the charging time constant of node a of the circuit is larger than the discharging time constant because R1 exists only in the charging loop. The t can be adjusted by adjusting the R1 resistance value and the C1 capacitance value in (b) of FIG. 11fd4And trd4And (4) adjusting.
Fig. 12 schematically illustrates an output and an output waveform diagram of a signal pile-up correction circuit according to an embodiment of the present disclosure.
Now, the operation principle of the PUC circuit in fig. 9 is explained based on the pulse width characteristic of the input signal as follows:
when no signal is input, the inputs of the MUX1, the MUX2 and the MUX3 are all low, and their outputs can only be low no matter their S terminals are low or high, i.e., the a, b and Y nodes are low. Since the b node is low, the nodes c and d are also low.
When t isw＜trd3+trd4At this time, since the state before the point d is low, the output terminal b will also be high when the rising edge of the input signal arrives. Node (C)The rising edge at point b requires a delay trd3+trd4Will appear at node d but because of the pulse width t of the input signalw＜trd3+trd4Therefore, the potential of node d will remain low at all times; therefore, the IN0 inputs of MUX1 and MUX2 are always gated, so the pulse width at node b is the same as the pulse width at input node I.
When trd3+trd4＜tw＜trd3+trd4+tfd3+tfd4The rising edge of node b needs to be delayed by trd3+trd4This time later appears at node d, and when node d is high, the IN1 inputs of MUX1 and MUX2 are gated on, and nodes a and b go low. But since the falling edge of node b passes tfd3+tfd4Later appears at node d, but the input high level pulse becomes low level before node b becomes low level, so that the potential of node b becomes trd3+trd4And remains low for a period of time after the moment. In this case, the node pulse width is trd3+trd4。
④tw＞trd3+trd4+tfd3+tfd4Then, the analysis of the third step shows that the node b is at trd3+trd4At time t, the node d becomes lowrf3+trf4Time to trd3+trd4+tfd3+tfd4The time of day is kept high, and when the node d is high, the IN1 inputs of the MUX1 and MUX2 are gated, and the potential of the output node b is equal to the potential of the node e, i.e., low. At trd3+trd4+tfd3+tfd4After that time, node d goes low, MUX1 and MUX2 re-gate the IN0 input, and output node b returns to the same high level as input I.
The timing diagram of the critical nodes I, b, d of the pile-up correction circuit is shown in FIG. 12. When EN is low, MUX3 gates the input of IN0 and the waveform at output node Y is the same as the waveform at node b.
As can be seen from the above description, the signal pile-up correction circuit functions as:
when inputting pulse width tinNot greater than the window time t of the signal pile-up correction circuitpThe signal pile-up correction circuit outputs a pulse whose output pulse width is not greater than tp。
When the pulse width t is inputinGreater than tpThe signal pile-up correction circuit outputs n pulses. Wherein
That is, n is the ratio tin/tpThe largest smallest integer.
Here, tpThe PUC circuit's intrinsic window time, which can be adjusted by the configuration circuit. For a pixel type photon counter chip with m energy regions, the window time of a PUC circuit corresponding to a high-energy region discriminator is required to be not more than that of a low-energy region.
In the embodiment of FIG. 9, tpMay be equal to trd3+trd4+tfd3+tfd4。
It can be seen that the signal pile-up correction circuit splits the stacked input pulse signal based on its window time, thereby splitting the stacked input pulse signal into a plurality of non-stacked signals, thereby facilitating the counter to count the input signal correctly.
By utilizing the signal accumulation correction circuit to carry out nonlinear correction on the counting rate of the chip, the chip can work under the condition of higher counting rate without saturation.
Fig. 13 schematically illustrates a graph of the relationship between input count rate and output count rate before and after utilizing a signal pile-up correction circuit according to an embodiment of the disclosure.
As shown in fig. 13, the linearity of the count rate corrected by using the signal pile-up correction circuit according to the embodiment of the present application can be further improved, and the maximum count rate can be further improved.
FIG. 14 schematically illustrates a comparison of low and high energy zone count rates before and after using a signal pile-up correction circuit according to an embodiment of the disclosure.
The curve shown in fig. 14 is the experimental data of the counting rate of the photon counter chip with signal pile-up correction function, and the main experimental conditions are as follows:
the detector is a Cadmium Zinc Telluride (CZT) detector, and the pixel size of the detector is 1mm2。
② the forming time of the chip is 200ns, and the gain is 380 mv/fC.
Thirdly, the chip is provided with two energy regions, the energy of the X-ray corresponding to the threshold of the low energy region is 18keV, the energy of the X-ray corresponding to the threshold of the high energy region is 79keV,
the distance between the x-ray machine and the detector is 1m, and the maximum output ray energy of the x-ray machine is 160 keV.
The experimental method is as follows:
because the current of the X-ray machine is in direct proportion to the input counting rate, the change of the output counting rate of the chip is observed by scanning the current of the X-ray machine.
The experimental results are shown in fig. 14 (a) and (b). As can be seen from fig. 14, for the output count rate of the low energy region, when the x-ray machine current is low, that is, the input count rate is low, the count rates of the two cases of the pile-up correction circuit and the non-pile-up correction circuit are close; when the current of the x-ray machine is higher, namely the input counting rate is higher, the output counting rate has larger difference; after the accumulation correction circuit is started, the linearity of the output counting rate and the maximum counting rate are obviously improved. For the output count rate of the high energy region, the pile-up correction circuit does not significantly improve, but improves, the count rate of the high energy region because the number of x-rays of the high energy region of the x-ray machine is generally much less than the number of low energy regions, and there is much less signal pile-up with lower energy.
For an x-ray imaging system, the indexes of the image, such as silk resolution, substance identification capability, penetrating power, line pair and the like, can be improved after being corrected by the accumulation correction method.
Although the above embodiments are described by taking a pixel type photon single counter chip as an example, it should be understood by those skilled in the art that the technical solutions set forth in the present disclosure can also be used in a chip with only one channel or any other suitable circuit.
The above description has been mainly made in hardware, but it should be understood by those skilled in the art that corresponding hardware can correspondingly execute a corresponding method.
For simplicity of description, the functions and methods performed by the hardware circuitry will not be set forth in detail herein.
Those skilled in the art will appreciate that various combinations and/or combinations of features recited in the various embodiments and/or claims of the present disclosure can be made, even if such combinations or combinations are not expressly recited in the present disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present disclosure may be made without departing from the spirit or teaching of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (17)
1. A detector module, comprising:
a detector; and
a readout circuit for reading out the electrical signal of the detector and counting the electrical signal, the readout circuit comprising a charge sensitive pre-amplification CSA circuit, a shaping circuit, a discriminator and a counter, wherein,
the readout circuit further includes a signal pile-up correction circuit connected between the discriminator and the counter for dividing a pulse width of the signal of the discriminator based on a predetermined window time of the signal pile-up correction circuit for pile-up signal correction in a case where the signal output by the shaping circuit is piled up, so that the counter counts the corrected signal.
2. The detector module of claim 1, wherein the signal pile-up correction circuitry comprises:
at least one first one-of-two circuit having a first input terminal IN0, a second input terminal IN1, a gate input terminal S, and an output terminal Q; and
a delay circuit having an input and an output, wherein,
the first input IN0 of the at least one first one-out circuit is connected to an output of the discriminator, the gated input S of the at least one first one-out circuit is connected to the output of the delay circuit, and the output Q of the at least one first one-out circuit is connected to the input of the delay circuit.
3. The detector module of claim 2, the signal pile-up correction circuit further comprising: a second alternative circuit for selecting whether the signal pile-up correction circuit performs a correction function in the readout circuit or does not perform a correction function in the readout circuit, wherein
The first input IN0 of the second one-of-two circuit is connected to the output Q of the at least one first one-of-two circuit, and the second input IN1 of the second one-of-two circuit is connected to the output of the discriminator.
4. The detector module of claim 2,
the predetermined window time of the signal pile-up correction circuit is equal to the sum of the delay time from the input rising edge to the output rising edge of the delay circuit and the delay time from the input falling edge to the output falling edge of the delay circuit.
5. The detector module of claim 2,
IN the case where the signal output by the discriminator is a high-level trigger pulse, the delay time from the input rising edge to the output rising edge of the delay circuit is longer than the delay time from the input falling edge to the output falling edge of the delay circuit, and the second input terminal IN1 IN the at least one first one-out circuit remains low; or
IN the case where the signal output by the discriminator is a low-level trigger pulse, the delay time from the input rising edge to the output rising edge of the delay circuit is smaller than the delay time from the input falling edge to the output falling edge of the delay circuit, and the second input terminal IN1 IN the at least one first one-out-of-two circuit is kept at a high level.
6. The detector module of claim 4, wherein the signal pile-up correction circuitry is further configured to:
when the signal output by the discriminator in the reading circuit is a high-level trigger pulse, dividing the pulse width of the signal of the discriminator at the delay time from the input falling edge to the output falling edge by taking the delay time from the input rising edge to the output rising edge of the signal accumulation correction circuit as a scale, thereby obtaining the pulse width/predetermined window time pulses of the divided signal; and
the smallest integer larger than the pulse width of the signal/predetermined window time is taken as the magnitude value of the piled-up signal, so that the counter counts it.
7. The detector module of claim 4, wherein the signal pile-up correction circuitry is further configured to:
when the signal output by the discriminator in the reading circuit is a low-level trigger pulse, dividing the pulse width of the signal of the discriminator at the delay time from the input rising edge to the output rising edge by taking the delay time from the input falling edge to the output falling edge of the signal accumulation correction circuit as a scale, thereby obtaining the pulse width/predetermined window time number of pulses of the divided signal; and
the smallest integer larger than the pulse width of the signal/predetermined window time is taken as the magnitude value of the piled-up signal, so that the counter counts it.
8. The detector module of claim 1,
the predetermined window time can be adjusted by configuring the signal pile-up correction circuit.
9. The detector module of claim 1,
in the case where the readout circuit has multiple energy regions, the predetermined window time of the signal pile-up correction circuit corresponding to the discriminator for the high energy region is less than or equal to the predetermined window time of the signal pile-up correction circuit corresponding to the discriminator for the low energy region.
10. A method of signal count correction performed in a detector module, the method comprising:
in the case of signal pile-up output by a shaping circuit in a readout circuit in the detector module, a pulse width of a signal at a discriminator is divided for pile-up signal correction based on a predetermined window time of a signal pile-up correction circuit by a signal pile-up correction circuit disposed between the discriminator and a counter in the readout circuit to cause the counter to count the corrected signal.
11. The signal count correction method according to claim 10,
the window time of the signal pile-up correction circuit is equal to the sum of the delay time from the input rising edge to the output rising edge of the delay circuit in the signal pile-up correction circuit and the delay time from the input falling edge to the output falling edge of the delay circuit.
12. The signal count correction method according to claim 11,
in the case that a signal output by a discriminator in the readout circuit is a high-level trigger pulse, the delay time from the input rising edge to the output rising edge of the delay circuit is longer than the delay time from the input falling edge to the output falling edge of the delay circuit; and
when the signal output by the discriminator is a low-level trigger pulse, the delay time from the input rising edge to the output rising edge of the delay circuit is less than the delay time from the input falling edge to the output falling edge of the delay circuit.
13. The signal count correction method of claim 12, wherein dividing the pulse width of the signal at the discriminator based on a predetermined window time of the signal pile-up correction circuit for pile-up signal correction to cause the counter to count the corrected signal comprises:
when the signal output by the discriminator in the reading circuit is a high-level trigger pulse, dividing the pulse width of the signal at the delay time from the input falling edge to the output falling edge by taking the delay time from the input rising edge to the output rising edge of the signal accumulation correction circuit as a scale, thereby obtaining the pulse width/preset window time pulses of the divided signal; and
counting the number value of the piled-up signals with the smallest integer larger than the pulse width/predetermined window time of the signals.
14. The signal count correction method of claim 13, wherein dividing the pulse width of the signal at the discriminator based on a predetermined window time of the signal pile-up correction circuit for pile-up signal correction to cause the counter to count the corrected signal comprises:
when the signal output by the discriminator in the readout circuit is a low-level trigger pulse, dividing the pulse width of the signal at the delay time from the input rising edge to the output rising edge by taking the delay time from the input falling edge to the output falling edge of the signal accumulation correction circuit as a scale, thereby obtaining the pulse width/predetermined window time pulses of the divided signal; and
counting the number value of the piled-up signals with the smallest integer larger than the pulse width/predetermined window time of the signals.
15. The signal count correction method according to claim 10,
the predetermined window time can be adjusted by configuring the signal pile-up correction circuit.
16. The signal count correction method according to claim 10,
in the case where the readout circuit has multiple energy regions, the predetermined window time of the signal pile-up correction circuit corresponding to the discriminator for the high energy region is less than or equal to the predetermined window time of the signal pile-up correction circuit corresponding to the discriminator for the low energy region.
17. An X-ray imaging system comprising a detector module according to any one of claims 1 to 9.
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