CN112928016A - Rapid annealing process for wafer - Google Patents
Rapid annealing process for wafer Download PDFInfo
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- CN112928016A CN112928016A CN202110133828.4A CN202110133828A CN112928016A CN 112928016 A CN112928016 A CN 112928016A CN 202110133828 A CN202110133828 A CN 202110133828A CN 112928016 A CN112928016 A CN 112928016A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02634—Homoepitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Microelectronics & Electronic Packaging (AREA)
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- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a rapid annealing process of a wafer. The rapid annealing process for the wafer provided by the invention is used for carrying out solid phase epitaxial treatment on the silicon wafer before the rapid heating step in the rapid annealing process in the foundation. The heavily doped ions cause lattice damage, an amorphous and single crystal interface is formed at the ion implantation junction, and through medium-low temperature short-time tempering, the single crystal below the interface can be used as a seed crystal for recrystallization of an amorphous layer to complete a solid phase epitaxy process, the lattice damage caused by arsenic can be greatly repaired along with crystallization, and meanwhile, the diffusion of other lightly doped ions cannot be influenced to cause junction deepening because the temperature is not too high and the time is relatively short in the process. Therefore, the process provided by the invention does not need additional processing procedures and cost investment, and introduces a new scheme into the existing processing procedures, thereby not only realizing the repair of high lattice damage caused by the heavily doped ions, but also ensuring the high activation rate of all ions and forming a shallow junction.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a rapid annealing process of a wafer.
Background
In the manufacture of integrated circuits, ion implantation is used to add dopants to control electrons or holes, thereby achieving the necessary steps of increasing or decreasing the conductivity of the semiconductor. Due to the ever-shrinking dimensions of semiconductor devices, as shown in fig. 1, higher doses of ion doping (e.g., arsenic, boron, etc.) are required for manufacturing processes and to meet the low resistance requirements. The accompanying problem is a large amount of lattice damage, especially of heavy dopant ions such as arsenic, which, if present at a shallow junction, can severely affect the leakage current and even cause device failure.
In the prior art, in order to solve the above problems, two technical schemes, namely, conventional FURNACE tube (furace) annealing and rapid thermal annealing (RTP), are adopted. As shown in fig. 2, conventional furnace annealing can completely repair lattice damage and activate ions, but cannot meet the process requirements of advanced shallow junctions due to the high thermal budget caused by long processing time. As shown in fig. 3, the rapid thermal anneal is stabilized at about 500 degrees celsius for 20 to 30 seconds and then rapidly ramped up to over 1000 degrees with a dwell time of less than 1.5 seconds at a peak temperature of plus or minus 50 degrees to form a shallow junction with high ion activation. Because the time is too short at a stable temperature of 500 degrees (low temperature and short time) and at a spike temperature (over 1000 degrees), the repair rate of the damaged crystal lattice interface caused by arsenic ion implantation is relatively low, which causes an increase in Transient Enhanced Diffusion (TED) during subsequent high temperature annealing, and high leakage problems.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a rapid annealing process for wafers, which aims to solve the technical problems of lattice damage, high ion activation rate and formation of shallow junctions, which cannot be satisfied simultaneously, caused by ion implantation in the conventional integrated circuit manufacturing process.
The invention provides a rapid annealing process for a wafer, which has the following specific technical scheme:
the method is used for the rapid annealing process of the wafer, and the silicon wafer is subjected to solid phase epitaxy treatment before the rapid temperature rise step in the rapid annealing process in the basic medium.
In certain embodiments, the method comprises the steps of:
s1, loading the silicon wafer subjected to the ion implantation treatment;
s2, solid phase epitaxy treatment;
s3, rapidly heating;
s4, annealing and cooling;
and S5, unloading the wafer.
Specifically, in step S1, the ion implantation process is a heavy doping process, and the ions are ions with atomic mass greater than 70.
In particular, the ions are arsenic ions, phosphorus ions or boron ions.
Specifically, in step S2, the solid phase epitaxy treatment is a low-temperature annealing treatment at 700-750 ℃ for 20-30 seconds.
Specifically, in step S3, the temperature-increasing rate of the rapid temperature-increasing is greater than 100 ℃/S, and the peak temperature during the rapid temperature-increasing process is 1000-.
In particular, in step S4, the annealing cooling has a cooling rate greater than 100 ℃/S.
The invention has the following beneficial effects: the rapid annealing process for the wafer provided by the invention is used for carrying out solid phase epitaxial treatment on the silicon wafer before the rapid heating step in the rapid annealing process in the foundation. The heavily doped ions cause lattice damage, an amorphous and single crystal interface is formed at the ion implantation interface, and the single crystal under the interface can be used as a seed crystal for recrystallization of the amorphous layer to complete the solid phase epitaxy process through low temperature (700-750 ℃) and short time (20-30 seconds) tempering. In the solid phase epitaxy process, the crystal lattice damage caused by arsenic can be greatly repaired along with crystallization, and meanwhile, because the temperature is not too high and the time is relatively short in the process, the diffusion of other light doped ions cannot be influenced, and the junction is not deepened. Therefore, the process provided by the invention does not need additional processing procedures and cost investment, and introduces a new scheme into the existing processing procedures, thereby not only realizing the repair of high lattice damage caused by the heavily doped ions, but also ensuring the high activation rate of all ions and forming a shallow junction.
Drawings
FIG. 1 is a schematic illustration of ion doping in a prior art semiconductor device fabrication process;
FIG. 2 is a schematic diagram illustrating the temperature variation of a conventional furnace annealing process in the prior art;
FIG. 3 is a schematic diagram of the temperature change of a rapid thermal annealing process in the prior art;
fig. 4 is a flowchart of a rapid annealing process for a wafer according to embodiment 1 of the present invention;
fig. 5 is a schematic temperature variation diagram of a rapid annealing process for a wafer according to embodiment 1 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
Example 1
The rapid annealing process for a wafer provided in this embodiment has the following specific implementation:
as shown in fig. 4-5, the rapid annealing process for wafer includes the following steps:
and S1, loading the silicon wafer heavily doped with arsenic ions, wherein the crystal lattice of the silicon wafer is damaged due to the heavily doped arsenic ions, and an amorphous and single crystal interface is formed at the ion implantation junction.
S2, solid phase epitaxy processing, wherein the single crystal below the interface can be used as a seed crystal for amorphous layer recrystallization to complete a solid phase epitaxy process through medium and low temperature (700-750 ℃) short-time (20-30 seconds) tempering, and in the solid phase epitaxy process, the crystal lattice damage caused by arsenic can be greatly repaired along with crystallization; meanwhile, because the temperature of the process is not too high and the time is relatively short, the diffusion of other light doped ions is not affected, so that the junction is deepened.
S3, rapidly heating, wherein the heating rate of the rapid heating is more than 100 ℃/S; wherein the peak temperature for the rapid ramp is 1066 degrees celsius.
S4, annealing and cooling, wherein the cooling rate of the annealing and cooling is more than 100C/S; the subsequent rapid annealing process (more than 1000 degrees, less than 1.5 seconds) can ensure high activation rates of all ions.
And S5, unloading the wafer.
The above description is only for the purpose of illustrating preferred embodiments of the present invention and is not to be construed as limiting the invention, and the present invention is not limited to the above examples, and those skilled in the art should also be able to make various changes, modifications, additions or substitutions within the spirit and scope of the present invention.
Claims (7)
1. The novel rapid annealing process for the wafer is characterized in that the silicon wafer is subjected to solid phase epitaxy treatment before the rapid temperature rise step in the basic rapid annealing process.
2. The novel rapid annealing process for wafers according to claim 1, comprising the steps of:
s1, loading the silicon wafer subjected to the ion implantation treatment;
s2, solid phase epitaxy treatment;
s3, rapidly heating;
s4, annealing and cooling;
and S5, unloading the wafer.
3. The novel rapid annealing process for wafer according to claim 2, wherein in step S1, the ion implantation process is a heavy doping process, and the ions are ions with atomic mass greater than 70.
4. The novel rapid annealing process for wafers according to claim 3, wherein the ions are arsenic ions, phosphorus ions or boron ions.
5. The novel rapid annealing process for wafer as claimed in claim 2, wherein in step S2, the solid phase epitaxy process is a low-temperature annealing process with 700-750 ℃ for 20-30 seconds.
6. The novel rapid annealing process for wafers as claimed in claim 2, wherein in step S3, the temperature rise rate of the rapid temperature rise is greater than 100 ℃/S, and the peak temperature during the rapid temperature rise process is 1000-.
7. The novel rapid annealing process for wafer according to claim 2, wherein in step S4, the temperature decrease rate of the annealing cooling is greater than 100 ℃/S.
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| CN202110133828.4A CN112928016A (en) | 2021-02-01 | 2021-02-01 | Rapid annealing process for wafer |
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| CN202110133828.4A CN112928016A (en) | 2021-02-01 | 2021-02-01 | Rapid annealing process for wafer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113421820A (en) * | 2021-06-22 | 2021-09-21 | 捷捷半导体有限公司 | Oxidation annealing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110098524A (en) * | 2010-02-26 | 2011-09-01 | 주식회사 하이닉스반도체 | Transistor manufacturing method of semiconductor device |
| US20130264644A1 (en) * | 2012-04-09 | 2013-10-10 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of the same |
| CN105244272A (en) * | 2014-06-18 | 2016-01-13 | 中国科学院微电子研究所 | Monitoring method of annealing equipment |
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2021
- 2021-02-01 CN CN202110133828.4A patent/CN112928016A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110098524A (en) * | 2010-02-26 | 2011-09-01 | 주식회사 하이닉스반도체 | Transistor manufacturing method of semiconductor device |
| US20130264644A1 (en) * | 2012-04-09 | 2013-10-10 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of the same |
| CN105244272A (en) * | 2014-06-18 | 2016-01-13 | 中国科学院微电子研究所 | Monitoring method of annealing equipment |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113421820A (en) * | 2021-06-22 | 2021-09-21 | 捷捷半导体有限公司 | Oxidation annealing method |
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Effective date of registration: 20220915 Address after: 510000 building a, No. 136, Kaiyuan Avenue, Huangpu Development Zone, Guangzhou, Guangdong Applicant after: Guangdong Dawan District integrated circuit and System Application Research Institute Applicant after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510535 building a, 136 Kaiyuan Avenue, Guangzhou Development Zone, Guangdong Province Applicant before: Guangdong Dawan District integrated circuit and System Application Research Institute Applicant before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |
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Application publication date: 20210608 |