CN112910794A - Load balancing system for multi-path E1 networking - Google Patents

Abstract

The invention discloses a load balancing system of a multi-path E1 networking, which comprises a lower layer Ethernet networking, an FPGA chip, an Ethernet chip and an upper layer Ethernet networking, wherein a downlink port of the FPGA chip is connected with the lower layer Ethernet networking, and an uplink port of the FPGA chip is connected with the upper layer Ethernet networking through the Ethernet chip; the FPGA chip is configured with a bus bridge module; the bus bridge module is used for processing data requests of a plurality of paths of E1 links by adopting a preset processing strategy; after the data receiving request of one E1 link is processed, the processing strategy continues to jump to the next E1 link until the data receiving request of each E1 link is traversed. According to the invention, through carrying out load balancing design on the bridge module of the core network IPOE interface and adopting a non-blocking state machine based on rapid jump, the problem of IPOE data packet congestion at the junction of the core network in a service concurrent scene is avoided.

Description

A load balancing system for multi-channel E1 networking

technical field

The present invention relates to the field of communication technologies, in particular to a load balancing system for multi-channel E1 networking.

Background technique

In the 2M networking based on E1 links, the use scenarios of multiplexing E1 links are very common. For example, the secondary equipment of the provincial core network is connected to the municipal office, and the municipal core network is connected with the local office. to network. In a 2M network where multiple E1 links are multiplexed through the IPOE data channel, there will inevitably be scenarios in which multiple services are concurrent.

In the case of high multi-office service load, if the load balancing design is not carried out at the IPOE receiving point of the core network, it is easy to occur that a certain office direction is fully occupied, and the core network receiving tandem always processes the office with high load occupancy. request to. If other offices send requests at this time, it is easy to cause the requests of other offices to be put on hold and cannot be processed.

SUMMARY OF THE INVENTION

The purpose of the embodiments of the present invention is to provide a load balancing system for multi-channel E1 networking. By carrying out a load balancing design on the bridge module of the IPOE interface of the core network, and adopting a non-blocking state machine based on fast jumping, it avoids the need for business concurrency In the scenario of , IPOE packet congestion occurs at the core network junction.

To achieve the above object, an embodiment of the present invention provides a load balancing system for multi-channel E1 networking, including a lower-layer Ethernet networking, an FPGA chip, an Ethernet chip, and an upper-layer Ethernet networking, wherein the FPGA chip The downlink port of the FPGA chip is connected to the lower-layer Ethernet networking, and the uplink port of the FPGA chip is connected to the upper-layer Ethernet networking through the Ethernet chip; the FPGA chip is configured with a bus bridge module; wherein,

The bus bridging module is used to process data requests of multiple E1 links by using a preset processing strategy; the processing strategy is to continue to jump to processing the next E1 link after processing the data reception request of one E1 link The data receiving request of the link is traversed until the data receiving request of each E1 link.

Preferably, the FPGA chip is further configured with a codec module, a parsing conversion module and a buffer module; wherein,

The encoding and decoding module is used to receive the differential signal sent by the lower-layer Ethernet networking, decode it into a binary code stream, and send it to the analysis and conversion module;

The analysis and conversion module is used for serial-to-parallel conversion and analysis of the received binary code stream to be the data of the Avalon-ST bus protocol, and sent to the buffer module;

The buffer module is used to read the data of the Avalon-ST bus protocol, and perform aggregation and bridging in the format of data packets.

Preferably, it also includes:

The buffer module is also used to receive the data of the Avalon-ST bus protocol sent by the upper-layer Ethernet networking, and send it to the analysis and conversion module;

The analysis and conversion module is also used to reorganize the received data of the Avalon-ST bus protocol according to the HDLC protocol, and serially convert it into a serial binary code stream, and send it to the codec module;

The encoding and decoding module is further configured to encode the received serial binary code stream and send it to the lower-layer Ethernet networking.

Preferably, it also includes a Buffer chip, and each E1 link in the lower-layer Ethernet networking is connected to the FPGA chip through one of the Buffer chips.

Preferably, the encoding and decoding rules adopted by the encoding and decoding modules are HDB3 encoding and decoding rules.

Preferably, the parsing protocol adopted by the parsing conversion module is the HDLC protocol.

Preferably, the buffering mode of the buffer module is whole packet buffering, and when it is confirmed that the data sent by the downlink E1 link has been buffered as a complete data packet, the data packet is read at a preset reading rate .

Preferably, the buffering rate of the buffering module is 2 Mbps.

Preferably, the preset read rate is 50Mbps.

Preferably, the waiting time for the bus bridge module to process the data request of each E1 link is 1 clock cycle.

Compared with the prior art, the load balancing system of the multi-channel E1 networking provided by the embodiment of the present invention, by applying the fast jumping strategy to the design of the Avalon-ST bus bridge in the E1 networking, the request The processing state machine is designed for fast jumping, so as to achieve the purpose of load balancing processing when multiple services are concurrent, and solve the problem of concurrent blocking of multiple services. Moreover, the redesigned state machine only needs to add extra processing time resources and FPGA logic resources. consume.

Description of drawings

FIG. 1 is a schematic structural diagram of a load balancing system for multi-channel E1 networking according to an embodiment of the present invention;

2 is a schematic diagram of data processing of a fast jump-based non-blocking state machine provided by an embodiment of the present invention;

3 is a schematic diagram of data processing of a priority-based bridging policy according to an embodiment of the present invention;

4 is a schematic diagram of the time taken by a state machine based on a fast jump design provided by an embodiment of the present invention when processing data requests of various E1 links;

5 is a schematic structural diagram of an FPGA chip provided by an embodiment of the present invention;

6 is a schematic diagram of a processing flow corresponding to an FPGA chip pair when it receives a data request from an upper-layer Ethernet networking and a lower-layer Ethernet networking according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Referring to FIG. 1 , it is a schematic structural diagram of a load balancing system for multi-channel E1 networking according to Embodiment 1 of the present invention. The system includes a lower-layer Ethernet networking, an FPGA chip, an Ethernet chip, and an upper-layer Ethernet networking. Wherein, the downlink port of the FPGA chip is connected to the lower-layer Ethernet network, and the uplink port of the FPGA chip is connected to the upper-layer Ethernet network through the Ethernet chip; the FPGA chip is configured with a bus bridging module; where,

The bus bridging module is used to process data requests of multiple E1 links by using a preset processing strategy; the processing strategy is to continue to jump to processing the next E1 link after processing the data reception request of one E1 link The data receiving request of the link is traversed until the data receiving request of each E1 link.

Specifically, the load balancing system for multi-channel E1 networking includes a lower-layer Ethernet network, an FPGA (FieldProgrammable Gate Array, Field Programmable Gate Array) chip, an Ethernet chip, and an upper-layer Ethernet network. The port is connected to the lower-layer Ethernet network, and the upstream port of the FPGA chip is connected to the upper-layer Ethernet network through the Ethernet chip. Generally, both the lower-layer Ethernet networking and the upper-layer Ethernet networking consist of multiple E1 links. The above is a complete 2M system, and the solution of the present invention can be implemented after power-on.

Wherein, the FPGA chip is configured with the bus bridge module. The main purpose of the bus bridge module is to realize the load balancing function. The implementation process is as follows:

The bus bridge module is used to process data requests of multiple E1 links by using a preset processing strategy; the processing strategy is to continue to jump to the next E1 link after processing the data reception request of one E1 link until the data receiving request of each E1 link is traversed. When the bus bridge module works at a clock rate of 50Mhz, it can process data of up to 25 2M links without blocking. Therefore, after the module has processed the data receiving request of a certain E1 link, it directly uses the 50Mhz clock to jump to the next channel to judge the status of the E1 receiving request, even if the next E1 link does not request to receive data, this strategy can be used to In the process of one data reception, traversing and judging the receiving request of each channel avoids the blocking of other channels E1 due to the high load of one channel E1. This strategy can be called a non-blocking state machine based on fast jumping. Referring to FIG. 2 , it is a schematic diagram of data processing of a fast jump-based non-blocking state machine provided by this embodiment of the present invention. In order to highlight the advantages of the present invention, this embodiment of the present invention also describes the processing of multi-channel concurrent data in the prior art. In the prior art, a priority-based bridging strategy is generally used for multi-channel concurrent data processing, that is, when When the bridge has been processing requests with high load, it is easy to cause other requests to be put on hold and cannot be processed. Referring to FIG. 3 , it is a schematic diagram of data processing of a priority-based bridging strategy provided by this embodiment of the present invention.

Although the redesigned state machine of the present invention requires additional processing time resources, the time cost is very low and can be ignored. Referring to FIG. 4 , it is a schematic diagram of the time spent by the state machine based on the fast jump design provided by this embodiment of the present invention when processing data requests of various E1 links. It can be seen from Figure 4 that even if only one E1 link is receiving at full load, the additional jumping time of the state machine is n-1 50Mhz clock cycles. Taking the 2M system as an example, one FPGA chip handles the receiving requests of 16 E1 links, and the intermediate jump time of the state machine is 20ns*15=300ns, which is equivalent to only increasing the bandwidth consumption of 120bps under one full-load E1 link. , which is almost negligible relative to the 2Mbps E1 link bandwidth. Therefore, the bus bridge module can judge the reception request of each E1 link with little increase in processing time cost.

Embodiment 1 of the present invention provides a load balancing system for multi-channel E1 networking, performs load balancing design on the bridging module of the IPOE interface of the core network, and adopts a non-blocking state machine based on fast jumping, which avoids the need for concurrent business operations. In the scenario, the IPOE packet congestion problem occurs at the core network tandem.

As an improvement of the above solution, the FPGA chip is further configured with an encoding/decoding module, a parsing conversion module and a buffering module; wherein,

The encoding and decoding module is used to receive the differential signal sent by the lower-layer Ethernet networking, decode it into a binary code stream, and send it to the analysis and conversion module;

The analysis and conversion module is used for serial-to-parallel conversion and analysis of the received binary code stream to be the data of the Avalon-ST bus protocol, and sent to the buffer module;

The buffer module is used to read the data of the Avalon-ST bus protocol, and perform aggregation and bridging in the format of data packets.

Specifically, referring to FIG. 5 , it is a schematic structural diagram of an FPGA chip provided by this embodiment of the present invention. It can be seen from FIG. 5 that the FPGA chip is further configured with the codec module, the parsing and conversion module, and the buffer module; wherein,

The encoding and decoding module is used to receive the differential signal sent by the lower-layer Ethernet networking, decode it into a binary code stream, and send it to the parsing and converting module. The differential signal refers to the HDB3 differential signal. The HDB3 original differential signal of the E1 link is connected to the FPGA pins through the Buffer chip after being shaped by positive and negative judgments externally. After the codec module decodes the differential signal, it also obtains the clock of the peer device.

The analysis and conversion module is used for serial-to-parallel conversion and analysis of the received binary code stream into data of the Avalon-ST bus protocol, and sends the data to the buffer module. That is to say, when the parsing and converting module receives the binary code stream sent by the encoding and decoding module, it first performs serial-to-parallel conversion on the binary code stream, and then parses it into data of the Avalon-ST bus protocol.

The buffer module is used to read the data of the Avalon-ST bus protocol, and perform aggregation and bridging in the format of data packets. Generally, the E1 link works at the rate of 2M, and before entering the data processing on the FPGA chip, the data packets at the rate of 2Mbps need to be converted into the rate of 50Mbps for processing. The buffer module buffers the whole packet of the data packet received by the E1 link, confirms the buffering of a complete packet at a rate of 2 Mbps, and then reads the data packet at a rate of 50 Mbps for aggregation and bridging.

The above process is a process in which the FPGA chip processes the data request received from the lower-layer Ethernet networking. Referring to FIG. 6 , it is a schematic diagram of a corresponding processing flow when an FPGA chip pair according to this embodiment of the present invention receives a data request from an upper-layer Ethernet networking and a lower-layer Ethernet networking. Among them, the upper part is the corresponding processing flow when receiving the data request of the lower-layer Ethernet networking, and the lower half is the corresponding processing flow when receiving the data request of the upper-layer Ethernet networking.

In this embodiment of the present invention, the HDB3 original differential signal of the E1 link is decoded by the encoding and decoding module to obtain a binary code stream, and then the binary code stream is serial-to-parallel conversion by the parsing and conversion module, and then parsed into the Avalon-ST bus protocol Then use the buffer module to read the data of the Avalon-ST bus protocol, and perform aggregation and bridging in the format of data packets to process the data request of the lower-layer Ethernet networking.

As an improvement of the above scheme, it also includes:

The buffer module is also used to receive the data of the Avalon-ST bus protocol sent by the upper-layer Ethernet networking, and send it to the analysis and conversion module;

The analysis and conversion module is also used to reorganize the received data of the Avalon-ST bus protocol according to the HDLC protocol, and serially convert it into a serial binary code stream, and send it to the codec module;

The encoding and decoding module is further configured to encode the received serial binary code stream and send it to the lower-layer Ethernet networking.

Specifically, referring to the lower half of the flow in Figure 6, when the FPGA chip pair receives a data request from the upper-layer Ethernet networking, it needs to perform reverse transmission, and the corresponding processing flow is as follows:

The buffer module is further configured to receive the data of the Avalon-ST bus protocol sent by the upper-layer Ethernet networking, and send it to the analysis and conversion module. Similarly, the receiving process also needs to buffer the entire packet. After a complete data packet is buffered, the buffering module sends the data packet to the parsing and converting module through the Avalon-ST bus.

The analysis and conversion module is also used to reorganize the received data of the Avalon-ST bus protocol according to the HDLC protocol, which is also called encapsulation. Codec module.

The encoding and decoding module is also used for encoding the received serial binary code stream and sending it to the lower-layer Ethernet networking. Before reaching each E1 link, the encoded signal is sent to the Buffer chip and converted to positive and negative levels.

In this embodiment of the present invention, the buffer module is used to receive the data of the Avalon-ST bus protocol sent by the upper-layer Ethernet networking, and then the data of the received Avalon-ST bus protocol is reorganized by the analysis and conversion module according to the HDLC protocol. Convert it into a serial binary code stream, then encode it through the serial binary code stream of the codec module, and send it to the lower-layer Ethernet network to process the data request of the upper-layer Ethernet network.

As an improvement of the above solution, a Buffer chip is also included, and each E1 link in the lower-layer Ethernet networking is connected to the FPGA chip through one of the Buffer chips.

Specifically, the load balancing system for multi-channel E1 networking further includes the Buffer chip, and each E1 link in the lower-layer Ethernet networking is connected to the FPGA chip through one of the Buffer chips. That is to say, each E1 link in the lower-layer Ethernet networking is connected to the pins of the FPGA chip through the Buffer chip.

In this embodiment of the present invention, a Buffer chip is added between each E1 link and the FPGA chip to reduce the positive and negative level distortion of each E1 link.

As an improvement of the above solution, the encoding and decoding rules adopted by the encoding and decoding modules are HDB3 encoding and decoding rules.

Specifically, the encoding and decoding rules adopted by the encoding and decoding modules are HDB3 encoding and decoding rules. That is, the encoding and decoding module decodes the received differential signal into a binary code stream according to the HDB3 decoding rule, and encodes the received binary code stream into a differential signal according to the HDB3 encoding rule.

As an improvement of the above solution, the parsing protocol adopted by the parsing conversion module is the HDLC protocol.

Specifically, the parsing protocol adopted by the parsing conversion module is the HDLC protocol. Preferably, the HDLC protocol adopts the parallel HDLC protocol, and the idle code is translated relative to the standard HDLC protocol, so as to ensure that the data packet will not be debugged when the same data as the idle code appears in the original data.

As an improvement of the above solution, the buffering mode of the buffer module is whole packet buffering. When confirming that the data sent by the downlink E1 link has been buffered as a complete data packet, the data packet is stored at a preset reading rate. to read.

Specifically, the buffering mode of the buffer module is whole packet buffering, and when it is confirmed that the data sent by the downlink E1 link has been buffered as a complete data packet, the data packet is read at a preset reading rate . For example, it is confirmed that a complete packet is buffered at a rate of 2Mbps, and then the data packet is read out at a rate of 50Mbps for aggregation bridging.

As an improvement of the above solution, the buffering rate of the buffering module is 2 Mbps.

Specifically, the buffering rate of the buffering module is 2 Mbps. The buffer module buffers the whole packet of the data packets received by the E1 link, and then reads the data packets after confirming that a complete packet is buffered at a rate of 2 Mbps, so as to avoid incomplete data or errors or omissions in the data packets.

As an improvement of the above solution, the preset read rate is 50Mbps.

Specifically, the preset read rate is 50 Mbps. After the data packet is completely cached, read it again, and the read rate is greater than the cache rate, which is beneficial to quickly obtain the content of the data packet, process the data request, and reduce link congestion.

As an improvement of the above solution, the waiting time for the bus bridge module to process the data request of each E1 link is 1 clock cycle.

Specifically, the waiting time for the bus bridge module to process the data request of each E1 link is 1 clock cycle. That is to say, the bus bridge module can judge the reception request of each channel E1 with little increase in processing time cost. Even if only one channel of E1 is receiving at full load, the additional jumping time of the state machine is n-1 channels of 50Mhz clock cycles. Taking the 2M system as an example, an FPGA handles the receiving requests of 16 E1 links, and the intermediate jump time of the state machine is 20ns*15=300ns, which is equivalent to only increasing the bandwidth consumption of 120bps under a full-load E1 link. The E1 link bandwidth of 2Mbps is almost negligible.

To sum up, the load balancing system of the multi-channel E1 networking provided by the embodiment of the present invention, by applying the fast jump strategy to the design of the Avalon-ST bus bridge in the E1 networking, the request processing state machine is processed. The fast jump design achieves the purpose of load balancing processing when multiple services are concurrent, and solves the problem of concurrent blocking of multiple services. Moreover, the redesigned state machine only needs to add extra processing time resources, FPGA logic resource consumption, and processing reception. The request latency is only 1 clock cycle, the bandwidth consumption is almost negligible, and the resource consumption of the bus bridge is not increased. The invention can be compatible with various multi-channel E1 networking modes, and can ensure that the problem of blocking caused by a single-channel office direction does not occur in the networking environment.

The above are the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can also be made, and these improvements and modifications may also be regarded as It is the protection scope of the present invention.

Claims (10)

1. a load balancing system of multi-channel E1 networking, is characterized in that, comprises lower layer Ethernet networking, FPGA chip, Ethernet chip and upper layer Ethernet networking, wherein, the downlink port of described FPGA chip and described The lower-layer Ethernet networking is connected, and the uplink port of the FPGA chip is connected to the upper-layer Ethernet networking through the Ethernet chip; the FPGA chip is configured with a bus bridge module; wherein, The bus bridging module is used to process data requests of multiple E1 links by using a preset processing strategy; the processing strategy is to continue to jump to processing the next E1 link after processing the data reception request of one E1 link The data receiving request of the link is traversed until the data receiving request of each E1 link. 2. The load balancing system of multi-channel E1 networking according to claim 1, wherein the FPGA chip is also configured with a codec module, a parsing conversion module and a buffer module; wherein, The encoding and decoding module is used to receive the differential signal sent by the lower-layer Ethernet networking, decode it into a binary code stream, and send it to the analysis and conversion module; The analysis and conversion module is used for serial-to-parallel conversion and analysis of the received binary code stream to be the data of the Avalon-ST bus protocol, and sent to the buffer module; The buffer module is used to read the data of the Avalon-ST bus protocol, and perform aggregation and bridging in the format of data packets. 3. The load balancing system for multi-channel E1 networking as claimed in claim 2, further comprising: The buffer module is also used to receive the data of the Avalon-ST bus protocol sent by the upper-layer Ethernet networking, and send it to the analysis and conversion module; The analysis and conversion module is also used to reorganize the received data of the Avalon-ST bus protocol according to the HDLC protocol, and serially convert it into a serial binary code stream, and send it to the codec module; The encoding and decoding module is further configured to encode the received serial binary code stream and send it to the lower-layer Ethernet networking. 4. The load balancing system of multi-channel E1 networking as claimed in claim 1, characterized in that, further comprising a Buffer chip, and each E1 link in the lower-layer Ethernet networking is connected to the Buffer chip through a described Buffer chip. The FPGA chip is connected. 5 . The load balancing system for multi-channel E1 networking according to claim 2 , wherein the encoding and decoding rules adopted by the encoding and decoding modules are HDB3 encoding and decoding rules. 6 . 6 . The load balancing system for multi-channel E1 networking according to claim 2 , wherein the parsing protocol adopted by the parsing and converting module is the HDLC protocol. 7 . 7. The load balancing system of multi-channel E1 networking as claimed in claim 2, wherein the buffering mode of the buffer module is a whole packet buffer, and the data sent by the downlink E1 link has been buffered as a complete When the data packet is received, the data packet is read at a preset read rate. 8 . The load balancing system for multi-channel E1 networking according to claim 7 , wherein the buffering module has a buffering rate of 2 Mbps. 9 . 9 . The load balancing system for multi-channel E1 networking according to claim 7 , wherein the preset reading rate is 50 Mbps. 10 . 10. The load balancing system for multi-channel E1 networking according to any one of claims 1-7, wherein the waiting time for the bus bridge module to process the data request of each E1 link is 1 clock cycle .

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