CN112910366B - Single-resistor current sampling method, chip and electronic equipment - Google Patents
Single-resistor current sampling method, chip and electronic equipment Download PDFInfo
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- CN112910366B CN112910366B CN201911223432.8A CN201911223432A CN112910366B CN 112910366 B CN112910366 B CN 112910366B CN 201911223432 A CN201911223432 A CN 201911223432A CN 112910366 B CN112910366 B CN 112910366B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
- H02P23/14—Estimation or adaptation of motor parameters, e.g. rotor time constant, flux, speed, current or voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
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Abstract
The application provides a single-resistor current sampling method, a chip and electronic equipment, wherein the method comprises the following steps: detecting that the count value of the timer is zero, triggering a first interrupt, acquiring the current value flowing through the sampling resistor in the current period in the first interrupt, and modulating a first pulse width modulation signal in the first interrupt; detecting that the count value of the timer is the maximum period value, outputting a first pulse width modulation signal, and triggering a second interrupt; phase-shift compensating a second pulse width modulation signal modulated in a second interrupt according to the first pulse width modulation signal; and the counting value of the detection timer is restored to zero, and a second pulse width modulation signal is output. The method and the device have the advantages that the current is sampled and the pulse width modulation signal is updated in the first interruption, the pulse width modulation signal is updated in the second interruption again, timers adopted by the current sampling and the pulse width modulation signal updating are all timers required by chip driving output, only three timers are used, one extra timer resource can be reduced, and the method and the device have good feasibility for scenes with a plurality of control objects.
Description
Technical Field
The application belongs to the technical field of motors, and particularly relates to a single-resistor current sampling method, a chip and electronic equipment.
Background
In an efficient variable frequency speed control system, accurate motor three-phase current acquisition is a key factor of system control, and current sampling schemes commonly used in the industrial field comprise Hall sensor sampling and bridge arm sampling, but the two schemes have high cost. With the continuous improvement of the demand of household appliances and other industries, the single-resistor current sampling mode is concerned more and more.
Currently, in the related art, a single-resistor current sampling reconstruction is performed based on a DSP (Digital Signal Processing) chip. The DSP includes a timer CTR (Counter) and two comparison registers CMP (Compare) a and CMPB, compares the value of the timer CTR with the values of CMPA and CMPB, generates a logic transition when the value of the timer CTR is equal to the values of CMPA and CMPB, and outputs an asymmetric PWM (Pulse width modulation) wave. The extra timer is responsible for triggering the sampling signal, and two triggering signals are generated by independently setting CMPA and CMPB to sample the bus current.
However, in the above related art, four timers are required for one control object, and when there are a plurality of control objects, the problem of insufficient chip resources is likely to occur.
Disclosure of Invention
The application provides a single-resistor current sampling method, a chip and electronic equipment, wherein two times of interruption are performed in one pulse width modulation period, a current is sampled and a pulse width modulation signal is updated in the first interruption, the pulse width modulation signal is updated again in the second interruption, a comparison register corresponding to a current sampling trigger signal is a comparison register of a timer adopted for updating the pulse width modulation signal, only three timers are used, one extra timer resource can be reduced, and the feasibility is good for scenes with a plurality of control objects.
An embodiment of a first aspect of the present application provides a single-resistor current sampling method, where the method includes:
detecting that the count value of a timer is zero, triggering a first interrupt, acquiring the current value flowing through a sampling resistor in the current period in the first interrupt, and modulating a first pulse width modulation signal in the first interrupt;
detecting that the count value of the timer is the maximum period value, outputting the first pulse width modulation signal, and triggering a second interrupt;
according to the first pulse width modulation signal, carrying out phase shift compensation on a second pulse width modulation signal modulated in the second interrupt;
and detecting that the count value of the timer is restored to zero, and outputting the second pulse width modulation signal.
In some embodiments of the present application, the obtaining, in the first interrupt, a current value flowing through a sampling resistor in a current cycle includes:
detecting sampling signals triggered by two first comparison registers in the first interrupt;
and collecting the current value flowing through the sampling resistor in the current period.
In some embodiments of the present application, said modulating a first pulse width modulated signal within said first interrupt comprises:
generating an initial pulse width modulation signal through a Space Vector Pulse Width Modulation (SVPWM) module;
and performing phase shift compensation on the initial pulse width modulation signal according to the minimum sampling time to obtain a first pulse width modulation signal in the first interrupt.
In some embodiments of the present application, the compensating for phase shift of the second pwm signal modulated in the second interrupt according to the first pwm signal includes:
calculating the pulse width and the phase-shifting time of the first pulse width modulation signal through an SVPWM module;
and reversely compensating the second pulse width modulation signal modulated in the second interrupt according to the pulse width and the phase shifting time.
In some embodiments of the present application, the method further comprises:
detecting that the count value of the timer is zero, and acquiring a current value sampled in the previous period;
and updating the current signal to the current value sampled in the last period.
In some embodiments of the present application, the method further comprises:
and executing a first control program with the updating frequency larger than a preset threshold value in the first interrupt.
In some embodiments of the present application, the method further comprises:
and executing a second control program with the updating frequency less than or equal to the preset threshold in the second interrupt.
An embodiment of the second aspect of the present application provides a chip, configured to perform the method described in the foregoing first aspect.
An embodiment of a third aspect of the present application provides an electronic device, including the chip of the second aspect.
In some embodiments of the present application, the electronic device comprises a motor, a compressor, an air conditioner, a wall breaking machine, a washing machine.
The technical scheme provided in the embodiment of the application at least has the following technical effects or advantages:
in the embodiment of the application, current sampling and two-time updating of pulse width modulation signals are performed in one pulse width modulation period, and only three timers required by chip drive output are used, so that compared with the prior art, one additional timer resource can be reduced, and the method is suitable for more occasions, for example, when a scheme that a single chip controls multiple motors or multiple motors and a rectifier is adopted, the feasibility of reconstructing current by adopting single-resistor sampling is realized. In addition, the embodiment of the application provides a program execution scheme in cooperation with the single resistance sampling reconstruction implementation scheme, and the execution frequency of the program can be ensured to be consistent with that of the traditional scheme, so that the overall operation characteristic of the system is not changed.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
Various additional advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings.
In the drawings:
fig. 1 is a schematic diagram illustrating an inverter-side system with single resistor sampling according to an embodiment of the present application;
FIG. 2 is a flow chart of a single resistor current sampling method according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating a single-resistor current sampling method according to an embodiment of the present application;
fig. 4 is a schematic diagram illustrating a program executed according to a single-resistor current sampling method provided in an embodiment of the present application;
FIG. 5 is a flow chart illustrating the execution of a program of a single resistor current sampling method according to an embodiment of the present application;
FIG. 6 is a diagram illustrating a comparison of a reconstructed current waveform and an actual current waveform corresponding to a single-resistor current sampling method according to an embodiment of the present disclosure;
fig. 7 shows a schematic structural diagram of a single-resistor current sampling apparatus according to an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The following describes a single-resistor current sampling method, a chip and an electronic device according to an embodiment of the present application with reference to the drawings.
Example 1
The embodiment of the application provides a single-resistor current sampling method, the structure of an inversion side system for single-resistor sampling is shown in fig. 1, and the core principle of single-resistor current sampling is to reconstruct three-phase current by sampling a current value flowing through a sampling resistor on a bus and combining a position interval of a motor. According to the embodiment of the application, no additional timer is needed in the single-resistor current sampling process, the current sampling and the updating of the pulse width modulation signals can be completed only by using the three timers required by the chip driving output, the timer resource is saved, and the application scene with a plurality of control objects is high in applicability. Referring to fig. 2, the method specifically includes the following steps:
step 101: and detecting that the count value of the timer is zero, triggering first interruption, acquiring the current value flowing through the sampling resistor in the current period in the first interruption, and modulating a first pulse width modulation signal in the first interruption.
The chip in the embodiment of the application can be a DSP (Digital Signal Processing) C2000 series chip, and can also be a chip with other resource types similar to the DSP C2000 series.
A compare register and a 16-bit increment/decrement timer are included in the chip. Wherein, the chip at least comprises 3 timers. The comparison registers include two first comparison registers and three second comparison registers, such as first comparison registers CMPB1 and CMPB2, and second comparison registers CMPA1, CMPA2, and CMPA3.
The method uses only three timers in the chip, referred to as a first timer, a second timer, and a third timer, respectively, for ease of description. The embodiment of the application monitors the first timer, the second timer and the third timer in real time, triggers the first interruption when the count values of the first timer, the second timer and the third timer are detected to be zero, and performs current sampling and updating of the pulse width modulation signal within the duration time of the first interruption.
In this embodiment of the present application, the chip includes an SVPWM (Space Vector Pulse Width Modulation) module, and the SVPWM module includes the first timer, the second timer, the third timer, and three second comparison registers. The SVPWM module is used for modulating a pulse width modulation signal. Specifically, an initial pulse width modulation signal is generated through an SVPWM module; and carrying out phase shift compensation on the initial pulse width modulation signal according to the minimum sampling time to obtain a first pulse width modulation signal in the first interrupt.
And the three second comparison registers are respectively used for the pulse control of the three phases of the motor. And during the duration of the first interrupt, comparing the count values of the first timer, the second timer and the third timer with the values of three second comparison registers through the SVPWM module, and when the count value of the timer is equal to the value of the second comparison register, generating a jump of a signal output by the second comparison register, thereby generating an initial pulse width modulation signal. And in the process of generating the pulse width modulation signal, performing phase shift compensation on the initial pulse width modulation signal according to the minimum sampling time to obtain a first pulse width modulation signal.
In this embodiment, the two first comparison registers are used to trigger the sampling signal. And also arbitrarily selecting two timers from the three timers, and configuring the two selected timers to trigger the sampling signal. It is assumed that the first timer and the second timer are configured for triggering the sampling signal. The count value of the first timer is also compared with the value of the first comparison register CMPB1 during the duration of the first interrupt and the sampling signal is triggered when the two values are equal. And comparing the count value of the second timer with the value of the second first comparison register CMPB2, and triggering the sampling signal when the two values are equal.
The chip thus detects the sampling signals triggered by the two first comparison registers in the first interrupt. And when a sampling signal triggered by any one first comparison register is detected, acquiring the current value of the current flowing through the sampling resistor.
After the current sampling of a plurality of pulse width modulation periods is carried out by the method of the embodiment of the application, the reconstruction of the three-phase current of the motor can be carried out according to the current value obtained by sampling and the voltage vector form of the inverter during each sampling.
In the embodiment of the application, in the first interruption, current sampling is performed twice, and the modulation of the first pulse width modulation signal is completed. And because the trigger of the sampling signal utilizes the timer required by the chip drive output, no additional timer is needed to participate, and the timer resource is saved.
In the embodiment of the present application, a first control program whose update frequency is greater than a preset threshold is also executed in the first interrupt. The preset threshold may be 60% or 70%, etc. The first control program comprises three-phase current reconstruction, current transformation, current loop control, output voltage inverse transformation and SVPWM modulation which are sequentially executed.
Step 102: and detecting that the count value of the timer is the maximum period value, outputting a first pulse width modulation signal and triggering a second interrupt.
And the chip monitors the timer in real time, and when detecting that the count values of the first timer, the second timer and the third timer are the maximum value of the period, the chip outputs the first pulse width modulation signal modulated in the step 101 and triggers a second interrupt.
Step 103: and performing phase shift compensation on the second pulse width modulation signal modulated in the second interrupt according to the first pulse width modulation signal.
In the duration of the second interruption, calculating the pulse width and the phase shift time of the first pulse width modulation signal through an SVPWM module; and reversely compensating the second pulse width modulation signal modulated in the second interrupt according to the calculated pulse width and the phase shift time.
Because two times of interruption are carried out in one pulse width modulation period and the phase shift compensation directions of the two times of interruption are opposite, the volt-second balance in the pulse width modulation period can be ensured.
Step 104: and the counting value of the detection timer is restored to zero, and a second pulse width modulation signal is output.
The chip monitors the timer in real time, and outputs the second pwm signal modulated in step 103 when detecting that the count values of the first timer, the second timer, and the third timer are returned to zero.
In the embodiment of the present application, a second control program whose update frequency is less than or equal to the preset threshold is also executed in the second interrupt. The second control program comprises a flux linkage observer, rotation speed estimation, rotation speed loop control, maximum torque current control and flux weakening control which are sequentially executed.
Therefore, compared with the conventional interrupt control mode, the execution frequency of the program in the scheme adopted by the embodiment of the application is not changed, and the overall control effect of the system is not changed.
To facilitate understanding of the methods provided by the embodiments of the present application, reference is made to fig. 3. Fig. 3 is a schematic diagram of single-resistor current sampling according to an embodiment of the present application, and the U, V, and W three-phase pulse width modulation signals shown in fig. 3 implement volt-second balance through reverse compensation. And in the rising stage of the count value of the timer, current sampling is carried out twice, the triggering of sampling signals AD _ Trigger1 and AD _ Trigger2 in two times utilizes the timer used by three-phase pulse width modulation, and an additional timer is not used.
The method can realize that one interruption is triggered when the count value of the timer is 0 and the count value of the timer is the maximum value of the period by configuration, and adopts a single-sampling double-comparison mode, namely, one interruption is triggered at the positions of a wave crest and a wave trough respectively in one pulse width modulation period, so that one current sampling and two updates of pulse width modulation signals are completed in one pulse width modulation period. The asymmetric pulse width modulation signal after phase shift compensation can be generated only by adopting the second comparison register, and the rest first comparison registers can be configured to finish trigger sampling in the half period of the ascending counting of the timer, so that single-resistor current sampling can be realized without an additional timer.
Fig. 4 shows a program execution principle under the single-resistor current sampling method provided in the embodiment of the present application. And completing the object control program once in one pulse width modulation period, and dividing the control program into a first control program and a second control program according to different update frequencies of the programs. And finishing the current signal updating at the trough position, wherein the updating value is the current value obtained by triggering sampling in the last period. One of the partial programs is executed in each of two interrupts of one pwm period. And in the first interrupt period (the ascending stage of the count value of the timer), the calculation of functions with higher updating frequency, such as current conversion, current loop, SVPWM modulation and the like, is completed in sequence. And finishing the calculation of functions with lower update frequency, such as voltage ring calculation, effective value calculation and the like in the second interrupt period, and inheriting the pulse width and the phase shift time of the first pulse width modulation signal calculated by the last interrupt SVPWM module. The compensation directions of the phase shift of two interrupts in one pulse width modulation period are opposite, so that the volt-second balance in the pulse width modulation period is ensured. Compared with the traditional pulse width modulation period single-interrupt control mode, the execution frequency of the program in the scheme adopted by the embodiment of the application is not changed, so that the overall control effect of the system is not changed.
FIG. 5 is a flow chart of a conventional FOC (field-oriented control, field-oriented vector control) process using a corresponding scheme of the present application. Firstly, judging whether the count value of the timer is increased, if so, sequentially executing three-phase current reconstruction, current conversion, current loop control, output voltage inverse conversion and SVPWM modulation in an interruption (namely a first interruption) corresponding to the rising stage of the count value of the timer. If not, sequentially executing flux linkage observer, rotating speed estimation, rotating speed loop control, maximum torque current control and field weakening control in the corresponding interruption (namely the second interruption) at the descending stage of the counting value of the timer. Phase-shifting and compensating the pulse width output after SVPWM in the first interruption according to the minimum sampling time Tmin, and outputting the pulse width output in the first interruption as t1/2+ delta t if the pulse width of an A-phase pulse width modulation signal output by the SVPWM module is t1 and the phase-shifting compensation time is delta t; and the second interrupt continues to use the result calculated by the SVPWM module in the first interrupt and outputs the pulse width with the time length t 1/2-delta t, thereby ensuring that the pulse width time length in one pulse width modulation period is consistent with the pulse width time length before phase shifting.
Fig. 6 shows the actual current waveform and the reconstructed current waveform of the motor side AB phase of the positionless permanent magnet synchronous motor FOC using the single-resistor current sampling reconstruction implementation shown in fig. 3 and the program execution implementations shown in fig. 4 and 5. As shown in the figure, the embodiment of the application can reliably sample and reconstruct the current of the motor, thereby realizing stable motor control.
The single-resistor current sampling of the embodiment of the application carries out once current sampling and twice updating of pulse width modulation signals in one pulse width modulation period, and only three timers required by chip driving output are utilized, so that an extra timer resource can be reduced compared with the prior art, the single-resistor current sampling method is suitable for more occasions, and the feasibility of adopting single-resistor sampling to reconstruct current is realized when a scheme that a single chip controls a plurality of motors or a plurality of motors and a rectifier is adopted. In addition, the embodiment of the application provides a program execution scheme in cooperation with the single resistance sampling reconstruction implementation scheme, and the execution frequency of the program can be ensured to be consistent with that of the traditional scheme, so that the overall operation characteristic of the system is not changed.
Example 2
An embodiment of the present application provides a single-resistor current sampling apparatus, which is configured to perform the single-resistor current sampling method described in the foregoing embodiment, and as shown in fig. 7, the apparatus includes:
a first interrupt module 201, configured to detect that a count value of the timer is zero, trigger a first interrupt, obtain a current value flowing through the sampling resistor in a current period in the first interrupt, and modulate a first pulse width modulation signal in the first interrupt;
a second interrupt module 202, configured to detect that a count value of the timer is a maximum period value, output a first pulse width modulation signal, and trigger a second interrupt;
the phase shift compensation module 203 is configured to perform phase shift compensation on the second pulse width modulation signal modulated in the second interrupt according to the first pulse width modulation signal;
and the signal output module 204 is configured to detect that the count value of the timer is restored to zero, and output a second pulse width modulation signal.
The first interrupt module 201 is configured to detect sampling signals triggered by two first comparison registers in a first interrupt; collecting the current value flowing through the sampling resistor in the current period; the SVPWM module is used for generating an initial pulse width modulation signal; and carrying out phase shift compensation on the initial pulse width modulation signal according to the minimum sampling time to obtain a first pulse width modulation signal in the first interrupt.
The phase shift compensation module 203 is configured to calculate a pulse width and a phase shift time of the first pulse width modulation signal through the SVPWM module; and reversely compensating the second pulse width modulation signal modulated in the second interrupt according to the pulse width and the phase shifting time.
The device also includes: the current updating module is used for detecting that the count value of the timer is zero and acquiring a current value sampled in the previous period; and updating the current signal to a current value sampled in the last period.
The device also includes: and the program execution module is used for executing a first control program with the updating frequency larger than a preset threshold value in the first interrupt and executing a second control program with the updating frequency smaller than or equal to the preset threshold value in the second interrupt.
The first control program comprises three-phase current reconstruction, current transformation, current loop control, output voltage inverse transformation and SVPWM modulation which are sequentially executed. The second control program comprises a flux linkage observer, rotation speed estimation, rotation speed loop control, maximum torque current control and flux weakening control which are sequentially executed.
The single-resistor current sampling provided by the embodiment of the application carries out current sampling and two-time updating of pulse width modulation signals in one pulse width modulation period, and only three timers required by chip drive output are utilized. In addition, the embodiment of the application provides a program execution scheme by matching with the single resistance sampling reconstruction implementation scheme, and the execution frequency of the program can be ensured to be consistent with that of the traditional scheme, so that the overall operation characteristic of the system is not changed.
Example 3
The embodiment of the application provides a chip, which can be a DSP series chip and any other chip supporting multiple interrupts. The chip comprises at least three timers, two first comparison registers for triggering sampling signals and three second comparison registers for modulating pulse width modulation signals. The chip is used for executing the single-resistor current sampling method in the embodiment.
In the process of executing the single-resistor current sampling method, the chip only needs to drive and output three timers required by the chip, compared with the prior art, one extra timer resource can be reduced, and the single-resistor current sampling method can be suitable for more occasions, for example, when a scheme that a single chip controls a plurality of motors or a plurality of motors and a rectifier is adopted, the feasibility of adopting single-resistor sampling to reconstruct current is realized. In addition, the embodiment of the application provides a program execution scheme in cooperation with the single resistance sampling reconstruction implementation scheme, and the execution frequency of the program can be ensured to be consistent with that of the traditional scheme, so that the overall operation characteristic of the system is not changed.
Example 4
The embodiment of the application provides an electronic device, which comprises the chip described in the embodiment, and the single-resistor current sampling method described in the embodiment is executed through the chip.
The electronic equipment can be any equipment with the chip, such as a motor, a compressor, an air conditioner, a wall breaking machine, a washing machine and the like.
In the process of executing the single-resistor current sampling method, the electronic equipment only needs three timers on a chip, one extra timer resource can be reduced compared with the prior art, and the method is suitable for more occasions, for example, when a scheme that a single chip controls a plurality of motors or a plurality of motors and a rectifier is adopted, the feasibility of adopting single-resistor sampling to reconstruct current is realized. In addition, the embodiment of the application provides a program execution scheme in cooperation with the single resistance sampling reconstruction implementation scheme, and the execution frequency of the program can be ensured to be consistent with that of the traditional scheme, so that the overall operation characteristic of the system is not changed.
Example 5
In order to implement the foregoing embodiments, the present application further proposes a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the non-transitory computer-readable storage medium implements the single-resistance current sampling method according to any one of the foregoing embodiments.
It should be noted that:
the algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. Various general purpose devices may be used with the teachings herein. The required structure for constructing an arrangement of this type will be apparent from the description above. In addition, this application is not directed to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present application as described herein, and any descriptions of specific languages are provided above to disclose the best modes of the present application.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the application and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.
The various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the creation apparatus of a virtual machine according to embodiments of the present application. The present application may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present application may be stored on a computer readable medium or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means can be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
The above description is only for the preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. The single-resistor current sampling method is characterized by being applied to a chip comprising comparison registers and a timer, wherein the comparison registers comprise two first comparison registers and three second comparison registers, and the second comparison registers are respectively used for pulse control of three phases of a motor; the timer comprises a first timer, a second timer and a third timer, and the first timer and the second timer are respectively matched with the two first comparison registers and used for triggering sampling; the method comprises the following steps:
detecting that the count values of the first timer, the second timer and the third timer are all zero, triggering a first interrupt, acquiring a current value flowing through a sampling resistor in the current period in the first interrupt, and modulating a first pulse width modulation signal in the first interrupt;
detecting that the count values of the first timer, the second timer and the third timer are all period maximum values, outputting the first pulse width modulation signal, and triggering a second interrupt;
performing phase shift compensation on a second pulse width modulation signal modulated in the second interrupt according to the first pulse width modulation signal;
detecting that the count values of the first timer, the second timer and the third timer are all restored to zero, and outputting the second pulse width modulation signal;
before obtaining the current value flowing through the sampling resistor in the current period, the method comprises the following steps:
comparing the count value of the first timer with the value of the first comparison register within the duration of the first interrupt, and triggering a sampling signal when the count value of the first timer is equal to the value of the first comparison register; and comparing the count value of the second timer with the value of the second first comparison register, and triggering the sampling signal when the count value of the second timer is equal to the value of the second first comparison register.
2. The method of claim 1, wherein obtaining the current value flowing through the sampling resistor in the current cycle in the first interrupt comprises:
detecting sampling signals triggered by two first comparison registers in the first interrupt;
and collecting the current value flowing through the sampling resistor in the current period.
3. The method of claim 1, wherein said modulating the first pulse width modulated signal within the first interrupt comprises:
generating an initial pulse width modulation signal through a Space Vector Pulse Width Modulation (SVPWM) module;
and carrying out phase shift compensation on the initial pulse width modulation signal according to the minimum sampling time to obtain a first pulse width modulation signal in the first interrupt.
4. The method of claim 1, wherein the compensating for phase shifting of the second pwm signal modulated within the second interrupt based on the first pwm signal comprises:
calculating the pulse width and the phase shift time of the first pulse width modulation signal through an SVPWM module;
and reversely compensating the second pulse width modulation signal modulated in the second interrupt according to the pulse width and the phase shift time.
5. The method of claim 1, further comprising:
detecting that the count values of the first timer, the second timer and the third timer are all zero, and acquiring a current value sampled in the previous period;
and updating the current signal to the current value sampled in the last period.
6. The method of claim 1, further comprising:
and executing a first control program with the updating frequency larger than a preset threshold value in the first interrupt.
7. The method of claim 6, further comprising:
and executing a second control program with the updating frequency less than or equal to the preset threshold in the second interrupt.
8. A chip for performing the method of any one of claims 1 to 7.
9. An electronic device comprising the chip of claim 8.
10. The electronic device of claim 9, wherein the electronic device is any one of a motor, a compressor, an air conditioner, a wall breaking machine, or a washing machine.
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