CN112909083B - High-voltage JFET device structure for improving withstand voltage reliability and manufacturing method thereof - Google Patents

Abstract

The invention provides a high-voltage JFET device structure for improving withstand voltage reliability and a manufacturing method thereof, DNW positioned in an active region; a second N+ region located on one side of the DNW inner edge; the first field oxide region is positioned on the surface of the DNW and takes the second N+ region as the center of a circle, and the P well is positioned on the surface in the DNW and takes the second N+ region as the center of a circle and surrounds the first field oxide region; a first P+ region and a first N+ region at the surface of the P well; the first polysilicon gate is positioned at the edge of the upper surface of the first N+ region and extends to the upper surface of the first field oxide region; the upper surface of one side of the first field oxide region, which is close to the second N+ region, is also provided with a second polysilicon gate; the first polysilicon gate and the second polysilicon gate are annular structures surrounding the second N+ region; the first P+ region and the first N+ region are connected to the first metal plate through the through holes above the first P+ region and the first N+ region respectively; the first metal plate extends to a position above the upper surface of the first field oxide region; the first metal plate is of an annular structure taking the second N+ region as a circle center; the annular structure forms a plurality of segmented hollow grooves in an annular direction thereof.

Description

A high-voltage JFET device structure with improved withstand voltage reliability and its manufacturing method

technical field

The invention relates to the technical field of semiconductors, in particular to a high-voltage JFET device structure with improved withstand voltage reliability and a manufacturing method thereof.

Background technique

At present, the high-voltage JFET device in the high-voltage BCD process (with a withstand voltage greater than 300V), in order to improve the breakdown voltage BV in the off state, two field plates of gate polysilicon and source metal are required on the field oxygen of the drift region near the channel side. , the metal field plate also needs to protrude from the gate polysilicon to form a stepped double field plate. The metal field plate needs to be connected to the gate (Poly) and the channel P well (PW) of the JFET device to be connected to zero potential. High-voltage JFET devices generally adopt a circular structure, with the high-voltage drain in the middle and the JFET channel PW on the outside. When such a source metal field plate is connected to the channel PW, the metal will cover the entire gate polysilicon Poly, forming a ring. The gate poly is generally etched and formed by plasma etching, and the number of residual charges after plasma etching increases as the area of the etched poly increases. These residual charges are generally eliminated by thermal annealing after metal etching, but if there is a metal cover on the Poly, it will affect the effect of elimination, especially for this high-voltage JFET device, the gate Poly has a large area and is covered with a metal layer , During thermal annealing, the residual charge will not be fully eliminated, resulting in increased device leakage and reduced withstand voltage.

Contents of the invention

In view of the above-mentioned shortcoming of prior art, the object of the present invention is to provide a kind of high-voltage JFET device structure and manufacturing method thereof that improves withstand voltage reliability, be used to solve the problem in the prior art that the metal plate above the polysilicon gate in the JFET device Covering leads to the problem that the residual charge cannot be sufficiently eliminated after thermal annealing of the gate polysilicon.

In order to achieve the above purpose and other related purposes, the present invention provides a high-voltage JFET device structure with improved withstand voltage reliability, at least including:

P-type substrate; an active region located on the P-type substrate; a DNW located in the active region;

A second N+ region located on one side of the inner edge of the DNW; a first field oxygen region located at the surface of the DNW and having an upper surface higher than the upper surface of the DNW, and the first field oxygen region is separated by the second The N+ region is the center of a circle, forming a ring structure surrounding the second N+ region; a P well located at the surface in the DNW, centered on the second N+ region and surrounding the first field oxygen region; There is an interval between the first field oxygen region and the P well;

The first P+ region and the first N+ region located at the surface of the P well; wherein the first N+ region is closer to the first field oxygen region than the first P+ region; located in the first N+ region The edge of the upper surface and extending to the first polysilicon gate on the upper surface of the first field oxygen region; the upper surface of the first field oxygen region close to the second N+ region is also provided with a second polysilicon gate gate; both the first and second polysilicon gates are annular structures surrounding the second N+ region;

The first P+ region and the first N+ region are respectively connected to the first metal plate through through holes above each; the first metal plate extends in its plane until the first polysilicon gate is located on the first metal plate. Above one end of the upper surface of the field oxygen region; and the first metal plate is an annular structure centered on the second N+ region; and the annular structure forms a plurality of segmented hollow grooves in its annular direction;

The second N+ region and the second polysilicon gate are connected to the second metal plate through through holes located above each other.

Preferably, the high-voltage JFET device structure further includes: a second field oxygen region located at the surface of the DNW and having an upper surface higher than the upper surface of the DNW; the second field oxygen region is located at the P well away from the side of the first polysilicon gate.

Preferably, the first metal plate is the gate of the high voltage JFET device structure.

Preferably, the second metal plate is the drain of the high voltage JFET device structure.

Preferably, the high voltage JFET device structure further includes a third N+ region located on the inner surface of the DNW, and the third N+ region is located on a side of the second field oxygen region away from the first P+ region.

Preferably, the third N+ region is connected to a third metal plate through a via hole thereon, and the third metal plate is the source of the high voltage JFET device structure.

Preferably, the high-voltage JFET device structure further includes a third field oxygen region located at the junction of the DNW and the P-type substrate and having an upper surface higher than the upper surface of the DNW, and the third field oxygen region is located at The side of the third N+ region away from the second field oxygen region.

Preferably, the high-voltage JFET device structure further includes a second P+ region located on the inner surface of the P-type substrate, and the second P+ region is connected to the fourth metal plate through a via hole thereon.

The present invention also provides the manufacturing method of the high-voltage JFET device structure with improved withstand voltage reliability, at least including:

Step 1, providing a P-type substrate, and forming a DNW on the P-type substrate;

Step 2, forming an annular first field oxygen region with the second N+ region as the center between the first N+ region and the second N+ region; between the third N+ region and the first An annular second field oxygen region centered on the second N+ region is formed between the P+ regions;

Step 3, forming an annular P well in the DNW;

Step 4, forming a first polysilicon gate located at the edge of the upper surface of the first N+ region and extending to the upper surface of the first field oxygen region; in the first field oxygen region close to the second N+ region A second polysilicon gate is formed on the upper surface of the side;

Step 5, forming a second N+ region at the surface in the P well; the annular P well is a ring structure with the second N+ region as the center; forming a first N+ region at the surface in the P well. An N+ region and a first P+ region; and the first N+ region is closer to the second N+ region than the first P+ region; the first P+ region on the side away from the first N+ region A third N+ region is formed at the surface inside the DNW; a second P+ region is formed at the surface inside the P-type substrate outside the DNW, and the second P+ region is located far away from the third N+ region. one side of the first P+ region;

Step 6, covering the dielectric layer; and forming via holes on the upper surface of the first P+ region, the first N+ region, the second N+ region, the third N+ region and the upper surface of the second polysilicon gate;

Step 7, forming a metal layer on the dielectric layer, etching the metal layer, forming a first metal plate in the through holes above the first P+ region and the first N+ region, and the first metal plate extends to The first polysilicon gate is located above one end of the upper surface of the first field oxygen region, and the first metal plate is a ring structure with the second N+ region as the center; the ring structure is in its ring direction A plurality of segmented hollow grooves are formed; through holes above the second N+ region and the second polysilicon gate form a second metal plate.

As mentioned above, the high-voltage JFET device structure and its manufacturing method with improved withstand voltage reliability of the present invention have the following beneficial effects: In order to expose as many polysilicon regions as possible, especially the gate oxide region under the polysilicon gate, the present invention , to release the residual charge, and the metal field plate covering it is designed to be slotted. By optimizing the layout of the metal field plate near the JFET channel side, the whole metal is divided into several segments to maintain the premise of the field plate effect Next, the problem of insufficient elimination of residual charge after thermal process caused by metal covering is eliminated.

Description of drawings

Fig. 1 is shown as the longitudinal section schematic diagram of the high voltage JFET device structure of improving withstand voltage reliability of the present invention;

FIG. 2 is a schematic diagram of the layout structure of the high-voltage JFET device structure with improved withstand voltage reliability of the present invention.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 2. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

The present invention provides a high-voltage JFET device structure with improved withstand voltage reliability, which at least includes:

P-type substrate; an active region located on the P-type substrate; a DNW located in the active region; a second N+ region located on one side of the inner edge of the DNW; located at the surface of the DNW and on the The surface is higher than the first field oxygen region on the upper surface of the DNW, and the first field oxygen region takes the second N+ region as the center to form a ring structure surrounding the second N+ region; it is located in the DNW at the surface of the surface, with the second N+ region as the center and surrounding the P well of the first field oxygen region; there is an interval between the first field oxygen region and the P well; the P well located in the P well The first P+ region and the first N+ region at the surface; wherein the first N+ region is closer to the first field oxygen region than the first P+ region; it is located at the edge of the upper surface of the first N+ region and extends to the The first polysilicon gate on the upper surface of the first field oxygen region; the upper surface of the first field oxygen region close to the second N+ region is also provided with a second polysilicon gate; the first, The second polysilicon gates are ring structures surrounding the second N+ region;

The first P+ region and the first N+ region are respectively connected to the first metal plate through through holes above each; the first metal plate extends in its plane until the first polysilicon gate is located on the first metal plate. Above one end of the upper surface of the field oxygen region; and the first metal plate is a ring structure centered on the second N+ region; and the ring structure forms a plurality of segmented hollow grooves in its ring direction; the The second N+ region and the second polysilicon gate are connected to the second metal plate through through holes located above each other.

As shown in Figure 1, Fig. 1 shows the vertical cross-sectional schematic view of the high-voltage JFET device structure of the present invention that improves withstand voltage reliability, and this high-voltage JFET device structure comprises in the present embodiment: P-type substrate (PSUB); The active area AA on the P-type substrate; the DNW (N-type deep well) located in the active area;

The high-voltage JFET device structure also includes: a second N+ region 01 located on one side of the inner edge of the DNW (N-type deep well); a first field oxygen located at the surface of the DNW and having an upper surface higher than the upper surface of the DNW region 02, and the first field oxygen region 02 takes the second N+ region 01 as the center to form a ring structure surrounding the second N+ region 01; as shown in Figure 2, Figure 2 shows the improvement of the present invention Schematic diagram of the layout structure of the high-voltage JFET device structure with withstand voltage reliability. The Drain in FIG. 2 is the drain formed by the metal above the second N+ region 01 .

As shown in FIG. 1 , the high-voltage JFET device structure further includes: a surface located in the DNW (N-type deep well), centered on the second N+ region 01 and surrounding the first field oxygen region 02 P well (PW); there is an interval between the first field oxygen region and the P well in FIG. 1 ;

The high voltage JFET device structure also includes a first P+ region 03 and a first N+ region 04 located at the surface of the P well (PW); wherein the first N+ region 04 is closer to the first P+ region 03 than the first P+ region 03 The oxygen zone 02 of the first field;

And the high-voltage JFET device structure also includes a first polysilicon gate 05 located at the edge of the upper surface of the first N+ region 04 and extending to the upper surface of the first field oxygen region 02; the first field oxygen region 02 is close to The upper surface of one side of the second N+ region 01 is also provided with a second polysilicon gate 06; the first polysilicon gate 05 and the second polysilicon gate 06 are all surrounding the second N+ region 01 ring structure; as shown in FIG. 2 , both the first polysilicon gate 05 and the second polysilicon gate 06 are ring structures surrounding the second N+ region (Drain).

The first P+ region 03 and the first N+ region 04 in FIG. The polysilicon gate 05 is located above one end of the upper surface of the first field oxygen region 02; that is, the plane where the first metal plate is located is a horizontal plane above the substrate as shown in FIG. 1 , as shown in FIG. 2, and the first metal plate 08 is an annular structure centered on the second N+ region 01 (Drain); and the annular structure forms a plurality of segmented hollow grooves 09 in its annular direction, FIG. 2 The part between the two rings formed by the medium black thick line constitutes the first metal plate 08 , and there are four segmented hollow grooves 09 inside the first metal plate 08 .

As shown in FIG. 1 , the second N+ region 01 and the second polysilicon gate 06 are connected to the second metal plate 10 through through holes 07 respectively located above them.

As shown in Figure 1, the present invention further includes that the high-voltage JFET device structure in this embodiment further includes: a second field oxygen region 11 located at the surface of the DNW and having an upper surface higher than the upper surface of the DNW; The second field oxygen region 11 is located on a side of the P well (PW) away from the first polysilicon gate 05 .

In this embodiment, the first metal plate 08 is the gate of the high voltage JFET device structure; the second metal plate 10 is the drain of the high voltage JFET device structure.

As shown in Figure 1, the present invention further, the high-voltage JFET device structure in this embodiment also includes a third N+ region 12 located at the inner surface of the DNW, and the third N+ region 12 is located at the second The field oxygen region 11 is away from the side of the first P+ region 03 .

Further in the present invention, in this embodiment, the third N+ region 12 is connected to the third metal plate 13 through a through hole on it, and the third metal plate 13 is the source of the high-voltage JFET device structure (Source ).

As shown in Fig. 1, further in the present invention, the high-voltage JFET device structure in this embodiment also includes a third field located at the junction of the DNW and the P-type substrate and whose upper surface is higher than the upper surface of the DNW oxygen region 14, and the third field oxygen region 14 is located on the side of the third N+ region 12 away from the second field oxygen region 11.

Further in the present invention, the high-voltage JFET device structure in this embodiment also includes a second P+ region 15 located at the inner surface of the P-type substrate, and the second P+ region 15 is connected to the first Four metal plates 16 .

The present invention also includes: a dielectric layer 17 located below the first and second metal plates.

The present invention also provides the manufacturing method of the high-voltage JFET device structure with improved withstand voltage reliability, referring to Fig. 1, the improved method at least includes the following steps:

Step 1, providing a P-type substrate (PSUB), forming a DNW (N-type deep well) on the P-type substrate;

Step 2, forming an annular first field oxygen region 02 with the second N+ region 01 as the center between the first N+ region 04 and the second N+ region 01; in the third N+ region 12 An annular second field oxygen region 11 centered on the second N+ region 01 is formed between the first P+ region 03 and the first P+ region 03;

Step 3, forming an annular P well (PW) in the DNW (N-type deep well);

Step 4, forming a first polysilicon gate 05 located at the edge of the upper surface of the first N+ region 04 and extending to the upper surface of the first field oxygen region 02; A second polysilicon gate 06 is formed on the upper surface of one side of the N+ region 01;

Step 5, forming a second N+ region 01 at the surface in the P well (PW); the annular P well (PW) is an annular structure with the second N+ region 01 as the center; in the P A first N+ region 04 and a first P+ region 03 are formed on the surface of the well (PW); and the first N+ region 04 is closer to the second N+ region 01 than the first P+ region 03; A third N+ region 12 is formed at the surface of the DNW on the side of the P+ region 03 away from the first N+ region 04; a second P+ region is formed at the surface of the P-type substrate outside the DNW. region 15, and the second P+ region 15 is located on the side of the third N+ region 12 away from the first P+ region 03;

Step 6, covering the dielectric layer 17; and forming on the upper surface of the first P+ region 03, the first N+ region 04, the second N+ region 01, the third N+ region 12 and the second polysilicon gate 06 through hole 07;

Step 7, forming a metal layer on the dielectric layer 17, etching the metal layer, forming a first metal plate 08 in the through holes above the first P+ region 03 and the first N+ region 01, the first The metal plate extends until the first polysilicon gate 05 is located above one end of the upper surface of the first field oxygen region 02, as shown in FIG. 2, and the first metal plate 08 is formed by the second N+ region 01 is an annular structure at the center of the circle; the annular structure forms a plurality of segmented hollow grooves 09 in its annular direction; the through holes above the second N+ region 01 and the second polysilicon gate 06 form a second metal plate 10.

In summary, in order to expose as many polysilicon regions as possible, especially the gate oxide region below the polysilicon gate, the present invention releases residual charges, and the metal field plate covering it is designed in the form of a slot. The optimization of the metal field plate layout on the channel side of the JFET divides the whole metal into several segments, and under the premise of maintaining the field plate effect, the problem of insufficient elimination of residual charges after the thermal process caused by metal coverage is eliminated. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (9)

1. A high-voltage JFET device structure improving withstand voltage reliability, characterized in that it at least includes: P-type substrate; an active region located on the P-type substrate; an N-type deep well located in the active region; The second N+ region located on one side of the inner edge of the N-type deep well; the first field oxygen region located at the surface of the N-type deep well and whose upper surface is higher than the upper surface of the N-type deep well, and the first A field oxygen region takes the second N+ region as the center to form a ring structure surrounding the second N+ region; it is located at the surface in the N-type deep well, takes the second N+ region as the center and surrounds the second N+ region The P well of the first field oxygen region; there is an interval between the first field oxygen region and the P well; The first P+ region and the first N+ region located at the surface of the P well; wherein the first N+ region is closer to the first field oxygen region than the first P+ region; located in the first N+ region The edge of the upper surface and extending to the first polysilicon gate on the upper surface of the first field oxygen region; the upper surface of the first field oxygen region close to the second N+ region is also provided with a second polysilicon gate gate; both the first and second polysilicon gates are annular structures surrounding the second N+ region; The first P+ region and the first N+ region are respectively connected to the first metal plate through through holes above each; the first metal plate extends in its plane until the first polysilicon gate is located on the first metal plate. Above one end of the upper surface of the field oxygen region; and the first metal plate is an annular structure centered on the second N+ region; and the annular structure forms a plurality of segmented hollow grooves in its annular direction; The second N+ region and the second polysilicon gate are connected to the second metal plate through through holes located above each other. 2. The high-voltage JFET device structure for improving withstand voltage reliability according to claim 1, characterized in that: the high-voltage JFET device structure further comprises: being located at the surface of the N-type deep well and having an upper surface higher than the N The second field oxygen region on the upper surface of the type deep well; the second field oxygen region is located on the side of the P well away from the first polysilicon gate. 3. The high-voltage JFET device structure with improved withstand voltage reliability according to claim 1, wherein the first metal plate is a gate of the high-voltage JFET device structure. 4. The high-voltage JFET device structure with improved withstand voltage reliability according to claim 1, wherein the second metal plate is the drain of the high-voltage JFET device structure. 5. The high-voltage JFET device structure improving withstand voltage reliability according to claim 2, characterized in that: the high-voltage JFET device structure also includes a third N+ region located at the inner surface of the N-type deep well, and the The third N+ region is located on a side of the second field oxygen region away from the first P+ region. 6. The high-voltage JFET device structure with improved withstand voltage reliability according to claim 5, characterized in that: the third N+ region is connected to a third metal plate through a through hole located thereon, and the third metal plate is the source of the high voltage JFET device structure. 7. The high-voltage JFET device structure for improving withstand voltage reliability according to claim 5, characterized in that: the high-voltage JFET device structure also includes a junction between the N-type deep well and the P-type substrate and on the top The surface is higher than the third field oxygen region on the upper surface of the N-type deep well, and the third field oxygen region is located on the side of the third N+ region away from the second field oxygen region. 8. The high-voltage JFET device structure for improving withstand voltage reliability according to claim 1, characterized in that: the high-voltage JFET device structure also includes a second P+ region located at the inner surface of the P-type substrate, and the first The second P+ region is connected to the fourth metal plate through a via hole thereon. 9. The method for manufacturing a high-voltage JFET device structure for improving withstand voltage reliability according to any one of claims 1 to 8, characterized in that: at least comprising: Step 1, providing a P-type substrate, and forming an N-type deep well on the P-type substrate; Step 2, forming an annular first field oxygen region with the second N+ region as the center between the first N+ region and the second N+ region; between the third N+ region and the first An annular second field oxygen region centered on the second N+ region is formed between the P+ regions; Step 3, forming an annular P well in the N-type deep well; Step 4, forming a first polysilicon gate located at the edge of the upper surface of the first N+ region and extending to the upper surface of the first field oxygen region; in the first field oxygen region close to the second N+ region A second polysilicon gate is formed on the upper surface of the side; Step 5, forming a second N+ region at the surface in the P well; the annular P well is a ring structure with the second N+ region as the center; forming a first N+ region at the surface in the P well. An N+ region and a first P+ region; and the first N+ region is closer to the second N+ region than the first P+ region; the first P+ region on the side away from the first N+ region A third N+ region is formed at the surface in the N-type deep well; a second P+ region is formed at the surface in the P-type substrate outside the N-type deep well, and the second P+ region is located in the first N-type deep well. The side of the three N+ regions away from the first P+ region; Step 6, covering the dielectric layer; and forming via holes on the upper surface of the first P+ region, the first N+ region, the second N+ region, the third N+ region and the upper surface of the second polysilicon gate; Step 7, forming a metal layer on the dielectric layer, etching the metal layer, forming a first metal plate in the through holes above the first P+ region and the first N+ region, and the first metal plate extends to The first polysilicon gate is located above one end of the upper surface of the first field oxygen region, and the first metal plate is a ring structure with the second N+ region as the center; the ring structure is in its ring direction A plurality of segmented hollow grooves are formed; through holes above the second N+ region and the second polysilicon gate form a second metal plate.