CN112908971A - Semiconductor packaging structure, manufacturing method thereof and semiconductor device - Google Patents
Semiconductor packaging structure, manufacturing method thereof and semiconductor device Download PDFInfo
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- CN112908971A CN112908971A CN202110117983.7A CN202110117983A CN112908971A CN 112908971 A CN112908971 A CN 112908971A CN 202110117983 A CN202110117983 A CN 202110117983A CN 112908971 A CN112908971 A CN 112908971A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 67
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000002184 metal Substances 0.000 claims abstract description 113
- 238000000034 method Methods 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 26
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 claims 1
- 238000000465 moulding Methods 0.000 description 10
- 150000001875 compounds Chemical class 0.000 description 7
- 230000010354 integration Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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Abstract
The invention provides a packaging structure and a semiconductor device. The semiconductor package structure includes: a plastic packaging layer; the first interconnection structure layer is positioned on the surface of one side of the plastic packaging layer and comprises a first metal layer; the adapter plate is positioned in the plastic package layer, the plane extending from the plate body is perpendicular to the first interconnection structure layer, an adapter plate metal layer is arranged in the adapter plate, and the adapter plate metal layer is connected with the first metal layer; the first chip is positioned on the surface of one side, facing the plastic package layer, of the first interconnection structure layer, the first chip is connected with the first metal layer, and the plastic package layer wraps the first chip; the second chip is positioned on the surface of one side, facing the plastic packaging layer, of the first interconnection structure layer, is connected with the first metal layer, and wraps the first chip; the first chip and the second chip are different types of chips and are respectively positioned on two sides of the adapter plate.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure, a manufacturing method thereof and a semiconductor device.
Background
In a system-in-package semiconductor package structure, high-density interconnection is generally required for different chips in the same layer. It is common practice to implement interconnections by densely routing a plurality of planar interconnection lines. However, this method requires multi-layer wiring, and the line width and line distance are large due to process limitations, so that the wiring area occupies a large area on the horizontal plane of the package structure, which is not favorable for miniaturization of the package structure in the horizontal direction.
Disclosure of Invention
Therefore, the invention provides a semiconductor packaging structure, a manufacturing method thereof and a semiconductor device, which aim to solve the problem that the miniaturization of the packaging structure is influenced by the interconnection of different chips in the same layer of a system-level semiconductor packaging structure and the wiring area of a plane interconnection line.
The invention provides a semiconductor packaging structure, comprising: a plastic packaging layer; the first interconnection structure layer is positioned on the surface of one side of the plastic packaging layer and comprises a first metal layer; the adapter plate is positioned in the plastic package layer, the plane extending from the plate body is perpendicular to the first interconnection structure layer, an adapter plate metal layer is arranged in the adapter plate, and the adapter plate metal layer is connected with the first metal layer; the first chip is positioned on the surface of one side, facing the plastic package layer, of the first interconnection structure layer, the first chip is connected with the first metal layer, and the plastic package layer wraps the first chip; the second chip is positioned on the surface of one side, facing the plastic packaging layer, of the first interconnection structure layer and is connected with the first metal layer, and the plastic packaging layer wraps the second chip; the first chip and the second chip are different types of chips and are respectively positioned on two sides of the adapter plate.
Optionally, the interposer includes a board body, the board body has a first surface and a second surface opposite to each other, the first surface and the second surface are two surfaces with the largest area in each surface of the board body, respectively, and the first surface is perpendicular to the first interconnection structure layer; the second surface is vertical to the first interconnection structure layer; the first surface is provided with a first bottom edge, a plurality of first bottom edge connecting pins are arranged on one side of the first bottom edge of the first surface, and the plurality of first bottom edge connecting pins are connected with the first metal layer; the plurality of first bottom edge pins are also connected with the metal layer of the adapter plate; the second surface is provided with a second bottom edge, a plurality of second bottom edge connecting pins are arranged on one side of the second bottom edge of the second surface, and the plurality of second bottom edge connecting pins are connected with the first metal layer; the second bottom edge pins are also connected with the metal layer of the adapter plate.
Optionally, the plurality of first bottom edge pins are arranged in parallel with the first bottom edge, and the plurality of second bottom edge pins are arranged in parallel with the second bottom edge.
Optionally, the number of the first chips is multiple; and/or the number of the second chips is multiple.
Optionally, the first surface is further provided with a plurality of contacts, the second surface is further provided with a plurality of contacts, and the interposer metal layer is connected to the plurality of contacts of the first surface and the plurality of contacts of the second surface; the first surface is provided with a third element, and the third element is connected with the metal layer of the adapter plate through a contact point of the first surface; and/or the second surface is provided with a third element, and the third element is connected with the metal layer of the adapter plate through a contact point of the second surface;
optionally, the third element is a passive device or a chip.
The invention also provides a manufacturing method of the semiconductor packaging structure, which comprises the following steps: forming a plastic packaging layer; forming a first interconnection structure layer, wherein the first interconnection structure layer is positioned on the surface of one side of the plastic packaging layer and comprises a first metal layer; arranging an adapter plate, wherein the adapter plate is positioned in the plastic packaging layer, the plane extending by the plate body is vertical to the first interconnection structure layer, and an adapter plate metal layer is arranged in the adapter plate and connected with the first metal layer; mounting a first chip, wherein the first chip is positioned on the surface of one side, facing the plastic package layer, of the first interconnection structure layer, the first chip is connected with the first metal layer, and the plastic package layer wraps the first chip; mounting a second chip, wherein the second chip is positioned on the surface of one side, facing the plastic packaging layer, of the first interconnection structure layer, the second chip is connected with the first metal layer, and the plastic packaging layer wraps the second chip; the first chip and the second chip are different types of chips and are respectively positioned on two sides of the adapter plate.
Optionally, the interposer includes a board body, the board body has a first surface and a second surface opposite to each other, the first surface and the second surface are two surfaces with the largest area in each surface of the board body, respectively, and the first surface is perpendicular to the first interconnection structure layer; the second surface is vertical to the first interconnection structure layer; the first surface has a first bottom edge, and the manufacturing method of the semiconductor packaging structure comprises the following steps: forming a plurality of first bottom edge connecting pins on one side of the first bottom edge of the first surface, wherein the plurality of first bottom edge connecting pins are connected with the first metal layer; the plurality of first bottom edge pins are also connected with the metal layer of the adapter plate; the second surface has a second bottom edge, and the manufacturing method of the semiconductor packaging structure further comprises the following steps: forming a plurality of second bottom edge connecting pins on one side of a second bottom edge of the second surface, wherein the plurality of second bottom edge connecting pins are connected with the first metal layer; the second bottom edge pins are also connected with the metal layer of the adapter plate.
Optionally, the manufacturing method of the semiconductor package structure sequentially includes the following steps: providing a substrate, and forming a plurality of metal bumps on the substrate; connecting a plurality of first bottom edge pins and a plurality of second bottom edge pins of the adapter plate to the first substrate through a plurality of metal bumps; respectively mounting the first chip and the second chip to a substrate; forming a plastic packaging layer, wherein the plastic packaging layer coats the first chip, the second chip and the adapter plate; removing the substrate; forming a first interconnection structure layer, wherein the first interconnection structure layer covers the surface of the first chip facing the substrate, the surface of the second chip facing the substrate, the surface of the interposer facing the substrate and the surface of the plastic package layer facing the substrate; and forming a solder ball on one side of the first interconnection structure layer, which is back to the plastic packaging layer, wherein the solder ball is connected with the first metal layer.
Optionally, the manufacturing method of the semiconductor package structure further includes the following steps: forming a plurality of contacts on the first surface, forming a plurality of contacts on the second surface, and connecting the plurality of contacts on the first surface and the plurality of contacts on the second surface by the adapter plate metal layer; attaching a third element to the first surface, wherein the third element is connected with the adapter plate metal layer through a contact point of the first surface; and/or attaching a third element to the second surface, wherein the third element is connected with the adapter plate metal layer through the contact points of the second surface.
The invention also provides a semiconductor device comprising the semiconductor packaging structure.
The technical scheme of the invention has the following advantages:
1. according to the semiconductor packaging structure, the adapter plate is perpendicular to the first interconnection structure layer, so that the adapter plate is vertically arranged in the plastic packaging layer on the first interconnection structure layer, and the first chip and the second chip on two sides of the adapter plate are interconnected through the first metal layer and the adapter plate. Compared with the interconnection mode of the planar interconnection line, the process of the patch panel wiring can realize higher precision and smaller line width and line distance than the processing process of dense wiring of the planar interconnection line, so that the process can realize higher density and occupy smaller area than the planar interconnection line. In addition, because the adapter plate is vertically arranged, the routing of part of the plane interconnection line in the plane horizontal direction is changed into the vertical direction, the occupied area of a wiring area can be reduced, and the miniaturization of the packaging structure in the horizontal direction is facilitated.
2. According to the semiconductor packaging structure, the first bottom edge pin and the second bottom edge pin are connected to the first metal layer, and the plurality of first bottom edge pins and the plurality of second bottom edge pins are respectively connected with the adapter plate, so that on one hand, the upright position of the adapter plate is realized, and on the other hand, the first chip and the second chip on two sides of the adapter plate are interconnected through the first metal layer and the adapter plate. Compared with the interconnection mode of the planar interconnection line, the process of the patch panel wiring can realize higher precision and smaller line width and line distance than the processing process of dense wiring of the planar interconnection line, so that the process can realize higher density and occupy smaller area than the planar interconnection line. In addition, because the adapter plate is vertically arranged, part of the routing in the plane horizontal direction of the plane interconnection line is changed into the vertical direction, the occupied area of a wiring area can be reduced, and the miniaturization of the semiconductor packaging structure in the horizontal direction is facilitated.
3. In the semiconductor package structure of the invention, the plurality of first bottom edge connecting pins are arranged in parallel to the first bottom edge, and the plurality of second bottom edge connecting pins are arranged in parallel to the second bottom edge. The pins arranged in parallel are easy to realize the welding balance, and the condition that the individual pins are disconnected due to unbalanced welding can be avoided.
4. According to the semiconductor packaging structure, the first surface and the second surface are provided with the plurality of connecting points for connecting the adapter plate metal layers, the first surface and/or the second surface of the adapter plate can be provided with the third element, and the third element is connected with the adapter plate metal layers through the connecting points, so that interconnection with other elements in the packaging structure and fan-out on the same side can be realized, and the integration level of the device can be improved.
5. According to the semiconductor packaging structure manufactured by the manufacturing method of the semiconductor packaging structure, the adapter plate is perpendicular to the first interconnection structure layer, so that the adapter plate is vertically arranged in the plastic packaging layer on the first interconnection structure layer, and the first chip and the second chip on two sides of the adapter plate are interconnected through the first metal layer and the adapter plate. Compared with the interconnection mode of the planar interconnection line, the process of the patch panel wiring can realize higher precision and smaller line width and line distance than the processing process of dense wiring of the planar interconnection line, so that the process can realize higher density and occupy smaller area than the planar interconnection line. In addition, because the adapter plate is vertically arranged, the routing of part of the plane interconnection line in the plane horizontal direction is changed into the vertical direction, the occupied area of a wiring area can be reduced, and the miniaturization of the packaging structure in the horizontal direction is facilitated.
6. According to the semiconductor packaging structure manufactured by the manufacturing method of the semiconductor packaging structure, the plurality of first bottom edge pins and the plurality of second bottom edge pins are formed, the first bottom edge pins and the second bottom edge pins are connected to the first metal layer, and the adapter plate metal layer is connected with the plurality of first bottom edge pins and the plurality of second bottom edge pins, so that the adapter plate is erected on one hand, and the first chip and the second chip on two sides of the adapter plate are interconnected through the first metal layer and the adapter plate on the other hand. Compared with the interconnection mode of the planar interconnection line, the process of the patch panel wiring can realize higher precision and smaller line width and line distance than the processing process of dense wiring of the planar interconnection line, so that the process can realize higher density and occupy smaller area than the planar interconnection line. In addition, because the adapter plate is vertically arranged, part of the routing in the plane horizontal direction of the plane interconnection line is changed into the vertical direction, the occupied area of a wiring area can be reduced, and the miniaturization of the semiconductor packaging structure in the horizontal direction is facilitated.
7. According to the semiconductor packaging structure manufactured by the manufacturing method of the semiconductor packaging structure, the plurality of connecting points are formed on the adapter plate, the third element can be arranged on the first surface and/or the second surface of the adapter plate, and the third element is connected with the metal layer of the adapter plate through the connecting points, so that interconnection with other elements in the packaging structure and fan-out on the same side can be realized, and the integration level of the device is improved.
8. The semiconductor device comprises the semiconductor packaging structure, the adapter plate is vertically arranged in the plastic packaging layer on the first interconnection structure layer through the arrangement that the adapter plate is perpendicular to the first interconnection structure layer, and the first chip and the second chip on two sides of the adapter plate are interconnected through the first metal layer and the adapter plate. Compared with the interconnection mode of the planar interconnection line, the process of the patch panel wiring can realize higher precision and smaller line width and line distance than the processing process of dense wiring of the planar interconnection line, so that the process can realize higher density and occupy smaller area than the planar interconnection line. In addition, because the adapter plate is vertically arranged, the routing of part of the plane interconnection line in the plane horizontal direction is changed into the vertical direction, the occupied area of a wiring area can be reduced, and the miniaturization of the packaging structure in the horizontal direction is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIGS. 1-7 are schematic diagrams of various states in the fabrication of a semiconductor package structure according to an embodiment of the present application;
FIG. 3 is a side view of one side of the first surface of the interposer;
fig. 7 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a semiconductor package structure in another embodiment of the present application.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
Referring to fig. 1 to 8, the present embodiment provides a semiconductor package structure, including:
and a molding layer 400.
The first interconnect structure layer 500, the first interconnect structure layer 500 is located on one side surface of the plastic package layer 400, and the first interconnect structure layer 500 includes a first metal layer 501 and a first insulating dielectric layer 502.
The interposer 300, the interposer 300 is located in the plastic package layer 400, a plane of the interposer 300 extending itself is perpendicular to the first interconnect structure layer 500, and an interposer metal layer (not shown) is disposed in the interposer 300 and connected to the first metal layer 501.
The first chip 100, the first chip 100 is located on a surface of the first interconnect structure layer 500 facing the molding compound layer 400, the first chip 100 is connected to the first metal layer 501, and the molding compound layer 400 covers the first chip 100.
And the second chip 200, wherein the second chip 200 is located on the surface of the first interconnection structure layer 500 facing the side of the plastic package layer 400, the second chip 200 is connected to the first metal layer 501, and the plastic package layer 400 covers the second chip 200.
The first chip 100 and the second chip 200 are different kinds of chips, and the first chip 100 and the second chip 200 are respectively located on two sides of the interposer 300.
For example, the first chip 100 and the second chip 200 may be a Field Programmable Gate Array (FPGA) chip and a double data rate synchronous dynamic random access memory (DDR) chip, respectively.
In the semiconductor package structure of the embodiment, the interposer 300 is perpendicular to the first interconnect structure layer 500, so that the interposer 300 is vertically disposed in the plastic package layer 400 on the first interconnect structure layer 500, and the first chip 100 and the second chip 200 on two sides of the interposer 300 are interconnected through the first metal layer 501 and the interposer 300. Compared with the interconnection mode of the planar interconnection line, the process of wiring of the adapter plate 300 can realize higher precision and smaller line width and line distance than the dense wiring processing process of the planar interconnection line, so that higher density and smaller occupied area than the planar interconnection line can be realized. In addition, because the adapter plate 300 is vertically arranged, part of the routing in the plane horizontal direction in the plane interconnection line is changed into the vertical direction, the occupied area of a wiring area can be reduced, and the miniaturization of the packaging structure in the horizontal direction is facilitated.
Referring to fig. 2, 3 and 7, in the present embodiment, the interposer 300 includes a board body 301, where the board body 301 has a first surface and a second surface opposite to each other, the first surface and the second surface are two surfaces with the largest area among the surfaces of the board body, respectively, and the first surface is perpendicular to the first interconnect structure layer 500; the second surface is perpendicular to the first interconnect structure layer 500.
The first surface has a first bottom side, the first surface is provided with a plurality of first bottom side pins 3021 on one side of the first bottom side, and the plurality of first bottom side pins 3021 are connected to the first metal layer 501; the first bottom edge pins 3021 are also connected to the interposer metal layer.
The second surface has a second bottom side, a plurality of second bottom side pins 3022 are disposed on one side of the second bottom side of the second surface, and the plurality of second bottom side pins 3022 are connected to the first metal layer 501; the second bottom pins 3022 are also connected to the interposer metal layer.
The first bottom leg 3021 and the second bottom leg 3022 are connected to the first metal layer 501, and the plurality of first bottom legs 3021 and the plurality of second bottom legs 3022 are respectively connected to the interposer 300, so that on one hand, the interposer 300 is erected, and on the other hand, the first chip 100 and the second chip 200 on both sides of the interposer 300 are interconnected through the first metal layer 501 and the interposer 300. Compared with the interconnection mode of the planar interconnection line, the process of the wiring of the adapter plate 300 can realize higher precision and smaller line width and line distance than the processing process of the dense wiring of the planar interconnection line, so that the higher density and smaller occupied area than the planar interconnection line can be realized. In addition, because the adapter plate 300 is vertically arranged, part of the routing in the plane horizontal direction in the plane interconnection line is changed into the vertical direction, the area occupied by the wiring area can be reduced, and the miniaturization of the semiconductor packaging structure in the horizontal direction is facilitated.
In the present embodiment, the plurality of first bottom legs 3021 are arranged parallel to the first bottom side, and the plurality of second bottom legs 3022 are arranged parallel to the second bottom side. The pins arranged in parallel are easy to realize the welding balance, and the condition that the individual pins are disconnected due to unbalanced welding can be avoided.
In the present embodiment, the number of the first chips 100 may be plural; and/or the number of the second chips 200 may be plural.
Referring to fig. 8, in some other embodiments, the first surface is further provided with a plurality of contacts 303, the second surface is further provided with a plurality of contacts 303, and the interposer metal layer connects the plurality of contacts 303 of the first surface and the plurality of contacts 303 of the second surface. The first surface is provided with a third element 700, and the third element 700 is connected with the metal layer of the adapter plate through the contact 303 on the first surface; and/or the second surface is provided with a third element 700, and the third element 700 is connected with the metal layer of the adapter plate through the contact 303 of the second surface.
Specifically, the third element 700 may be a passive device or a chip.
The first surface and the second surface are provided with a plurality of connecting points for connecting the adapter plate metal layers, the first surface and/or the second surface of the adapter plate can be provided with a third element 700, the third element 700 is connected with the adapter plate metal layers through the connecting points 303, interconnection with other elements in the packaging structure and fan-out on the same side can be realized, and the integration level of the device is improved.
Example 2
Referring to fig. 1 to 7, the present embodiment provides a method for manufacturing a semiconductor package structure, including the steps of:
forming the molding layer 400.
Forming a first interconnect structure layer 500, wherein the first interconnect structure layer 500 is located on one side surface of the plastic package layer 400, and the first interconnect structure layer 500 includes a first metal layer 501 and a first insulating dielectric layer 502.
The interposer 300 is disposed, the interposer 300 is located in the plastic package layer 400, a plane of the interposer 300 extending itself is perpendicular to the first interconnect structure layer 500, an interposer metal layer is disposed in the interposer 300, and the interposer metal layer is connected to the first metal layer 501.
And mounting the first chip 100, wherein the first chip 100 is located on the surface of the first interconnect structure layer 500 facing the molding compound layer 400, the first chip 100 is connected to the first metal layer 501, and the molding compound layer 400 covers the first chip 100.
And mounting the second chip 200, wherein the second chip 200 is positioned on the surface of the first interconnection structure layer 500 facing the side of the plastic package layer 400, the second chip 200 is connected with the first metal layer 501, and the plastic package layer 400 covers the second chip 200.
The first chip 100 and the second chip 200 are different kinds of chips, and the first chip 100 and the second chip 200 are respectively located on two sides of the interposer 300.
For example, the first chip 100 and the second chip 200 may be a Field Programmable Gate Array (FPGA) chip and a double data rate synchronous dynamic random access memory (DDR) chip, respectively.
In this embodiment, the interposer 300 includes a board body 301, where the board body 301 has a first surface and a second surface opposite to each other, and the first surface and the second surface are two surfaces with the largest area in the respective surfaces of the board body 301, respectively, the first surface is perpendicular to the first interconnection structure layer 500, and the second surface is perpendicular to the first interconnection structure layer 500.
In the manufacturing method of the semiconductor package structure provided in this embodiment, the interposer 300 is perpendicular to the first interconnect structure layer 500, so that the interposer 300 is vertically disposed in the plastic package layer 400 on the first interconnect structure layer 500, and the first chip 100 and the second chip 200 on two sides of the interposer 300 are interconnected through the first metal layer 501 and the interposer 300. Compared with the interconnection mode of the planar interconnection line, the process of the wiring of the adapter plate 300 can realize higher precision and smaller line width and line distance than the processing process of the dense wiring of the planar interconnection line, so that the higher density and smaller occupied area than the planar interconnection line can be realized. In addition, because the adapter plate 300 is vertically arranged, part of the routing in the plane horizontal direction in the plane interconnection line is changed into the vertical direction, the occupied area of a wiring area can be reduced, and the miniaturization of the packaging structure in the horizontal direction is facilitated.
In this embodiment, the first surface has a first bottom edge, and the method for manufacturing the semiconductor package structure further includes the following steps: a plurality of first bottom side pins 3021 are formed on one side of the first bottom side of the first surface, and the plurality of first bottom side pins 3021 are connected to the first metal layer 501; the first bottom pins 3021 are also connected to the metal layer of the adapter board,
The second surface has a second bottom edge, and the manufacturing method of the semiconductor packaging structure further comprises the following steps: a plurality of second bottom side pins 3022 are formed on the second bottom side of the second surface, and the plurality of second bottom side pins 3022 are connected to the first metal layer 501. The second bottom pins 3022 are also connected to the interposer metal layer.
By forming a plurality of first bottom pins 3021 and a plurality of second bottom pins 3022, the first bottom pins 3021 and the second bottom pins 3022 are connected to the first metal layer 501, and the interposer metal layer connects the plurality of first bottom pins 3021 and the plurality of second bottom pins 3022, on the one hand, the riser of the interposer 300 is achieved, and on the other hand, the first chip 100 and the second chip 200 on both sides of the interposer 300 are interconnected through the first metal layer 501 and the interposer 300. Compared with the interconnection mode of the planar interconnection line, the process of the wiring of the adapter plate 300 can realize higher precision and smaller line width and line distance than the processing process of the dense wiring of the planar interconnection line, so that the higher density and smaller occupied area than the planar interconnection line can be realized. In addition, because the adapter plate 300 is vertically arranged, part of the routing in the plane horizontal direction in the plane interconnection line is changed into the vertical direction, the area occupied by the routing area can be reduced, and the miniaturization of the semiconductor packaging structure in the horizontal direction is facilitated
In this embodiment, the method for manufacturing a semiconductor package structure sequentially comprises the following steps:
referring to fig. 1, a substrate 0001 is provided, and a plurality of metal bumps 0002 are formed on the substrate 0001.
Referring to fig. 2, a plurality of first bottom leg 3021 and a plurality of second bottom leg 3022 of the interposer 300 are soldered to the first substrate 0001 by a plurality of metal bumps 0002.
Referring to fig. 4, the first chip 100 and the second chip 200 are respectively mounted to a substrate 0001.
Referring to fig. 5, a molding compound layer 400 is formed, and the molding compound layer 400 encapsulates the first chip 100, the second chip 200, and the interposer 300.
Referring to fig. 6, the substrate 0001 is removed.
Referring to fig. 7, a first interconnect structure layer 500 is formed, where the first interconnect structure layer 500 covers a surface of the first chip 100 facing the substrate 0001 side, a surface of the interposer 300 facing the substrate 0001 side, and a surface of the molding layer 400 facing the substrate 0001 side.
With continued reference to fig. 7, solder balls 600 are formed on the side of the first interconnect structure layer 500 opposite to the molding compound layer 400, and the solder balls 600 are connected to the first metal layer.
Referring to fig. 8, in some other embodiments, the method for manufacturing the semiconductor package structure further includes the steps of:
a plurality of contacts 303 are formed on the first surface and a plurality of contacts 303 are formed on the second surface, and the interposer metal layer connects the plurality of contacts 303 on the first surface and the plurality of contacts 303 on the second surface.
Attaching the third element 700 to the first surface, wherein the third element 700 is connected with the metal layer of the adapter plate through the contact 303 on the first surface; and/or the presence of a gas in the gas,
the third component 700 is attached to the second surface and the third component 700 is connected to the interposer metal layer by the contacts 303 of the second surface.
By forming a plurality of contacts 303 on the interposer 300, a third element 700 may be further disposed on the first surface and/or the second surface of the interposer 300, and the third element 700 is connected to the interposer metal layer through the contacts 303, so that interconnection with other elements in the package structure and fan-out on the same side may be achieved, which is beneficial to improving the integration of the device.
Example 3
The present embodiment provides a semiconductor device including the semiconductor package structure in embodiment 1 described above. Through the setting of the keysets perpendicular to the first interconnection structure layer for the keysets vertically arranges in the plastic envelope layer on the first interconnection structure layer, and the first chip and the second chip of keysets both sides have realized the interconnection through first metal level and keysets. Compared with the interconnection mode of the planar interconnection line, the process of the patch panel wiring can realize higher precision and smaller line width and line distance than the processing process of dense wiring of the planar interconnection line, so that the process can realize higher density and occupy smaller area than the planar interconnection line. In addition, because the adapter plate is vertically arranged, the routing of part of the plane interconnection line in the plane horizontal direction is changed into the vertical direction, the occupied area of a wiring area can be reduced, and the miniaturization of the packaging structure in the horizontal direction is facilitated.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. A semiconductor package structure, comprising:
a plastic packaging layer;
the first interconnection structure layer is positioned on one side surface of the plastic packaging layer and comprises a first metal layer;
the adapter plate is positioned in the plastic package layer, the plane extending by the adapter plate is perpendicular to the first interconnection structure layer, an adapter plate metal layer is arranged in the adapter plate, and the adapter plate metal layer is connected with the first metal layer;
the first chip is positioned on the surface of one side, facing the plastic package layer, of the first interconnection structure layer, the first chip is connected with the first metal layer, and the plastic package layer coats the first chip;
the second chip is positioned on the surface of one side, facing the plastic packaging layer, of the first interconnection structure layer, is connected with the first metal layer, and wraps the second chip;
the first chip and the second chip are different types of chips, and the first chip and the second chip are respectively located on two sides of the adapter plate.
2. The semiconductor package structure of claim 1,
the adapter plate comprises a plate body, wherein the plate body is provided with a first surface and a second surface which are opposite to each other, the first surface and the second surface are two surfaces with the largest area in the surfaces of the plate body respectively, and the first surface is perpendicular to the first interconnection structure layer; the second surface is perpendicular to the first interconnection structure layer;
the first surface is provided with a first bottom edge, a plurality of first bottom edge connecting pins are arranged on one side of the first bottom edge of the first surface, and the first bottom edge connecting pins are connected with the first metal layer; the first bottom edge pins are also connected with the adapter plate metal layer;
the second surface is provided with a second bottom edge, a plurality of second bottom edge connecting pins are arranged on one side of the second bottom edge of the second surface, and the second bottom edge connecting pins are connected with the first metal layer; the second bottom edge connecting pins are also connected with the adapter plate metal layer.
3. The semiconductor package structure of claim 2, wherein:
the plurality of first bottom edge connecting pins are arranged in parallel to the first bottom edge, and the plurality of second bottom edge connecting pins are arranged in parallel to the second bottom edge.
4. The semiconductor package structure of claim 1, further comprising:
the number of the first chips is multiple; and/or the number of the second chips is multiple.
5. The semiconductor package structure of claim 2 or 3,
the first surface is also provided with a plurality of joints, the second surface is also provided with a plurality of joints, and the adapter plate metal layer is connected with the joints of the first surface and the joints of the second surface;
the first surface is provided with a third element, and the third element is connected with the adapter plate metal layer through a contact of the first surface; and/or the presence of a gas in the gas,
the second surface is provided with a third element, and the third element is connected with the adapter plate metal layer through a contact of the second surface;
preferably, the third component is a passive device or a chip.
6. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
forming a plastic packaging layer;
forming a first interconnection structure layer, wherein the first interconnection structure layer is positioned on one side surface of the plastic packaging layer and comprises a first metal layer;
arranging an adapter plate, wherein the adapter plate is positioned in the plastic package layer, the plane extended by the adapter plate is vertical to the first interconnection structure layer, an adapter plate metal layer is arranged in the adapter plate, and the adapter plate metal layer is connected with the first metal layer;
mounting a first chip, wherein the first chip is positioned on the surface of one side, facing the plastic package layer, of the first interconnection structure layer, the first chip is connected with the first metal layer, and the plastic package layer coats the first chip;
mounting a second chip, wherein the second chip is positioned on the surface of one side, facing the plastic package layer, of the first interconnection structure layer, the second chip is connected with the first metal layer, and the plastic package layer coats the second chip;
the first chip and the second chip are different types of chips, and the first chip and the second chip are respectively located on two sides of the adapter plate.
7. The method of manufacturing a semiconductor package structure of claim 6,
the adapter plate comprises a plate body, wherein the plate body is provided with a first surface and a second surface which are opposite to each other, the first surface and the second surface are two surfaces with the largest area in the surfaces of the plate body respectively, and the first surface is perpendicular to the first interconnection structure layer; the second surface is perpendicular to the first interconnection structure layer;
the first surface is provided with a first bottom edge, and the manufacturing method of the semiconductor packaging structure comprises the following steps: forming a plurality of first bottom edge pins on one side of the first bottom edge of the first surface, wherein the plurality of first bottom edge pins are connected with the first metal layer; the first bottom edge pins are also connected with the adapter plate metal layer;
the second surface has a second bottom edge, and the manufacturing method of the semiconductor packaging structure further comprises the following steps: forming a plurality of second bottom edge pins on one side of the second bottom edge of the second surface, wherein the plurality of second bottom edge pins are connected with the first metal layer; the second bottom edge connecting pins are also connected with the adapter plate metal layer.
8. The method of manufacturing a semiconductor package according to claim 7,
the manufacturing method of the semiconductor packaging structure sequentially comprises the following steps:
providing a substrate, and forming a plurality of metal bumps on the substrate;
welding a plurality of first bottom edge pins and a plurality of second bottom edge pins of the adapter plate to the substrate through the plurality of metal bumps;
respectively mounting the first chip and the second chip to the substrate;
forming the plastic packaging layer, wherein the first chip, the second chip and the adapter plate are coated by the plastic packaging layer;
removing the substrate;
forming a first interconnection structure layer, wherein the first interconnection structure layer covers the surface of the first chip facing to the substrate side before, the surface of the second chip facing to the substrate side before, the surface of the interposer facing to the substrate side before and the surface of the encapsulation layer facing to the substrate side before;
and forming a solder ball on one side of the first interconnection structure layer, which is back to the plastic packaging layer, wherein the solder ball is connected with the first metal layer.
9. The method for manufacturing the semiconductor package structure according to claim 7 or 8, further comprising the steps of:
forming a plurality of contacts on the first surface, forming a plurality of contacts on the second surface, and connecting the plurality of contacts on the first surface and the plurality of contacts on the second surface by the adapter plate metal layer;
attaching a third element to the first surface, wherein the third element is connected with the adapter plate metal layer through a contact of the first surface; and/or the presence of a gas in the gas,
and attaching a third element to the second surface, wherein the third element is connected with the adapter plate metal layer through the contact point of the second surface.
10. A semiconductor device, comprising:
a semiconductor package structure of any one of claims 1-5.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110117983.7A CN112908971A (en) | 2021-01-28 | 2021-01-28 | Semiconductor packaging structure, manufacturing method thereof and semiconductor device |
| PCT/CN2021/079315 WO2022160415A1 (en) | 2021-01-28 | 2021-03-05 | Semiconductor package structure and manufacturing method therefor, and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110117983.7A CN112908971A (en) | 2021-01-28 | 2021-01-28 | Semiconductor packaging structure, manufacturing method thereof and semiconductor device |
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| CN112908971A true CN112908971A (en) | 2021-06-04 |
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|---|---|---|---|
| CN202110117983.7A Withdrawn CN112908971A (en) | 2021-01-28 | 2021-01-28 | Semiconductor packaging structure, manufacturing method thereof and semiconductor device |
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| CN (1) | CN112908971A (en) |
| WO (1) | WO2022160415A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113257782A (en) * | 2021-07-14 | 2021-08-13 | 北京壁仞科技开发有限公司 | Semiconductor packaging structure and packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6392896B1 (en) * | 1999-12-22 | 2002-05-21 | International Business Machines Corporation | Semiconductor package containing multiple memory units |
| KR101321282B1 (en) * | 2011-06-17 | 2013-10-28 | 삼성전기주식회사 | Power module package and system module having the same |
| US10163687B2 (en) * | 2015-05-22 | 2018-12-25 | Qualcomm Incorporated | System, apparatus, and method for embedding a 3D component with an interconnect structure |
| CN106340513B (en) * | 2015-07-09 | 2019-03-15 | 台达电子工业股份有限公司 | Power module of integrated control circuit |
-
2021
- 2021-01-28 CN CN202110117983.7A patent/CN112908971A/en not_active Withdrawn
- 2021-03-05 WO PCT/CN2021/079315 patent/WO2022160415A1/en active Application Filing
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113257782A (en) * | 2021-07-14 | 2021-08-13 | 北京壁仞科技开发有限公司 | Semiconductor packaging structure and packaging method |
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| WO2022160415A1 (en) | 2022-08-04 |
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